1/*****************************************************************************
2 *                                                                           *
3 * File: common.h                                                            *
4 * $Revision: 1.21 $                                                         *
5 * $Date: 2005/06/22 00:43:25 $                                              *
6 * Description:                                                              *
7 *  part of the Chelsio 10Gb Ethernet Driver.                                *
8 *                                                                           *
9 * This program is free software; you can redistribute it and/or modify      *
10 * it under the terms of the GNU General Public License, version 2, as       *
11 * published by the Free Software Foundation.                                *
12 *                                                                           *
13 * You should have received a copy of the GNU General Public License along   *
14 * with this program; if not, see <http://www.gnu.org/licenses/>.            *
15 *                                                                           *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
17 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
19 *                                                                           *
20 * http://www.chelsio.com                                                    *
21 *                                                                           *
22 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
23 * All rights reserved.                                                      *
24 *                                                                           *
25 * Maintainers: maintainers@chelsio.com                                      *
26 *                                                                           *
27 * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
28 *          Tina Yang               <tainay@chelsio.com>                     *
29 *          Felix Marti             <felix@chelsio.com>                      *
30 *          Scott Bardone           <sbardone@chelsio.com>                   *
31 *          Kurt Ottaway            <kottaway@chelsio.com>                   *
32 *          Frank DiMambro          <frank@chelsio.com>                      *
33 *                                                                           *
34 * History:                                                                  *
35 *                                                                           *
36 ****************************************************************************/
37
38#define pr_fmt(fmt) "cxgb: " fmt
39
40#ifndef _CXGB_COMMON_H_
41#define _CXGB_COMMON_H_
42
43#include <linux/module.h>
44#include <linux/netdevice.h>
45#include <linux/types.h>
46#include <linux/delay.h>
47#include <linux/pci.h>
48#include <linux/ethtool.h>
49#include <linux/if_vlan.h>
50#include <linux/mdio.h>
51#include <linux/crc32.h>
52#include <linux/slab.h>
53#include <asm/io.h>
54#include <linux/pci_ids.h>
55
56#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
57#define DRV_NAME "cxgb"
58#define DRV_VERSION "2.2"
59
60#define CH_DEVICE(devid, ssid, idx) \
61	{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
62
63#define SUPPORTED_PAUSE       (1 << 13)
64#define SUPPORTED_LOOPBACK    (1 << 15)
65
66#define ADVERTISED_PAUSE      (1 << 13)
67#define ADVERTISED_ASYM_PAUSE (1 << 14)
68
69typedef struct adapter adapter_t;
70
71struct t1_rx_mode {
72       struct net_device *dev;
73};
74
75#define t1_rx_mode_promisc(rm)	(rm->dev->flags & IFF_PROMISC)
76#define t1_rx_mode_allmulti(rm)	(rm->dev->flags & IFF_ALLMULTI)
77#define t1_rx_mode_mc_cnt(rm)	(netdev_mc_count(rm->dev))
78#define t1_get_netdev(rm)	(rm->dev)
79
80#define	MAX_NPORTS 4
81#define PORT_MASK ((1 << MAX_NPORTS) - 1)
82#define NMTUS      8
83#define TCB_SIZE   128
84
85#define SPEED_INVALID 0xffff
86#define DUPLEX_INVALID 0xff
87
88enum {
89	CHBT_BOARD_N110,
90	CHBT_BOARD_N210,
91	CHBT_BOARD_7500,
92	CHBT_BOARD_8000,
93	CHBT_BOARD_CHT101,
94	CHBT_BOARD_CHT110,
95	CHBT_BOARD_CHT210,
96	CHBT_BOARD_CHT204,
97	CHBT_BOARD_CHT204V,
98	CHBT_BOARD_CHT204E,
99	CHBT_BOARD_CHN204,
100	CHBT_BOARD_COUGAR,
101	CHBT_BOARD_6800,
102	CHBT_BOARD_SIMUL,
103};
104
105enum {
106	CHBT_TERM_FPGA,
107	CHBT_TERM_T1,
108	CHBT_TERM_T2,
109	CHBT_TERM_T3
110};
111
112enum {
113	CHBT_MAC_CHELSIO_A,
114	CHBT_MAC_IXF1010,
115	CHBT_MAC_PM3393,
116	CHBT_MAC_VSC7321,
117	CHBT_MAC_DUMMY
118};
119
120enum {
121	CHBT_PHY_88E1041,
122	CHBT_PHY_88E1111,
123	CHBT_PHY_88X2010,
124	CHBT_PHY_XPAK,
125	CHBT_PHY_MY3126,
126	CHBT_PHY_8244,
127	CHBT_PHY_DUMMY
128};
129
130enum {
131	PAUSE_RX      = 1 << 0,
132	PAUSE_TX      = 1 << 1,
133	PAUSE_AUTONEG = 1 << 2
134};
135
136/* Revisions of T1 chip */
137enum {
138	TERM_T1A   = 0,
139	TERM_T1B   = 1,
140	TERM_T2    = 3
141};
142
143struct sge_params {
144	unsigned int cmdQ_size[2];
145	unsigned int freelQ_size[2];
146	unsigned int large_buf_capacity;
147	unsigned int rx_coalesce_usecs;
148	unsigned int last_rx_coalesce_raw;
149	unsigned int default_rx_coalesce_usecs;
150	unsigned int sample_interval_usecs;
151	unsigned int coalesce_enable;
152	unsigned int polling;
153};
154
155struct chelsio_pci_params {
156	unsigned short speed;
157	unsigned char  width;
158	unsigned char  is_pcix;
159};
160
161struct tp_params {
162	unsigned int pm_size;
163	unsigned int cm_size;
164	unsigned int pm_rx_base;
165	unsigned int pm_tx_base;
166	unsigned int pm_rx_pg_size;
167	unsigned int pm_tx_pg_size;
168	unsigned int pm_rx_num_pgs;
169	unsigned int pm_tx_num_pgs;
170	unsigned int rx_coalescing_size;
171	unsigned int use_5tuple_mode;
172};
173
174struct mc5_params {
175	unsigned int mode;       /* selects MC5 width */
176	unsigned int nservers;   /* size of server region */
177	unsigned int nroutes;    /* size of routing region */
178};
179
180/* Default MC5 region sizes */
181#define DEFAULT_SERVER_REGION_LEN 256
182#define DEFAULT_RT_REGION_LEN 1024
183
184struct adapter_params {
185	struct sge_params sge;
186	struct mc5_params mc5;
187	struct tp_params  tp;
188	struct chelsio_pci_params pci;
189
190	const struct board_info *brd_info;
191
192	unsigned short mtus[NMTUS];
193	unsigned int   nports;          /* # of ethernet ports */
194	unsigned int   stats_update_period;
195	unsigned short chip_revision;
196	unsigned char  chip_version;
197	unsigned char  is_asic;
198	unsigned char  has_msi;
199};
200
201struct link_config {
202	unsigned int   supported;        /* link capabilities */
203	unsigned int   advertising;      /* advertised capabilities */
204	unsigned short requested_speed;  /* speed user has requested */
205	unsigned short speed;            /* actual link speed */
206	unsigned char  requested_duplex; /* duplex user has requested */
207	unsigned char  duplex;           /* actual link duplex */
208	unsigned char  requested_fc;     /* flow control user has requested */
209	unsigned char  fc;               /* actual link flow control */
210	unsigned char  autoneg;          /* autonegotiating? */
211};
212
213struct cmac;
214struct cphy;
215
216struct port_info {
217	struct net_device *dev;
218	struct cmac *mac;
219	struct cphy *phy;
220	struct link_config link_config;
221	struct net_device_stats netstats;
222};
223
224struct sge;
225struct peespi;
226
227struct adapter {
228	u8 __iomem *regs;
229	struct pci_dev *pdev;
230	unsigned long registered_device_map;
231	unsigned long open_device_map;
232	unsigned long flags;
233
234	const char *name;
235	int msg_enable;
236	u32 mmio_len;
237
238	struct work_struct ext_intr_handler_task;
239	struct adapter_params params;
240
241	/* Terminator modules. */
242	struct sge    *sge;
243	struct peespi *espi;
244	struct petp   *tp;
245
246	struct napi_struct napi;
247	struct port_info port[MAX_NPORTS];
248	struct delayed_work stats_update_task;
249	struct timer_list stats_update_timer;
250
251	spinlock_t tpi_lock;
252	spinlock_t work_lock;
253	spinlock_t mac_lock;
254
255	/* guards async operations */
256	spinlock_t async_lock ____cacheline_aligned;
257	u32 slow_intr_mask;
258	int t1powersave;
259};
260
261enum {                                           /* adapter flags */
262	FULL_INIT_DONE        = 1 << 0,
263};
264
265struct mdio_ops;
266struct gmac;
267struct gphy;
268
269struct board_info {
270	unsigned char           board;
271	unsigned char           port_number;
272	unsigned long           caps;
273	unsigned char           chip_term;
274	unsigned char           chip_mac;
275	unsigned char           chip_phy;
276	unsigned int            clock_core;
277	unsigned int            clock_mc3;
278	unsigned int            clock_mc4;
279	unsigned int            espi_nports;
280	unsigned int            clock_elmer0;
281	unsigned char           mdio_mdien;
282	unsigned char           mdio_mdiinv;
283	unsigned char           mdio_mdc;
284	unsigned char           mdio_phybaseaddr;
285	const struct gmac      *gmac;
286	const struct gphy      *gphy;
287	const struct mdio_ops  *mdio_ops;
288	const char             *desc;
289};
290
291static inline int t1_is_asic(const adapter_t *adapter)
292{
293	return adapter->params.is_asic;
294}
295
296extern const struct pci_device_id t1_pci_tbl[];
297
298static inline int adapter_matches_type(const adapter_t *adapter,
299				       int version, int revision)
300{
301	return adapter->params.chip_version == version &&
302	       adapter->params.chip_revision == revision;
303}
304
305#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
306#define is_T2(adap)     adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
307
308/* Returns true if an adapter supports VLAN acceleration and TSO */
309static inline int vlan_tso_capable(const adapter_t *adapter)
310{
311	return !t1_is_T1B(adapter);
312}
313
314#define for_each_port(adapter, iter) \
315	for (iter = 0; iter < (adapter)->params.nports; ++iter)
316
317#define board_info(adapter) ((adapter)->params.brd_info)
318#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
319
320static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
321{
322	return board_info(adap)->clock_core / 1000000;
323}
324
325int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
326int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
327int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
328int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
329
330void t1_interrupts_enable(adapter_t *adapter);
331void t1_interrupts_disable(adapter_t *adapter);
332void t1_interrupts_clear(adapter_t *adapter);
333int t1_elmer0_ext_intr_handler(adapter_t *adapter);
334void t1_elmer0_ext_intr(adapter_t *adapter);
335int t1_slow_intr_handler(adapter_t *adapter);
336
337int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
338const struct board_info *t1_get_board_info(unsigned int board_id);
339const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
340						    unsigned short ssid);
341int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
342int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
343		     struct adapter_params *p);
344int t1_init_hw_modules(adapter_t *adapter);
345int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
346void t1_free_sw_modules(adapter_t *adapter);
347void t1_fatal_err(adapter_t *adapter);
348void t1_link_changed(adapter_t *adapter, int port_id);
349void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
350			    int speed, int duplex, int pause);
351#endif /* _CXGB_COMMON_H_ */
352