1#define A_SG_CONTROL 0x0
2
3#define S_CONGMODE    29
4#define V_CONGMODE(x) ((x) << S_CONGMODE)
5#define F_CONGMODE    V_CONGMODE(1U)
6
7#define S_TNLFLMODE    28
8#define V_TNLFLMODE(x) ((x) << S_TNLFLMODE)
9#define F_TNLFLMODE    V_TNLFLMODE(1U)
10
11#define S_FATLPERREN    27
12#define V_FATLPERREN(x) ((x) << S_FATLPERREN)
13#define F_FATLPERREN    V_FATLPERREN(1U)
14
15#define S_DROPPKT    20
16#define V_DROPPKT(x) ((x) << S_DROPPKT)
17#define F_DROPPKT    V_DROPPKT(1U)
18
19#define S_EGRGENCTRL    19
20#define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
21#define F_EGRGENCTRL    V_EGRGENCTRL(1U)
22
23#define S_USERSPACESIZE    14
24#define M_USERSPACESIZE    0x1f
25#define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
26
27#define S_HOSTPAGESIZE    11
28#define M_HOSTPAGESIZE    0x7
29#define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
30
31#define S_FLMODE    9
32#define V_FLMODE(x) ((x) << S_FLMODE)
33#define F_FLMODE    V_FLMODE(1U)
34
35#define S_PKTSHIFT    6
36#define M_PKTSHIFT    0x7
37#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
38
39#define S_ONEINTMULTQ    5
40#define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
41#define F_ONEINTMULTQ    V_ONEINTMULTQ(1U)
42
43#define S_BIGENDIANINGRESS    2
44#define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
45#define F_BIGENDIANINGRESS    V_BIGENDIANINGRESS(1U)
46
47#define S_ISCSICOALESCING    1
48#define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
49#define F_ISCSICOALESCING    V_ISCSICOALESCING(1U)
50
51#define S_GLOBALENABLE    0
52#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
53#define F_GLOBALENABLE    V_GLOBALENABLE(1U)
54
55#define S_AVOIDCQOVFL    24
56#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
57#define F_AVOIDCQOVFL    V_AVOIDCQOVFL(1U)
58
59#define S_OPTONEINTMULTQ    23
60#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
61#define F_OPTONEINTMULTQ    V_OPTONEINTMULTQ(1U)
62
63#define S_CQCRDTCTRL    22
64#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
65#define F_CQCRDTCTRL    V_CQCRDTCTRL(1U)
66
67#define A_SG_KDOORBELL 0x4
68
69#define S_SELEGRCNTX    31
70#define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
71#define F_SELEGRCNTX    V_SELEGRCNTX(1U)
72
73#define S_EGRCNTX    0
74#define M_EGRCNTX    0xffff
75#define V_EGRCNTX(x) ((x) << S_EGRCNTX)
76
77#define A_SG_GTS 0x8
78
79#define S_RSPQ    29
80#define M_RSPQ    0x7
81#define V_RSPQ(x) ((x) << S_RSPQ)
82#define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
83
84#define S_NEWTIMER    16
85#define M_NEWTIMER    0x1fff
86#define V_NEWTIMER(x) ((x) << S_NEWTIMER)
87
88#define S_NEWINDEX    0
89#define M_NEWINDEX    0xffff
90#define V_NEWINDEX(x) ((x) << S_NEWINDEX)
91
92#define A_SG_CONTEXT_CMD 0xc
93
94#define S_CONTEXT_CMD_OPCODE    28
95#define M_CONTEXT_CMD_OPCODE    0xf
96#define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
97
98#define S_CONTEXT_CMD_BUSY    27
99#define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
100#define F_CONTEXT_CMD_BUSY    V_CONTEXT_CMD_BUSY(1U)
101
102#define S_CQ_CREDIT    20
103
104#define M_CQ_CREDIT    0x7f
105
106#define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
107
108#define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
109
110#define S_CQ    19
111
112#define V_CQ(x) ((x) << S_CQ)
113#define F_CQ    V_CQ(1U)
114
115#define S_RESPONSEQ    18
116#define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
117#define F_RESPONSEQ    V_RESPONSEQ(1U)
118
119#define S_EGRESS    17
120#define V_EGRESS(x) ((x) << S_EGRESS)
121#define F_EGRESS    V_EGRESS(1U)
122
123#define S_FREELIST    16
124#define V_FREELIST(x) ((x) << S_FREELIST)
125#define F_FREELIST    V_FREELIST(1U)
126
127#define S_CONTEXT    0
128#define M_CONTEXT    0xffff
129#define V_CONTEXT(x) ((x) << S_CONTEXT)
130
131#define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
132
133#define A_SG_CONTEXT_DATA0 0x10
134
135#define A_SG_CONTEXT_DATA1 0x14
136
137#define A_SG_CONTEXT_DATA2 0x18
138
139#define A_SG_CONTEXT_DATA3 0x1c
140
141#define A_SG_CONTEXT_MASK0 0x20
142
143#define A_SG_CONTEXT_MASK1 0x24
144
145#define A_SG_CONTEXT_MASK2 0x28
146
147#define A_SG_CONTEXT_MASK3 0x2c
148
149#define A_SG_RSPQ_CREDIT_RETURN 0x30
150
151#define S_CREDITS    0
152#define M_CREDITS    0xffff
153#define V_CREDITS(x) ((x) << S_CREDITS)
154
155#define A_SG_DATA_INTR 0x34
156
157#define S_ERRINTR    31
158#define V_ERRINTR(x) ((x) << S_ERRINTR)
159#define F_ERRINTR    V_ERRINTR(1U)
160
161#define A_SG_HI_DRB_HI_THRSH 0x38
162
163#define A_SG_HI_DRB_LO_THRSH 0x3c
164
165#define A_SG_LO_DRB_HI_THRSH 0x40
166
167#define A_SG_LO_DRB_LO_THRSH 0x44
168
169#define A_SG_RSPQ_FL_STATUS 0x4c
170
171#define S_RSPQ0DISABLED    8
172
173#define S_FL0EMPTY    16
174#define V_FL0EMPTY(x) ((x) << S_FL0EMPTY)
175#define F_FL0EMPTY    V_FL0EMPTY(1U)
176
177#define A_SG_EGR_RCQ_DRB_THRSH 0x54
178
179#define S_HIRCQDRBTHRSH    16
180#define M_HIRCQDRBTHRSH    0x7ff
181#define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
182
183#define S_LORCQDRBTHRSH    0
184#define M_LORCQDRBTHRSH    0x7ff
185#define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
186
187#define A_SG_EGR_CNTX_BADDR 0x58
188
189#define A_SG_INT_CAUSE 0x5c
190
191#define S_HIRCQPARITYERROR    31
192#define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR)
193#define F_HIRCQPARITYERROR    V_HIRCQPARITYERROR(1U)
194
195#define S_LORCQPARITYERROR    30
196#define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR)
197#define F_LORCQPARITYERROR    V_LORCQPARITYERROR(1U)
198
199#define S_HIDRBPARITYERROR    29
200#define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR)
201#define F_HIDRBPARITYERROR    V_HIDRBPARITYERROR(1U)
202
203#define S_LODRBPARITYERROR    28
204#define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR)
205#define F_LODRBPARITYERROR    V_LODRBPARITYERROR(1U)
206
207#define S_FLPARITYERROR    22
208#define M_FLPARITYERROR    0x3f
209#define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR)
210#define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR)
211
212#define S_ITPARITYERROR    20
213#define M_ITPARITYERROR    0x3
214#define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR)
215#define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR)
216
217#define S_IRPARITYERROR    19
218#define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR)
219#define F_IRPARITYERROR    V_IRPARITYERROR(1U)
220
221#define S_RCPARITYERROR    18
222#define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR)
223#define F_RCPARITYERROR    V_RCPARITYERROR(1U)
224
225#define S_OCPARITYERROR    17
226#define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR)
227#define F_OCPARITYERROR    V_OCPARITYERROR(1U)
228
229#define S_CPPARITYERROR    16
230#define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR)
231#define F_CPPARITYERROR    V_CPPARITYERROR(1U)
232
233#define S_R_REQ_FRAMINGERROR    15
234#define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR)
235#define F_R_REQ_FRAMINGERROR    V_R_REQ_FRAMINGERROR(1U)
236
237#define S_UC_REQ_FRAMINGERROR    14
238#define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR)
239#define F_UC_REQ_FRAMINGERROR    V_UC_REQ_FRAMINGERROR(1U)
240
241#define S_HICTLDRBDROPERR    13
242#define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)
243#define F_HICTLDRBDROPERR    V_HICTLDRBDROPERR(1U)
244
245#define S_LOCTLDRBDROPERR    12
246#define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)
247#define F_LOCTLDRBDROPERR    V_LOCTLDRBDROPERR(1U)
248
249#define S_HIPIODRBDROPERR    11
250#define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
251#define F_HIPIODRBDROPERR    V_HIPIODRBDROPERR(1U)
252
253#define S_LOPIODRBDROPERR    10
254#define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
255#define F_LOPIODRBDROPERR    V_LOPIODRBDROPERR(1U)
256
257#define S_HIPRIORITYDBFULL    7
258#define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL)
259#define F_HIPRIORITYDBFULL    V_HIPRIORITYDBFULL(1U)
260
261#define S_HIPRIORITYDBEMPTY   6
262#define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY)
263#define F_HIPRIORITYDBEMPTY    V_HIPRIORITYDBEMPTY(1U)
264
265#define S_LOPRIORITYDBFULL    5
266#define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL)
267#define F_LOPRIORITYDBFULL    V_LOPRIORITYDBFULL(1U)
268
269#define S_LOPRIORITYDBEMPTY   4
270#define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY)
271#define F_LOPRIORITYDBEMPTY    V_LOPRIORITYDBEMPTY(1U)
272
273#define S_RSPQDISABLED    3
274#define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
275#define F_RSPQDISABLED    V_RSPQDISABLED(1U)
276
277#define S_RSPQCREDITOVERFOW    2
278#define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
279#define F_RSPQCREDITOVERFOW    V_RSPQCREDITOVERFOW(1U)
280
281#define S_FLEMPTY    1
282#define V_FLEMPTY(x) ((x) << S_FLEMPTY)
283#define F_FLEMPTY    V_FLEMPTY(1U)
284
285#define A_SG_INT_ENABLE 0x60
286
287#define A_SG_CMDQ_CREDIT_TH 0x64
288
289#define S_TIMEOUT    8
290#define M_TIMEOUT    0xffffff
291#define V_TIMEOUT(x) ((x) << S_TIMEOUT)
292
293#define S_THRESHOLD    0
294#define M_THRESHOLD    0xff
295#define V_THRESHOLD(x) ((x) << S_THRESHOLD)
296
297#define A_SG_TIMER_TICK 0x68
298
299#define A_SG_CQ_CONTEXT_BADDR 0x6c
300
301#define A_SG_OCO_BASE 0x70
302
303#define S_BASE1    16
304#define M_BASE1    0xffff
305#define V_BASE1(x) ((x) << S_BASE1)
306
307#define A_SG_DRB_PRI_THRESH 0x74
308
309#define A_PCIX_INT_ENABLE 0x80
310
311#define S_MSIXPARERR    22
312#define M_MSIXPARERR    0x7
313
314#define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
315
316#define S_CFPARERR    18
317#define M_CFPARERR    0xf
318
319#define V_CFPARERR(x) ((x) << S_CFPARERR)
320
321#define S_RFPARERR    14
322#define M_RFPARERR    0xf
323
324#define V_RFPARERR(x) ((x) << S_RFPARERR)
325
326#define S_WFPARERR    12
327#define M_WFPARERR    0x3
328
329#define V_WFPARERR(x) ((x) << S_WFPARERR)
330
331#define S_PIOPARERR    11
332#define V_PIOPARERR(x) ((x) << S_PIOPARERR)
333#define F_PIOPARERR    V_PIOPARERR(1U)
334
335#define S_DETUNCECCERR    10
336#define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
337#define F_DETUNCECCERR    V_DETUNCECCERR(1U)
338
339#define S_DETCORECCERR    9
340#define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
341#define F_DETCORECCERR    V_DETCORECCERR(1U)
342
343#define S_RCVSPLCMPERR    8
344#define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
345#define F_RCVSPLCMPERR    V_RCVSPLCMPERR(1U)
346
347#define S_UNXSPLCMP    7
348#define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
349#define F_UNXSPLCMP    V_UNXSPLCMP(1U)
350
351#define S_SPLCMPDIS    6
352#define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
353#define F_SPLCMPDIS    V_SPLCMPDIS(1U)
354
355#define S_DETPARERR    5
356#define V_DETPARERR(x) ((x) << S_DETPARERR)
357#define F_DETPARERR    V_DETPARERR(1U)
358
359#define S_SIGSYSERR    4
360#define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
361#define F_SIGSYSERR    V_SIGSYSERR(1U)
362
363#define S_RCVMSTABT    3
364#define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
365#define F_RCVMSTABT    V_RCVMSTABT(1U)
366
367#define S_RCVTARABT    2
368#define V_RCVTARABT(x) ((x) << S_RCVTARABT)
369#define F_RCVTARABT    V_RCVTARABT(1U)
370
371#define S_SIGTARABT    1
372#define V_SIGTARABT(x) ((x) << S_SIGTARABT)
373#define F_SIGTARABT    V_SIGTARABT(1U)
374
375#define S_MSTDETPARERR    0
376#define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
377#define F_MSTDETPARERR    V_MSTDETPARERR(1U)
378
379#define A_PCIX_INT_CAUSE 0x84
380
381#define A_PCIX_CFG 0x88
382
383#define S_DMASTOPEN    19
384#define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
385#define F_DMASTOPEN    V_DMASTOPEN(1U)
386
387#define S_CLIDECEN    18
388#define V_CLIDECEN(x) ((x) << S_CLIDECEN)
389#define F_CLIDECEN    V_CLIDECEN(1U)
390
391#define A_PCIX_MODE 0x8c
392
393#define S_PCLKRANGE    6
394#define M_PCLKRANGE    0x3
395#define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
396#define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
397
398#define S_PCIXINITPAT    2
399#define M_PCIXINITPAT    0xf
400#define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
401#define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
402
403#define S_64BIT    0
404#define V_64BIT(x) ((x) << S_64BIT)
405#define F_64BIT    V_64BIT(1U)
406
407#define A_PCIE_INT_ENABLE 0x80
408
409#define S_BISTERR    15
410#define M_BISTERR    0xff
411
412#define V_BISTERR(x) ((x) << S_BISTERR)
413
414#define S_TXPARERR    18
415#define V_TXPARERR(x) ((x) << S_TXPARERR)
416#define F_TXPARERR    V_TXPARERR(1U)
417
418#define S_RXPARERR    17
419#define V_RXPARERR(x) ((x) << S_RXPARERR)
420#define F_RXPARERR    V_RXPARERR(1U)
421
422#define S_RETRYLUTPARERR    16
423#define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR)
424#define F_RETRYLUTPARERR    V_RETRYLUTPARERR(1U)
425
426#define S_RETRYBUFPARERR    15
427#define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR)
428#define F_RETRYBUFPARERR    V_RETRYBUFPARERR(1U)
429
430#define S_PCIE_MSIXPARERR    12
431#define M_PCIE_MSIXPARERR    0x7
432
433#define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
434
435#define S_PCIE_CFPARERR    11
436#define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
437#define F_PCIE_CFPARERR    V_PCIE_CFPARERR(1U)
438
439#define S_PCIE_RFPARERR    10
440#define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
441#define F_PCIE_RFPARERR    V_PCIE_RFPARERR(1U)
442
443#define S_PCIE_WFPARERR    9
444#define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
445#define F_PCIE_WFPARERR    V_PCIE_WFPARERR(1U)
446
447#define S_PCIE_PIOPARERR    8
448#define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
449#define F_PCIE_PIOPARERR    V_PCIE_PIOPARERR(1U)
450
451#define S_UNXSPLCPLERRC    7
452#define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
453#define F_UNXSPLCPLERRC    V_UNXSPLCPLERRC(1U)
454
455#define S_UNXSPLCPLERRR    6
456#define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
457#define F_UNXSPLCPLERRR    V_UNXSPLCPLERRR(1U)
458
459#define S_PEXERR    0
460#define V_PEXERR(x) ((x) << S_PEXERR)
461#define F_PEXERR    V_PEXERR(1U)
462
463#define A_PCIE_INT_CAUSE 0x84
464
465#define S_PCIE_DMASTOPEN    24
466#define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN)
467#define F_PCIE_DMASTOPEN    V_PCIE_DMASTOPEN(1U)
468
469#define A_PCIE_CFG 0x88
470
471#define S_ENABLELINKDWNDRST    21
472#define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST)
473#define F_ENABLELINKDWNDRST    V_ENABLELINKDWNDRST(1U)
474
475#define S_ENABLELINKDOWNRST    20
476#define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST)
477#define F_ENABLELINKDOWNRST    V_ENABLELINKDOWNRST(1U)
478
479#define S_PCIE_CLIDECEN    16
480#define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
481#define F_PCIE_CLIDECEN    V_PCIE_CLIDECEN(1U)
482
483#define S_CRSTWRMMODE    0
484#define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
485#define F_CRSTWRMMODE    V_CRSTWRMMODE(1U)
486
487#define A_PCIE_MODE 0x8c
488
489#define S_NUMFSTTRNSEQRX    10
490#define M_NUMFSTTRNSEQRX    0xff
491#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
492#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
493
494#define A_PCIE_PEX_CTRL0 0x98
495
496#define S_NUMFSTTRNSEQ    22
497#define M_NUMFSTTRNSEQ    0xff
498#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
499#define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
500
501#define S_REPLAYLMT    2
502#define M_REPLAYLMT    0xfffff
503
504#define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
505
506#define A_PCIE_PEX_CTRL1 0x9c
507
508#define S_T3A_ACKLAT    0
509#define M_T3A_ACKLAT    0x7ff
510
511#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
512
513#define S_ACKLAT    0
514#define M_ACKLAT    0x1fff
515
516#define V_ACKLAT(x) ((x) << S_ACKLAT)
517
518#define A_PCIE_PEX_ERR 0xa4
519
520#define A_T3DBG_GPIO_EN 0xd0
521
522#define S_GPIO11_OEN    27
523#define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
524#define F_GPIO11_OEN    V_GPIO11_OEN(1U)
525
526#define S_GPIO10_OEN    26
527#define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
528#define F_GPIO10_OEN    V_GPIO10_OEN(1U)
529
530#define S_GPIO7_OEN    23
531#define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
532#define F_GPIO7_OEN    V_GPIO7_OEN(1U)
533
534#define S_GPIO6_OEN    22
535#define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
536#define F_GPIO6_OEN    V_GPIO6_OEN(1U)
537
538#define S_GPIO5_OEN    21
539#define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
540#define F_GPIO5_OEN    V_GPIO5_OEN(1U)
541
542#define S_GPIO4_OEN    20
543#define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
544#define F_GPIO4_OEN    V_GPIO4_OEN(1U)
545
546#define S_GPIO2_OEN    18
547#define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
548#define F_GPIO2_OEN    V_GPIO2_OEN(1U)
549
550#define S_GPIO1_OEN    17
551#define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
552#define F_GPIO1_OEN    V_GPIO1_OEN(1U)
553
554#define S_GPIO0_OEN    16
555#define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
556#define F_GPIO0_OEN    V_GPIO0_OEN(1U)
557
558#define S_GPIO10_OUT_VAL    10
559#define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
560#define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
561
562#define S_GPIO7_OUT_VAL    7
563#define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
564#define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
565
566#define S_GPIO6_OUT_VAL    6
567#define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
568#define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
569
570#define S_GPIO5_OUT_VAL    5
571#define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
572#define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
573
574#define S_GPIO4_OUT_VAL    4
575#define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
576#define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
577
578#define S_GPIO2_OUT_VAL    2
579#define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
580#define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
581
582#define S_GPIO1_OUT_VAL    1
583#define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
584#define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
585
586#define S_GPIO0_OUT_VAL    0
587#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
588#define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
589
590#define A_T3DBG_INT_ENABLE 0xd8
591
592#define S_GPIO11    11
593#define V_GPIO11(x) ((x) << S_GPIO11)
594#define F_GPIO11    V_GPIO11(1U)
595
596#define S_GPIO10    10
597#define V_GPIO10(x) ((x) << S_GPIO10)
598#define F_GPIO10    V_GPIO10(1U)
599
600#define S_GPIO9    9
601#define V_GPIO9(x) ((x) << S_GPIO9)
602#define F_GPIO9    V_GPIO9(1U)
603
604#define S_GPIO7    7
605#define V_GPIO7(x) ((x) << S_GPIO7)
606#define F_GPIO7    V_GPIO7(1U)
607
608#define S_GPIO6    6
609#define V_GPIO6(x) ((x) << S_GPIO6)
610#define F_GPIO6    V_GPIO6(1U)
611
612#define S_GPIO5    5
613#define V_GPIO5(x) ((x) << S_GPIO5)
614#define F_GPIO5    V_GPIO5(1U)
615
616#define S_GPIO4    4
617#define V_GPIO4(x) ((x) << S_GPIO4)
618#define F_GPIO4    V_GPIO4(1U)
619
620#define S_GPIO3    3
621#define V_GPIO3(x) ((x) << S_GPIO3)
622#define F_GPIO3    V_GPIO3(1U)
623
624#define S_GPIO2    2
625#define V_GPIO2(x) ((x) << S_GPIO2)
626#define F_GPIO2    V_GPIO2(1U)
627
628#define S_GPIO1    1
629#define V_GPIO1(x) ((x) << S_GPIO1)
630#define F_GPIO1    V_GPIO1(1U)
631
632#define S_GPIO0    0
633#define V_GPIO0(x) ((x) << S_GPIO0)
634#define F_GPIO0    V_GPIO0(1U)
635
636#define A_T3DBG_INT_CAUSE 0xdc
637
638#define A_T3DBG_GPIO_ACT_LOW 0xf0
639
640#define MC7_PMRX_BASE_ADDR 0x100
641
642#define A_MC7_CFG 0x100
643
644#define S_IFEN    13
645#define V_IFEN(x) ((x) << S_IFEN)
646#define F_IFEN    V_IFEN(1U)
647
648#define S_TERM150    11
649#define V_TERM150(x) ((x) << S_TERM150)
650#define F_TERM150    V_TERM150(1U)
651
652#define S_SLOW    10
653#define V_SLOW(x) ((x) << S_SLOW)
654#define F_SLOW    V_SLOW(1U)
655
656#define S_WIDTH    8
657#define M_WIDTH    0x3
658#define V_WIDTH(x) ((x) << S_WIDTH)
659#define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
660
661#define S_BKS    6
662#define V_BKS(x) ((x) << S_BKS)
663#define F_BKS    V_BKS(1U)
664
665#define S_ORG    5
666#define V_ORG(x) ((x) << S_ORG)
667#define F_ORG    V_ORG(1U)
668
669#define S_DEN    2
670#define M_DEN    0x7
671#define V_DEN(x) ((x) << S_DEN)
672#define G_DEN(x) (((x) >> S_DEN) & M_DEN)
673
674#define S_RDY    1
675#define V_RDY(x) ((x) << S_RDY)
676#define F_RDY    V_RDY(1U)
677
678#define S_CLKEN    0
679#define V_CLKEN(x) ((x) << S_CLKEN)
680#define F_CLKEN    V_CLKEN(1U)
681
682#define A_MC7_MODE 0x104
683
684#define S_BUSY    31
685#define V_BUSY(x) ((x) << S_BUSY)
686#define F_BUSY    V_BUSY(1U)
687
688#define A_MC7_EXT_MODE1 0x108
689
690#define A_MC7_EXT_MODE2 0x10c
691
692#define A_MC7_EXT_MODE3 0x110
693
694#define A_MC7_PRE 0x114
695
696#define A_MC7_REF 0x118
697
698#define S_PREREFDIV    1
699#define M_PREREFDIV    0x3fff
700#define V_PREREFDIV(x) ((x) << S_PREREFDIV)
701
702#define S_PERREFEN    0
703#define V_PERREFEN(x) ((x) << S_PERREFEN)
704#define F_PERREFEN    V_PERREFEN(1U)
705
706#define A_MC7_DLL 0x11c
707
708#define S_DLLENB    1
709#define V_DLLENB(x) ((x) << S_DLLENB)
710#define F_DLLENB    V_DLLENB(1U)
711
712#define S_DLLRST    0
713#define V_DLLRST(x) ((x) << S_DLLRST)
714#define F_DLLRST    V_DLLRST(1U)
715
716#define A_MC7_PARM 0x120
717
718#define S_ACTTOPREDLY    26
719#define M_ACTTOPREDLY    0xf
720#define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
721
722#define S_ACTTORDWRDLY    23
723#define M_ACTTORDWRDLY    0x7
724#define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
725
726#define S_PRECYC    20
727#define M_PRECYC    0x7
728#define V_PRECYC(x) ((x) << S_PRECYC)
729
730#define S_REFCYC    13
731#define M_REFCYC    0x7f
732#define V_REFCYC(x) ((x) << S_REFCYC)
733
734#define S_BKCYC    8
735#define M_BKCYC    0x1f
736#define V_BKCYC(x) ((x) << S_BKCYC)
737
738#define S_WRTORDDLY    4
739#define M_WRTORDDLY    0xf
740#define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
741
742#define S_RDTOWRDLY    0
743#define M_RDTOWRDLY    0xf
744#define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
745
746#define A_MC7_CAL 0x128
747
748#define S_CAL_FAULT    30
749#define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
750#define F_CAL_FAULT    V_CAL_FAULT(1U)
751
752#define S_SGL_CAL_EN    20
753#define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
754#define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
755
756#define A_MC7_ERR_ADDR 0x12c
757
758#define A_MC7_ECC 0x130
759
760#define S_ECCCHKEN    1
761#define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
762#define F_ECCCHKEN    V_ECCCHKEN(1U)
763
764#define S_ECCGENEN    0
765#define V_ECCGENEN(x) ((x) << S_ECCGENEN)
766#define F_ECCGENEN    V_ECCGENEN(1U)
767
768#define A_MC7_CE_ADDR 0x134
769
770#define A_MC7_CE_DATA0 0x138
771
772#define A_MC7_CE_DATA1 0x13c
773
774#define A_MC7_CE_DATA2 0x140
775
776#define S_DATA    0
777#define M_DATA    0xff
778
779#define G_DATA(x) (((x) >> S_DATA) & M_DATA)
780
781#define A_MC7_UE_ADDR 0x144
782
783#define A_MC7_UE_DATA0 0x148
784
785#define A_MC7_UE_DATA1 0x14c
786
787#define A_MC7_UE_DATA2 0x150
788
789#define A_MC7_BD_ADDR 0x154
790
791#define S_ADDR    3
792
793#define M_ADDR    0x1fffffff
794
795#define A_MC7_BD_DATA0 0x158
796
797#define A_MC7_BD_DATA1 0x15c
798
799#define A_MC7_BD_OP 0x164
800
801#define S_OP    0
802
803#define V_OP(x) ((x) << S_OP)
804#define F_OP    V_OP(1U)
805
806#define A_MC7_BIST_ADDR_BEG 0x168
807
808#define A_MC7_BIST_ADDR_END 0x16c
809
810#define A_MC7_BIST_DATA 0x170
811
812#define A_MC7_BIST_OP 0x174
813
814#define S_CONT    3
815#define V_CONT(x) ((x) << S_CONT)
816#define F_CONT    V_CONT(1U)
817
818#define A_MC7_INT_ENABLE 0x178
819
820#define S_AE    17
821#define V_AE(x) ((x) << S_AE)
822#define F_AE    V_AE(1U)
823
824#define S_PE    2
825#define M_PE    0x7fff
826
827#define V_PE(x) ((x) << S_PE)
828
829#define G_PE(x) (((x) >> S_PE) & M_PE)
830
831#define S_UE    1
832#define V_UE(x) ((x) << S_UE)
833#define F_UE    V_UE(1U)
834
835#define S_CE    0
836#define V_CE(x) ((x) << S_CE)
837#define F_CE    V_CE(1U)
838
839#define A_MC7_INT_CAUSE 0x17c
840
841#define MC7_PMTX_BASE_ADDR 0x180
842
843#define MC7_CM_BASE_ADDR 0x200
844
845#define A_CIM_BOOT_CFG 0x280
846
847#define S_BOOTADDR    2
848#define M_BOOTADDR    0x3fffffff
849#define V_BOOTADDR(x) ((x) << S_BOOTADDR)
850
851#define A_CIM_SDRAM_BASE_ADDR 0x28c
852
853#define A_CIM_SDRAM_ADDR_SIZE 0x290
854
855#define A_CIM_HOST_INT_ENABLE 0x298
856
857#define S_DTAGPARERR    28
858#define V_DTAGPARERR(x) ((x) << S_DTAGPARERR)
859#define F_DTAGPARERR    V_DTAGPARERR(1U)
860
861#define S_ITAGPARERR    27
862#define V_ITAGPARERR(x) ((x) << S_ITAGPARERR)
863#define F_ITAGPARERR    V_ITAGPARERR(1U)
864
865#define S_IBQTPPARERR    26
866#define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR)
867#define F_IBQTPPARERR    V_IBQTPPARERR(1U)
868
869#define S_IBQULPPARERR    25
870#define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
871#define F_IBQULPPARERR    V_IBQULPPARERR(1U)
872
873#define S_IBQSGEHIPARERR    24
874#define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
875#define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
876
877#define S_IBQSGELOPARERR    23
878#define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
879#define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
880
881#define S_OBQULPLOPARERR    22
882#define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR)
883#define F_OBQULPLOPARERR    V_OBQULPLOPARERR(1U)
884
885#define S_OBQULPHIPARERR    21
886#define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR)
887#define F_OBQULPHIPARERR    V_OBQULPHIPARERR(1U)
888
889#define S_OBQSGEPARERR    20
890#define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
891#define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
892
893#define S_DCACHEPARERR    19
894#define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR)
895#define F_DCACHEPARERR    V_DCACHEPARERR(1U)
896
897#define S_ICACHEPARERR    18
898#define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR)
899#define F_ICACHEPARERR    V_ICACHEPARERR(1U)
900
901#define S_DRAMPARERR    17
902#define V_DRAMPARERR(x) ((x) << S_DRAMPARERR)
903#define F_DRAMPARERR    V_DRAMPARERR(1U)
904
905#define A_CIM_HOST_INT_CAUSE 0x29c
906
907#define S_BLKWRPLINT    12
908#define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
909#define F_BLKWRPLINT    V_BLKWRPLINT(1U)
910
911#define S_BLKRDPLINT    11
912#define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
913#define F_BLKRDPLINT    V_BLKRDPLINT(1U)
914
915#define S_BLKWRCTLINT    10
916#define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
917#define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
918
919#define S_BLKRDCTLINT    9
920#define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
921#define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
922
923#define S_BLKWRFLASHINT    8
924#define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
925#define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
926
927#define S_BLKRDFLASHINT    7
928#define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
929#define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
930
931#define S_SGLWRFLASHINT    6
932#define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
933#define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
934
935#define S_WRBLKFLASHINT    5
936#define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
937#define F_WRBLKFLASHINT    V_WRBLKFLASHINT(1U)
938
939#define S_BLKWRBOOTINT    4
940#define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
941#define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
942
943#define S_FLASHRANGEINT    2
944#define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
945#define F_FLASHRANGEINT    V_FLASHRANGEINT(1U)
946
947#define S_SDRAMRANGEINT    1
948#define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
949#define F_SDRAMRANGEINT    V_SDRAMRANGEINT(1U)
950
951#define S_RSVDSPACEINT    0
952#define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
953#define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
954
955#define A_CIM_HOST_ACC_CTRL 0x2b0
956
957#define S_HOSTBUSY    17
958#define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
959#define F_HOSTBUSY    V_HOSTBUSY(1U)
960
961#define A_CIM_HOST_ACC_DATA 0x2b4
962
963#define A_CIM_IBQ_DBG_CFG 0x2c0
964
965#define S_IBQDBGADDR    16
966#define M_IBQDBGADDR    0x1ff
967#define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
968#define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
969
970#define S_IBQDBGQID    3
971#define M_IBQDBGQID    0x3
972#define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)
973#define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)
974
975#define S_IBQDBGWR    2
976#define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
977#define F_IBQDBGWR    V_IBQDBGWR(1U)
978
979#define S_IBQDBGBUSY    1
980#define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
981#define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
982
983#define S_IBQDBGEN    0
984#define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
985#define F_IBQDBGEN    V_IBQDBGEN(1U)
986
987#define A_CIM_IBQ_DBG_DATA 0x2c8
988
989#define A_TP_IN_CONFIG 0x300
990
991#define S_RXFBARBPRIO    25
992#define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)
993#define F_RXFBARBPRIO    V_RXFBARBPRIO(1U)
994
995#define S_TXFBARBPRIO    24
996#define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)
997#define F_TXFBARBPRIO    V_TXFBARBPRIO(1U)
998
999#define S_NICMODE    14
1000#define V_NICMODE(x) ((x) << S_NICMODE)
1001#define F_NICMODE    V_NICMODE(1U)
1002
1003#define S_IPV6ENABLE    15
1004#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
1005#define F_IPV6ENABLE    V_IPV6ENABLE(1U)
1006
1007#define A_TP_OUT_CONFIG 0x304
1008
1009#define S_VLANEXTRACTIONENABLE    12
1010
1011#define A_TP_GLOBAL_CONFIG 0x308
1012
1013#define S_TXPACINGENABLE    24
1014#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
1015#define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
1016
1017#define S_PATHMTU    15
1018#define V_PATHMTU(x) ((x) << S_PATHMTU)
1019#define F_PATHMTU    V_PATHMTU(1U)
1020
1021#define S_IPCHECKSUMOFFLOAD    13
1022#define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
1023#define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
1024
1025#define S_UDPCHECKSUMOFFLOAD    12
1026#define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
1027#define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
1028
1029#define S_TCPCHECKSUMOFFLOAD    11
1030#define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
1031#define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
1032
1033#define S_IPTTL    0
1034#define M_IPTTL    0xff
1035#define V_IPTTL(x) ((x) << S_IPTTL)
1036
1037#define A_TP_CMM_MM_BASE 0x314
1038
1039#define A_TP_CMM_TIMER_BASE 0x318
1040
1041#define S_CMTIMERMAXNUM    28
1042#define M_CMTIMERMAXNUM    0x3
1043#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
1044
1045#define A_TP_PMM_SIZE 0x31c
1046
1047#define A_TP_PMM_TX_BASE 0x320
1048
1049#define A_TP_PMM_RX_BASE 0x328
1050
1051#define A_TP_PMM_RX_PAGE_SIZE 0x32c
1052
1053#define A_TP_PMM_RX_MAX_PAGE 0x330
1054
1055#define A_TP_PMM_TX_PAGE_SIZE 0x334
1056
1057#define A_TP_PMM_TX_MAX_PAGE 0x338
1058
1059#define A_TP_TCP_OPTIONS 0x340
1060
1061#define S_MTUDEFAULT    16
1062#define M_MTUDEFAULT    0xffff
1063#define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
1064
1065#define S_MTUENABLE    10
1066#define V_MTUENABLE(x) ((x) << S_MTUENABLE)
1067#define F_MTUENABLE    V_MTUENABLE(1U)
1068
1069#define S_SACKRX    8
1070#define V_SACKRX(x) ((x) << S_SACKRX)
1071#define F_SACKRX    V_SACKRX(1U)
1072
1073#define S_SACKMODE    4
1074
1075#define M_SACKMODE    0x3
1076
1077#define V_SACKMODE(x) ((x) << S_SACKMODE)
1078
1079#define S_WINDOWSCALEMODE    2
1080#define M_WINDOWSCALEMODE    0x3
1081#define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
1082
1083#define S_TIMESTAMPSMODE    0
1084
1085#define M_TIMESTAMPSMODE    0x3
1086
1087#define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
1088
1089#define A_TP_DACK_CONFIG 0x344
1090
1091#define S_AUTOSTATE3    30
1092#define M_AUTOSTATE3    0x3
1093#define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
1094
1095#define S_AUTOSTATE2    28
1096#define M_AUTOSTATE2    0x3
1097#define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
1098
1099#define S_AUTOSTATE1    26
1100#define M_AUTOSTATE1    0x3
1101#define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
1102
1103#define S_BYTETHRESHOLD    5
1104#define M_BYTETHRESHOLD    0xfffff
1105#define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
1106
1107#define S_MSSTHRESHOLD    3
1108#define M_MSSTHRESHOLD    0x3
1109#define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
1110
1111#define S_AUTOCAREFUL    2
1112#define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
1113#define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
1114
1115#define S_AUTOENABLE    1
1116#define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
1117#define F_AUTOENABLE    V_AUTOENABLE(1U)
1118
1119#define S_DACK_MODE    0
1120#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
1121#define F_DACK_MODE    V_DACK_MODE(1U)
1122
1123#define A_TP_PC_CONFIG 0x348
1124
1125#define S_TXTOSQUEUEMAPMODE    26
1126#define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
1127#define F_TXTOSQUEUEMAPMODE    V_TXTOSQUEUEMAPMODE(1U)
1128
1129#define S_ENABLEEPCMDAFULL    23
1130#define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
1131#define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
1132
1133#define S_MODULATEUNIONMODE    22
1134#define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
1135#define F_MODULATEUNIONMODE    V_MODULATEUNIONMODE(1U)
1136
1137#define S_TXDEFERENABLE    20
1138#define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
1139#define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
1140
1141#define S_RXCONGESTIONMODE    19
1142#define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
1143#define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
1144
1145#define S_HEARBEATDACK    16
1146#define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
1147#define F_HEARBEATDACK    V_HEARBEATDACK(1U)
1148
1149#define S_TXCONGESTIONMODE    15
1150#define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
1151#define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
1152
1153#define S_ENABLEOCSPIFULL    30
1154#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
1155#define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
1156
1157#define S_LOCKTID    28
1158#define V_LOCKTID(x) ((x) << S_LOCKTID)
1159#define F_LOCKTID    V_LOCKTID(1U)
1160
1161#define S_TABLELATENCYDELTA    0
1162#define M_TABLELATENCYDELTA    0xf
1163#define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
1164#define G_TABLELATENCYDELTA(x) \
1165	(((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
1166
1167#define A_TP_PC_CONFIG2 0x34c
1168
1169#define S_DISBLEDAPARBIT0    15
1170#define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0)
1171#define F_DISBLEDAPARBIT0    V_DISBLEDAPARBIT0(1U)
1172
1173#define S_ENABLEARPMISS    13
1174#define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
1175#define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
1176
1177#define S_ENABLENONOFDTNLSYN    12
1178#define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN)
1179#define F_ENABLENONOFDTNLSYN    V_ENABLENONOFDTNLSYN(1U)
1180
1181#define S_ENABLEIPV6RSS    11
1182#define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
1183#define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
1184
1185#define S_CHDRAFULL    4
1186#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
1187#define F_CHDRAFULL    V_CHDRAFULL(1U)
1188
1189#define A_TP_TCP_BACKOFF_REG0 0x350
1190
1191#define A_TP_TCP_BACKOFF_REG1 0x354
1192
1193#define A_TP_TCP_BACKOFF_REG2 0x358
1194
1195#define A_TP_TCP_BACKOFF_REG3 0x35c
1196
1197#define A_TP_PARA_REG2 0x368
1198
1199#define S_MAXRXDATA    16
1200#define M_MAXRXDATA    0xffff
1201#define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
1202
1203#define S_RXCOALESCESIZE    0
1204#define M_RXCOALESCESIZE    0xffff
1205#define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
1206
1207#define A_TP_PARA_REG3 0x36c
1208
1209#define S_TXDATAACKIDX    16
1210#define M_TXDATAACKIDX    0xf
1211
1212#define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
1213
1214#define S_TXPACEAUTOSTRICT    10
1215#define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
1216#define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
1217
1218#define S_TXPACEFIXED    9
1219#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
1220#define F_TXPACEFIXED    V_TXPACEFIXED(1U)
1221
1222#define S_TXPACEAUTO    8
1223#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
1224#define F_TXPACEAUTO    V_TXPACEAUTO(1U)
1225
1226#define S_RXCOALESCEENABLE    1
1227#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
1228#define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
1229
1230#define S_RXCOALESCEPSHEN    0
1231#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
1232#define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
1233
1234#define A_TP_PARA_REG4 0x370
1235
1236#define A_TP_PARA_REG5 0x374
1237
1238#define S_RXDDPOFFINIT    3
1239#define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
1240#define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
1241
1242#define A_TP_PARA_REG6 0x378
1243
1244#define S_T3A_ENABLEESND    13
1245#define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
1246#define F_T3A_ENABLEESND    V_T3A_ENABLEESND(1U)
1247
1248#define S_ENABLEESND    11
1249#define V_ENABLEESND(x) ((x) << S_ENABLEESND)
1250#define F_ENABLEESND    V_ENABLEESND(1U)
1251
1252#define A_TP_PARA_REG7 0x37c
1253
1254#define S_PMMAXXFERLEN1    16
1255#define M_PMMAXXFERLEN1    0xffff
1256#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
1257
1258#define S_PMMAXXFERLEN0    0
1259#define M_PMMAXXFERLEN0    0xffff
1260#define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
1261
1262#define A_TP_TIMER_RESOLUTION 0x390
1263
1264#define S_TIMERRESOLUTION    16
1265#define M_TIMERRESOLUTION    0xff
1266#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
1267
1268#define S_TIMESTAMPRESOLUTION    8
1269#define M_TIMESTAMPRESOLUTION    0xff
1270#define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
1271
1272#define S_DELAYEDACKRESOLUTION    0
1273#define M_DELAYEDACKRESOLUTION    0xff
1274#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
1275
1276#define A_TP_MSL 0x394
1277
1278#define A_TP_RXT_MIN 0x398
1279
1280#define A_TP_RXT_MAX 0x39c
1281
1282#define A_TP_PERS_MIN 0x3a0
1283
1284#define A_TP_PERS_MAX 0x3a4
1285
1286#define A_TP_KEEP_IDLE 0x3a8
1287
1288#define A_TP_KEEP_INTVL 0x3ac
1289
1290#define A_TP_INIT_SRTT 0x3b0
1291
1292#define A_TP_DACK_TIMER 0x3b4
1293
1294#define A_TP_FINWAIT2_TIMER 0x3b8
1295
1296#define A_TP_SHIFT_CNT 0x3c0
1297
1298#define S_SYNSHIFTMAX    24
1299
1300#define M_SYNSHIFTMAX    0xff
1301
1302#define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
1303
1304#define S_RXTSHIFTMAXR1    20
1305
1306#define M_RXTSHIFTMAXR1    0xf
1307
1308#define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
1309
1310#define S_RXTSHIFTMAXR2    16
1311
1312#define M_RXTSHIFTMAXR2    0xf
1313
1314#define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
1315
1316#define S_PERSHIFTBACKOFFMAX    12
1317#define M_PERSHIFTBACKOFFMAX    0xf
1318#define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
1319
1320#define S_PERSHIFTMAX    8
1321#define M_PERSHIFTMAX    0xf
1322#define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
1323
1324#define S_KEEPALIVEMAX    0
1325
1326#define M_KEEPALIVEMAX    0xff
1327
1328#define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
1329
1330#define A_TP_MTU_PORT_TABLE 0x3d0
1331
1332#define A_TP_CCTRL_TABLE 0x3dc
1333
1334#define A_TP_MTU_TABLE 0x3e4
1335
1336#define A_TP_RSS_MAP_TABLE 0x3e8
1337
1338#define A_TP_RSS_LKP_TABLE 0x3ec
1339
1340#define A_TP_RSS_CONFIG 0x3f0
1341
1342#define S_TNL4TUPEN    29
1343#define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
1344#define F_TNL4TUPEN    V_TNL4TUPEN(1U)
1345
1346#define S_TNL2TUPEN    28
1347#define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
1348#define F_TNL2TUPEN    V_TNL2TUPEN(1U)
1349
1350#define S_TNLPRTEN    26
1351#define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
1352#define F_TNLPRTEN    V_TNLPRTEN(1U)
1353
1354#define S_TNLMAPEN    25
1355#define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
1356#define F_TNLMAPEN    V_TNLMAPEN(1U)
1357
1358#define S_TNLLKPEN    24
1359#define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
1360#define F_TNLLKPEN    V_TNLLKPEN(1U)
1361
1362#define S_RRCPLMAPEN    7
1363#define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
1364#define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
1365
1366#define S_RRCPLCPUSIZE    4
1367#define M_RRCPLCPUSIZE    0x7
1368#define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
1369
1370#define S_RQFEEDBACKENABLE    3
1371#define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
1372#define F_RQFEEDBACKENABLE    V_RQFEEDBACKENABLE(1U)
1373
1374#define S_HASHTOEPLITZ    2
1375#define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
1376#define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
1377
1378#define S_DISABLE    0
1379
1380#define A_TP_TM_PIO_ADDR 0x418
1381
1382#define A_TP_TM_PIO_DATA 0x41c
1383
1384#define A_TP_TX_MOD_QUE_TABLE 0x420
1385
1386#define A_TP_TX_RESOURCE_LIMIT 0x424
1387
1388#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
1389
1390#define S_TX_MOD_QUEUE_REQ_MAP    0
1391#define M_TX_MOD_QUEUE_REQ_MAP    0xff
1392#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1393
1394#define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
1395
1396#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
1397
1398#define A_TP_MOD_CHANNEL_WEIGHT 0x434
1399
1400#define A_TP_MOD_RATE_LIMIT 0x438
1401
1402#define A_TP_PIO_ADDR 0x440
1403
1404#define A_TP_PIO_DATA 0x444
1405
1406#define A_TP_RESET 0x44c
1407
1408#define S_FLSTINITENABLE    1
1409#define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
1410#define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
1411
1412#define S_TPRESET    0
1413#define V_TPRESET(x) ((x) << S_TPRESET)
1414#define F_TPRESET    V_TPRESET(1U)
1415
1416#define A_TP_CMM_MM_RX_FLST_BASE 0x460
1417
1418#define A_TP_CMM_MM_TX_FLST_BASE 0x464
1419
1420#define A_TP_CMM_MM_PS_FLST_BASE 0x468
1421
1422#define A_TP_MIB_INDEX 0x450
1423
1424#define A_TP_MIB_RDATA 0x454
1425
1426#define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
1427
1428#define A_TP_INT_ENABLE 0x470
1429
1430#define S_FLMTXFLSTEMPTY    30
1431#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
1432#define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
1433
1434#define S_FLMRXFLSTEMPTY    29
1435#define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)
1436#define F_FLMRXFLSTEMPTY    V_FLMRXFLSTEMPTY(1U)
1437
1438#define S_ARPLUTPERR    26
1439#define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
1440#define F_ARPLUTPERR    V_ARPLUTPERR(1U)
1441
1442#define S_CMCACHEPERR    24
1443#define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
1444#define F_CMCACHEPERR    V_CMCACHEPERR(1U)
1445
1446#define A_TP_INT_CAUSE 0x474
1447
1448#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
1449
1450#define A_TP_TX_DROP_CFG_CH0 0x12b
1451
1452#define A_TP_TX_DROP_MODE 0x12f
1453
1454#define A_TP_EGRESS_CONFIG 0x145
1455
1456#define S_REWRITEFORCETOSIZE    0
1457#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
1458#define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
1459
1460#define A_TP_TX_TRC_KEY0 0x20
1461
1462#define A_TP_RX_TRC_KEY0 0x120
1463
1464#define A_TP_TX_DROP_CNT_CH0 0x12d
1465
1466#define S_TXDROPCNTCH0RCVD    0
1467#define M_TXDROPCNTCH0RCVD    0xffff
1468#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
1469#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
1470			       M_TXDROPCNTCH0RCVD)
1471
1472#define A_TP_PROXY_FLOW_CNTL 0x4b0
1473
1474#define A_TP_EMBED_OP_FIELD0 0x4e8
1475#define A_TP_EMBED_OP_FIELD1 0x4ec
1476#define A_TP_EMBED_OP_FIELD2 0x4f0
1477#define A_TP_EMBED_OP_FIELD3 0x4f4
1478#define A_TP_EMBED_OP_FIELD4 0x4f8
1479#define A_TP_EMBED_OP_FIELD5 0x4fc
1480
1481#define A_ULPRX_CTL 0x500
1482
1483#define S_ROUND_ROBIN    4
1484#define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
1485#define F_ROUND_ROBIN    V_ROUND_ROBIN(1U)
1486
1487#define A_ULPRX_INT_ENABLE 0x504
1488
1489#define S_DATASELFRAMEERR0    7
1490#define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0)
1491#define F_DATASELFRAMEERR0    V_DATASELFRAMEERR0(1U)
1492
1493#define S_DATASELFRAMEERR1    6
1494#define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1)
1495#define F_DATASELFRAMEERR1    V_DATASELFRAMEERR1(1U)
1496
1497#define S_PCMDMUXPERR    5
1498#define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR)
1499#define F_PCMDMUXPERR    V_PCMDMUXPERR(1U)
1500
1501#define S_ARBFPERR    4
1502#define V_ARBFPERR(x) ((x) << S_ARBFPERR)
1503#define F_ARBFPERR    V_ARBFPERR(1U)
1504
1505#define S_ARBPF0PERR    3
1506#define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR)
1507#define F_ARBPF0PERR    V_ARBPF0PERR(1U)
1508
1509#define S_ARBPF1PERR    2
1510#define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR)
1511#define F_ARBPF1PERR    V_ARBPF1PERR(1U)
1512
1513#define S_PARERRPCMD    1
1514#define V_PARERRPCMD(x) ((x) << S_PARERRPCMD)
1515#define F_PARERRPCMD    V_PARERRPCMD(1U)
1516
1517#define S_PARERRDATA    0
1518#define V_PARERRDATA(x) ((x) << S_PARERRDATA)
1519#define F_PARERRDATA    V_PARERRDATA(1U)
1520
1521#define A_ULPRX_INT_CAUSE 0x508
1522
1523#define A_ULPRX_ISCSI_LLIMIT 0x50c
1524
1525#define A_ULPRX_ISCSI_ULIMIT 0x510
1526
1527#define A_ULPRX_ISCSI_TAGMASK 0x514
1528
1529#define A_ULPRX_ISCSI_PSZ 0x518
1530
1531#define A_ULPRX_TDDP_LLIMIT 0x51c
1532
1533#define A_ULPRX_TDDP_ULIMIT 0x520
1534#define A_ULPRX_TDDP_PSZ 0x528
1535
1536#define S_HPZ0    0
1537#define M_HPZ0    0xf
1538#define V_HPZ0(x) ((x) << S_HPZ0)
1539#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1540
1541#define A_ULPRX_STAG_LLIMIT 0x52c
1542
1543#define A_ULPRX_STAG_ULIMIT 0x530
1544
1545#define A_ULPRX_RQ_LLIMIT 0x534
1546
1547#define A_ULPRX_RQ_ULIMIT 0x538
1548
1549#define A_ULPRX_PBL_LLIMIT 0x53c
1550
1551#define A_ULPRX_PBL_ULIMIT 0x540
1552
1553#define A_ULPRX_TDDP_TAGMASK 0x524
1554
1555#define A_ULPTX_CONFIG 0x580
1556
1557#define S_CFG_CQE_SOP_MASK    1
1558#define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK)
1559#define F_CFG_CQE_SOP_MASK    V_CFG_CQE_SOP_MASK(1U)
1560
1561#define S_CFG_RR_ARB    0
1562#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
1563#define F_CFG_RR_ARB    V_CFG_RR_ARB(1U)
1564
1565#define A_ULPTX_INT_ENABLE 0x584
1566
1567#define S_PBL_BOUND_ERR_CH1    1
1568#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
1569#define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
1570
1571#define S_PBL_BOUND_ERR_CH0    0
1572#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
1573#define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
1574
1575#define A_ULPTX_INT_CAUSE 0x588
1576
1577#define A_ULPTX_TPT_LLIMIT 0x58c
1578
1579#define A_ULPTX_TPT_ULIMIT 0x590
1580
1581#define A_ULPTX_PBL_LLIMIT 0x594
1582
1583#define A_ULPTX_PBL_ULIMIT 0x598
1584
1585#define A_ULPTX_DMA_WEIGHT 0x5ac
1586
1587#define S_D1_WEIGHT    16
1588#define M_D1_WEIGHT    0xffff
1589#define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
1590
1591#define S_D0_WEIGHT    0
1592#define M_D0_WEIGHT    0xffff
1593#define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
1594
1595#define A_PM1_RX_CFG 0x5c0
1596#define A_PM1_RX_MODE 0x5c4
1597
1598#define A_PM1_RX_INT_ENABLE 0x5d8
1599
1600#define S_ZERO_E_CMD_ERROR    18
1601#define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
1602#define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
1603
1604#define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    17
1605#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
1606#define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1607
1608#define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    16
1609#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
1610#define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1611
1612#define S_IESPI0_RX_FRAMING_ERROR    15
1613#define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
1614#define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
1615
1616#define S_IESPI1_RX_FRAMING_ERROR    14
1617#define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
1618#define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
1619
1620#define S_IESPI0_TX_FRAMING_ERROR    13
1621#define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
1622#define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
1623
1624#define S_IESPI1_TX_FRAMING_ERROR    12
1625#define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
1626#define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
1627
1628#define S_OCSPI0_RX_FRAMING_ERROR    11
1629#define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
1630#define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
1631
1632#define S_OCSPI1_RX_FRAMING_ERROR    10
1633#define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
1634#define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
1635
1636#define S_OCSPI0_TX_FRAMING_ERROR    9
1637#define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
1638#define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
1639
1640#define S_OCSPI1_TX_FRAMING_ERROR    8
1641#define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
1642#define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
1643
1644#define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    7
1645#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
1646#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1647
1648#define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    6
1649#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1650#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1651
1652#define S_IESPI_PAR_ERROR    3
1653#define M_IESPI_PAR_ERROR    0x7
1654
1655#define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
1656
1657#define S_OCSPI_PAR_ERROR    0
1658#define M_OCSPI_PAR_ERROR    0x7
1659
1660#define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
1661
1662#define A_PM1_RX_INT_CAUSE 0x5dc
1663
1664#define A_PM1_TX_CFG 0x5e0
1665#define A_PM1_TX_MODE 0x5e4
1666
1667#define A_PM1_TX_INT_ENABLE 0x5f8
1668
1669#define S_ZERO_C_CMD_ERROR    18
1670#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
1671#define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
1672
1673#define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    17
1674#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
1675#define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1676
1677#define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    16
1678#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
1679#define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1680
1681#define S_ICSPI0_RX_FRAMING_ERROR    15
1682#define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
1683#define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
1684
1685#define S_ICSPI1_RX_FRAMING_ERROR    14
1686#define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
1687#define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
1688
1689#define S_ICSPI0_TX_FRAMING_ERROR    13
1690#define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
1691#define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
1692
1693#define S_ICSPI1_TX_FRAMING_ERROR    12
1694#define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
1695#define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
1696
1697#define S_OESPI0_RX_FRAMING_ERROR    11
1698#define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
1699#define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
1700
1701#define S_OESPI1_RX_FRAMING_ERROR    10
1702#define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
1703#define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
1704
1705#define S_OESPI0_TX_FRAMING_ERROR    9
1706#define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
1707#define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
1708
1709#define S_OESPI1_TX_FRAMING_ERROR    8
1710#define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
1711#define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
1712
1713#define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
1714#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
1715#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1716
1717#define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
1718#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1719#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1720
1721#define S_ICSPI_PAR_ERROR    3
1722#define M_ICSPI_PAR_ERROR    0x7
1723
1724#define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
1725
1726#define S_OESPI_PAR_ERROR    0
1727#define M_OESPI_PAR_ERROR    0x7
1728
1729#define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
1730
1731#define A_PM1_TX_INT_CAUSE 0x5fc
1732
1733#define A_MPS_CFG 0x600
1734
1735#define S_TPRXPORTEN    4
1736#define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
1737#define F_TPRXPORTEN    V_TPRXPORTEN(1U)
1738
1739#define S_TPTXPORT1EN    3
1740#define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
1741#define F_TPTXPORT1EN    V_TPTXPORT1EN(1U)
1742
1743#define S_TPTXPORT0EN    2
1744#define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
1745#define F_TPTXPORT0EN    V_TPTXPORT0EN(1U)
1746
1747#define S_PORT1ACTIVE    1
1748#define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
1749#define F_PORT1ACTIVE    V_PORT1ACTIVE(1U)
1750
1751#define S_PORT0ACTIVE    0
1752#define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
1753#define F_PORT0ACTIVE    V_PORT0ACTIVE(1U)
1754
1755#define S_ENFORCEPKT    11
1756#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
1757#define F_ENFORCEPKT    V_ENFORCEPKT(1U)
1758
1759#define A_MPS_INT_ENABLE 0x61c
1760
1761#define S_MCAPARERRENB    6
1762#define M_MCAPARERRENB    0x7
1763
1764#define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
1765
1766#define S_RXTPPARERRENB    4
1767#define M_RXTPPARERRENB    0x3
1768
1769#define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
1770
1771#define S_TX1TPPARERRENB    2
1772#define M_TX1TPPARERRENB    0x3
1773
1774#define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
1775
1776#define S_TX0TPPARERRENB    0
1777#define M_TX0TPPARERRENB    0x3
1778
1779#define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
1780
1781#define A_MPS_INT_CAUSE 0x620
1782
1783#define S_MCAPARERR    6
1784#define M_MCAPARERR    0x7
1785
1786#define V_MCAPARERR(x) ((x) << S_MCAPARERR)
1787
1788#define S_RXTPPARERR    4
1789#define M_RXTPPARERR    0x3
1790
1791#define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
1792
1793#define S_TX1TPPARERR    2
1794#define M_TX1TPPARERR    0x3
1795
1796#define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
1797
1798#define S_TX0TPPARERR    0
1799#define M_TX0TPPARERR    0x3
1800
1801#define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
1802
1803#define A_CPL_SWITCH_CNTRL 0x640
1804
1805#define A_CPL_INTR_ENABLE 0x650
1806
1807#define S_CIM_OP_MAP_PERR    5
1808#define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
1809#define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
1810
1811#define S_CIM_OVFL_ERROR    4
1812#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
1813#define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
1814
1815#define S_TP_FRAMING_ERROR    3
1816#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
1817#define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
1818
1819#define S_SGE_FRAMING_ERROR    2
1820#define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
1821#define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
1822
1823#define S_CIM_FRAMING_ERROR    1
1824#define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
1825#define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
1826
1827#define S_ZERO_SWITCH_ERROR    0
1828#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
1829#define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
1830
1831#define A_CPL_INTR_CAUSE 0x654
1832
1833#define A_CPL_MAP_TBL_DATA 0x65c
1834
1835#define A_SMB_GLOBAL_TIME_CFG 0x660
1836
1837#define A_I2C_CFG 0x6a0
1838
1839#define S_I2C_CLKDIV    0
1840#define M_I2C_CLKDIV    0xfff
1841#define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
1842
1843#define A_MI1_CFG 0x6b0
1844
1845#define S_CLKDIV    5
1846#define M_CLKDIV    0xff
1847#define V_CLKDIV(x) ((x) << S_CLKDIV)
1848
1849#define S_ST    3
1850
1851#define M_ST    0x3
1852
1853#define V_ST(x) ((x) << S_ST)
1854
1855#define G_ST(x) (((x) >> S_ST) & M_ST)
1856
1857#define S_PREEN    2
1858#define V_PREEN(x) ((x) << S_PREEN)
1859#define F_PREEN    V_PREEN(1U)
1860
1861#define S_MDIINV    1
1862#define V_MDIINV(x) ((x) << S_MDIINV)
1863#define F_MDIINV    V_MDIINV(1U)
1864
1865#define S_MDIEN    0
1866#define V_MDIEN(x) ((x) << S_MDIEN)
1867#define F_MDIEN    V_MDIEN(1U)
1868
1869#define A_MI1_ADDR 0x6b4
1870
1871#define S_PHYADDR    5
1872#define M_PHYADDR    0x1f
1873#define V_PHYADDR(x) ((x) << S_PHYADDR)
1874
1875#define S_REGADDR    0
1876#define M_REGADDR    0x1f
1877#define V_REGADDR(x) ((x) << S_REGADDR)
1878
1879#define A_MI1_DATA 0x6b8
1880
1881#define A_MI1_OP 0x6bc
1882
1883#define S_MDI_OP    0
1884#define M_MDI_OP    0x3
1885#define V_MDI_OP(x) ((x) << S_MDI_OP)
1886
1887#define A_SF_DATA 0x6d8
1888
1889#define A_SF_OP 0x6dc
1890
1891#define S_BYTECNT    1
1892#define M_BYTECNT    0x3
1893#define V_BYTECNT(x) ((x) << S_BYTECNT)
1894
1895#define A_PL_INT_ENABLE0 0x6e0
1896
1897#define S_T3DBG    23
1898#define V_T3DBG(x) ((x) << S_T3DBG)
1899#define F_T3DBG    V_T3DBG(1U)
1900
1901#define S_XGMAC0_1    20
1902#define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
1903#define F_XGMAC0_1    V_XGMAC0_1(1U)
1904
1905#define S_XGMAC0_0    19
1906#define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
1907#define F_XGMAC0_0    V_XGMAC0_0(1U)
1908
1909#define S_MC5A    18
1910#define V_MC5A(x) ((x) << S_MC5A)
1911#define F_MC5A    V_MC5A(1U)
1912
1913#define S_CPL_SWITCH    12
1914#define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
1915#define F_CPL_SWITCH    V_CPL_SWITCH(1U)
1916
1917#define S_MPS0    11
1918#define V_MPS0(x) ((x) << S_MPS0)
1919#define F_MPS0    V_MPS0(1U)
1920
1921#define S_PM1_TX    10
1922#define V_PM1_TX(x) ((x) << S_PM1_TX)
1923#define F_PM1_TX    V_PM1_TX(1U)
1924
1925#define S_PM1_RX    9
1926#define V_PM1_RX(x) ((x) << S_PM1_RX)
1927#define F_PM1_RX    V_PM1_RX(1U)
1928
1929#define S_ULP2_TX    8
1930#define V_ULP2_TX(x) ((x) << S_ULP2_TX)
1931#define F_ULP2_TX    V_ULP2_TX(1U)
1932
1933#define S_ULP2_RX    7
1934#define V_ULP2_RX(x) ((x) << S_ULP2_RX)
1935#define F_ULP2_RX    V_ULP2_RX(1U)
1936
1937#define S_TP1    6
1938#define V_TP1(x) ((x) << S_TP1)
1939#define F_TP1    V_TP1(1U)
1940
1941#define S_CIM    5
1942#define V_CIM(x) ((x) << S_CIM)
1943#define F_CIM    V_CIM(1U)
1944
1945#define S_MC7_CM    4
1946#define V_MC7_CM(x) ((x) << S_MC7_CM)
1947#define F_MC7_CM    V_MC7_CM(1U)
1948
1949#define S_MC7_PMTX    3
1950#define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
1951#define F_MC7_PMTX    V_MC7_PMTX(1U)
1952
1953#define S_MC7_PMRX    2
1954#define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
1955#define F_MC7_PMRX    V_MC7_PMRX(1U)
1956
1957#define S_PCIM0    1
1958#define V_PCIM0(x) ((x) << S_PCIM0)
1959#define F_PCIM0    V_PCIM0(1U)
1960
1961#define S_SGE3    0
1962#define V_SGE3(x) ((x) << S_SGE3)
1963#define F_SGE3    V_SGE3(1U)
1964
1965#define A_PL_INT_CAUSE0 0x6e4
1966
1967#define A_PL_RST 0x6f0
1968
1969#define S_FATALPERREN    4
1970#define V_FATALPERREN(x) ((x) << S_FATALPERREN)
1971#define F_FATALPERREN    V_FATALPERREN(1U)
1972
1973#define S_CRSTWRM    1
1974#define V_CRSTWRM(x) ((x) << S_CRSTWRM)
1975#define F_CRSTWRM    V_CRSTWRM(1U)
1976
1977#define A_PL_REV 0x6f4
1978
1979#define A_PL_CLI 0x6f8
1980
1981#define A_MC5_DB_CONFIG 0x704
1982
1983#define S_TMTYPEHI    30
1984#define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
1985#define F_TMTYPEHI    V_TMTYPEHI(1U)
1986
1987#define S_TMPARTSIZE    28
1988#define M_TMPARTSIZE    0x3
1989#define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
1990#define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
1991
1992#define S_TMTYPE    26
1993#define M_TMTYPE    0x3
1994#define V_TMTYPE(x) ((x) << S_TMTYPE)
1995#define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
1996
1997#define S_COMPEN    17
1998#define V_COMPEN(x) ((x) << S_COMPEN)
1999#define F_COMPEN    V_COMPEN(1U)
2000
2001#define S_PRTYEN    6
2002#define V_PRTYEN(x) ((x) << S_PRTYEN)
2003#define F_PRTYEN    V_PRTYEN(1U)
2004
2005#define S_MBUSEN    5
2006#define V_MBUSEN(x) ((x) << S_MBUSEN)
2007#define F_MBUSEN    V_MBUSEN(1U)
2008
2009#define S_DBGIEN    4
2010#define V_DBGIEN(x) ((x) << S_DBGIEN)
2011#define F_DBGIEN    V_DBGIEN(1U)
2012
2013#define S_TMRDY    2
2014#define V_TMRDY(x) ((x) << S_TMRDY)
2015#define F_TMRDY    V_TMRDY(1U)
2016
2017#define S_TMRST    1
2018#define V_TMRST(x) ((x) << S_TMRST)
2019#define F_TMRST    V_TMRST(1U)
2020
2021#define S_TMMODE    0
2022#define V_TMMODE(x) ((x) << S_TMMODE)
2023#define F_TMMODE    V_TMMODE(1U)
2024
2025#define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
2026
2027#define A_MC5_DB_FILTER_TABLE 0x710
2028
2029#define A_MC5_DB_SERVER_INDEX 0x714
2030
2031#define A_MC5_DB_RSP_LATENCY 0x720
2032
2033#define S_RDLAT    16
2034#define M_RDLAT    0x1f
2035#define V_RDLAT(x) ((x) << S_RDLAT)
2036
2037#define S_LRNLAT    8
2038#define M_LRNLAT    0x1f
2039#define V_LRNLAT(x) ((x) << S_LRNLAT)
2040
2041#define S_SRCHLAT    0
2042#define M_SRCHLAT    0x1f
2043#define V_SRCHLAT(x) ((x) << S_SRCHLAT)
2044
2045#define A_MC5_DB_PART_ID_INDEX 0x72c
2046
2047#define A_MC5_DB_INT_ENABLE 0x740
2048
2049#define S_DELACTEMPTY    18
2050#define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
2051#define F_DELACTEMPTY    V_DELACTEMPTY(1U)
2052
2053#define S_DISPQPARERR    17
2054#define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
2055#define F_DISPQPARERR    V_DISPQPARERR(1U)
2056
2057#define S_REQQPARERR    16
2058#define V_REQQPARERR(x) ((x) << S_REQQPARERR)
2059#define F_REQQPARERR    V_REQQPARERR(1U)
2060
2061#define S_UNKNOWNCMD    15
2062#define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
2063#define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
2064
2065#define S_NFASRCHFAIL    8
2066#define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
2067#define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
2068
2069#define S_ACTRGNFULL    7
2070#define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
2071#define F_ACTRGNFULL    V_ACTRGNFULL(1U)
2072
2073#define S_PARITYERR    6
2074#define V_PARITYERR(x) ((x) << S_PARITYERR)
2075#define F_PARITYERR    V_PARITYERR(1U)
2076
2077#define A_MC5_DB_INT_CAUSE 0x744
2078
2079#define A_MC5_DB_DBGI_CONFIG 0x774
2080
2081#define A_MC5_DB_DBGI_REQ_CMD 0x778
2082
2083#define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
2084
2085#define A_MC5_DB_DBGI_REQ_ADDR1 0x780
2086
2087#define A_MC5_DB_DBGI_REQ_ADDR2 0x784
2088
2089#define A_MC5_DB_DBGI_REQ_DATA0 0x788
2090
2091#define A_MC5_DB_DBGI_REQ_DATA1 0x78c
2092
2093#define A_MC5_DB_DBGI_REQ_DATA2 0x790
2094
2095#define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
2096
2097#define S_DBGIRSPVALID    0
2098#define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
2099#define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
2100
2101#define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
2102
2103#define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
2104
2105#define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
2106
2107#define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
2108
2109#define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
2110
2111#define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
2112
2113#define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
2114
2115#define A_MC5_DB_SYN_SRCH_CMD 0x7dc
2116
2117#define A_MC5_DB_SYN_LRN_CMD 0x7e0
2118
2119#define A_MC5_DB_ACK_SRCH_CMD 0x7e4
2120
2121#define A_MC5_DB_ACK_LRN_CMD 0x7e8
2122
2123#define A_MC5_DB_ILOOKUP_CMD 0x7ec
2124
2125#define A_MC5_DB_ELOOKUP_CMD 0x7f0
2126
2127#define A_MC5_DB_DATA_WRITE_CMD 0x7f4
2128
2129#define A_MC5_DB_DATA_READ_CMD 0x7f8
2130
2131#define XGMAC0_0_BASE_ADDR 0x800
2132
2133#define A_XGM_TX_CTRL 0x800
2134
2135#define S_TXEN    0
2136#define V_TXEN(x) ((x) << S_TXEN)
2137#define F_TXEN    V_TXEN(1U)
2138
2139#define A_XGM_TX_CFG 0x804
2140
2141#define S_TXPAUSEEN    0
2142#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
2143#define F_TXPAUSEEN    V_TXPAUSEEN(1U)
2144
2145#define A_XGM_TX_PAUSE_QUANTA 0x808
2146
2147#define A_XGM_RX_CTRL 0x80c
2148
2149#define S_RXEN    0
2150#define V_RXEN(x) ((x) << S_RXEN)
2151#define F_RXEN    V_RXEN(1U)
2152
2153#define A_XGM_RX_CFG 0x810
2154
2155#define S_DISPAUSEFRAMES    9
2156#define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
2157#define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
2158
2159#define S_EN1536BFRAMES    8
2160#define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
2161#define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
2162
2163#define S_ENJUMBO    7
2164#define V_ENJUMBO(x) ((x) << S_ENJUMBO)
2165#define F_ENJUMBO    V_ENJUMBO(1U)
2166
2167#define S_RMFCS    6
2168#define V_RMFCS(x) ((x) << S_RMFCS)
2169#define F_RMFCS    V_RMFCS(1U)
2170
2171#define S_ENHASHMCAST    2
2172#define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
2173#define F_ENHASHMCAST    V_ENHASHMCAST(1U)
2174
2175#define S_COPYALLFRAMES    0
2176#define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
2177#define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
2178
2179#define S_DISBCAST    1
2180#define V_DISBCAST(x) ((x) << S_DISBCAST)
2181#define F_DISBCAST    V_DISBCAST(1U)
2182
2183#define A_XGM_RX_HASH_LOW 0x814
2184
2185#define A_XGM_RX_HASH_HIGH 0x818
2186
2187#define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
2188
2189#define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
2190
2191#define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
2192
2193#define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
2194
2195#define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
2196
2197#define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
2198
2199#define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
2200
2201#define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
2202
2203#define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
2204
2205#define A_XGM_INT_STATUS 0x86c
2206
2207#define S_LINKFAULTCHANGE    9
2208#define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
2209#define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
2210
2211#define A_XGM_XGM_INT_ENABLE 0x874
2212#define A_XGM_XGM_INT_DISABLE 0x878
2213
2214#define A_XGM_STAT_CTRL 0x880
2215
2216#define S_CLRSTATS    2
2217#define V_CLRSTATS(x) ((x) << S_CLRSTATS)
2218#define F_CLRSTATS    V_CLRSTATS(1U)
2219
2220#define A_XGM_RXFIFO_CFG 0x884
2221
2222#define S_RXFIFO_EMPTY    31
2223#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
2224#define F_RXFIFO_EMPTY    V_RXFIFO_EMPTY(1U)
2225
2226#define S_RXFIFOPAUSEHWM    17
2227#define M_RXFIFOPAUSEHWM    0xfff
2228
2229#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
2230
2231#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
2232
2233#define S_RXFIFOPAUSELWM    5
2234#define M_RXFIFOPAUSELWM    0xfff
2235
2236#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
2237
2238#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
2239
2240#define S_RXSTRFRWRD    1
2241#define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
2242#define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
2243
2244#define S_DISERRFRAMES    0
2245#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
2246#define F_DISERRFRAMES    V_DISERRFRAMES(1U)
2247
2248#define A_XGM_TXFIFO_CFG 0x888
2249
2250#define S_UNDERUNFIX    22
2251#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
2252#define F_UNDERUNFIX    V_UNDERUNFIX(1U)
2253
2254#define S_TXIPG    13
2255#define M_TXIPG    0xff
2256#define V_TXIPG(x) ((x) << S_TXIPG)
2257#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
2258
2259#define S_TXFIFOTHRESH    4
2260#define M_TXFIFOTHRESH    0x1ff
2261
2262#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
2263
2264#define S_ENDROPPKT    21
2265#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
2266#define F_ENDROPPKT    V_ENDROPPKT(1U)
2267
2268#define A_XGM_SERDES_CTRL 0x890
2269#define A_XGM_SERDES_CTRL0 0x8e0
2270
2271#define S_SERDESRESET_    24
2272#define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
2273#define F_SERDESRESET_    V_SERDESRESET_(1U)
2274
2275#define S_RXENABLE    4
2276#define V_RXENABLE(x) ((x) << S_RXENABLE)
2277#define F_RXENABLE    V_RXENABLE(1U)
2278
2279#define S_TXENABLE    3
2280#define V_TXENABLE(x) ((x) << S_TXENABLE)
2281#define F_TXENABLE    V_TXENABLE(1U)
2282
2283#define A_XGM_PAUSE_TIMER 0x890
2284
2285#define A_XGM_RGMII_IMP 0x89c
2286
2287#define S_XGM_IMPSETUPDATE    6
2288#define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
2289#define F_XGM_IMPSETUPDATE    V_XGM_IMPSETUPDATE(1U)
2290
2291#define S_RGMIIIMPPD    3
2292#define M_RGMIIIMPPD    0x7
2293#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
2294
2295#define S_RGMIIIMPPU    0
2296#define M_RGMIIIMPPU    0x7
2297#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
2298
2299#define S_CALRESET    8
2300#define V_CALRESET(x) ((x) << S_CALRESET)
2301#define F_CALRESET    V_CALRESET(1U)
2302
2303#define S_CALUPDATE    7
2304#define V_CALUPDATE(x) ((x) << S_CALUPDATE)
2305#define F_CALUPDATE    V_CALUPDATE(1U)
2306
2307#define A_XGM_XAUI_IMP 0x8a0
2308
2309#define S_CALBUSY    31
2310#define V_CALBUSY(x) ((x) << S_CALBUSY)
2311#define F_CALBUSY    V_CALBUSY(1U)
2312
2313#define S_XGM_CALFAULT    29
2314#define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
2315#define F_XGM_CALFAULT    V_XGM_CALFAULT(1U)
2316
2317#define S_CALIMP    24
2318#define M_CALIMP    0x1f
2319#define V_CALIMP(x) ((x) << S_CALIMP)
2320#define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
2321
2322#define S_XAUIIMP    0
2323#define M_XAUIIMP    0x7
2324#define V_XAUIIMP(x) ((x) << S_XAUIIMP)
2325
2326#define A_XGM_RX_MAX_PKT_SIZE 0x8a8
2327
2328#define S_RXMAXFRAMERSIZE    17
2329#define M_RXMAXFRAMERSIZE    0x3fff
2330#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
2331#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
2332
2333#define S_RXENFRAMER    14
2334#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
2335#define F_RXENFRAMER    V_RXENFRAMER(1U)
2336
2337#define S_RXMAXPKTSIZE    0
2338#define M_RXMAXPKTSIZE    0x3fff
2339#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
2340#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
2341
2342#define A_XGM_RESET_CTRL 0x8ac
2343
2344#define S_XGMAC_STOP_EN    4
2345#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
2346#define F_XGMAC_STOP_EN    V_XGMAC_STOP_EN(1U)
2347
2348#define S_XG2G_RESET_    3
2349#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
2350#define F_XG2G_RESET_    V_XG2G_RESET_(1U)
2351
2352#define S_RGMII_RESET_    2
2353#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
2354#define F_RGMII_RESET_    V_RGMII_RESET_(1U)
2355
2356#define S_PCS_RESET_    1
2357#define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
2358#define F_PCS_RESET_    V_PCS_RESET_(1U)
2359
2360#define S_MAC_RESET_    0
2361#define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
2362#define F_MAC_RESET_    V_MAC_RESET_(1U)
2363
2364#define A_XGM_PORT_CFG 0x8b8
2365
2366#define S_CLKDIVRESET_    3
2367#define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
2368#define F_CLKDIVRESET_    V_CLKDIVRESET_(1U)
2369
2370#define S_PORTSPEED    1
2371#define M_PORTSPEED    0x3
2372
2373#define V_PORTSPEED(x) ((x) << S_PORTSPEED)
2374
2375#define S_ENRGMII    0
2376#define V_ENRGMII(x) ((x) << S_ENRGMII)
2377#define F_ENRGMII    V_ENRGMII(1U)
2378
2379#define A_XGM_INT_ENABLE 0x8d4
2380
2381#define S_TXFIFO_PRTY_ERR    17
2382#define M_TXFIFO_PRTY_ERR    0x7
2383
2384#define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
2385
2386#define S_RXFIFO_PRTY_ERR    14
2387#define M_RXFIFO_PRTY_ERR    0x7
2388
2389#define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
2390
2391#define S_TXFIFO_UNDERRUN    13
2392#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
2393#define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
2394
2395#define S_RXFIFO_OVERFLOW    12
2396#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
2397#define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
2398
2399#define S_SERDES_LOS    4
2400#define M_SERDES_LOS    0xf
2401
2402#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
2403
2404#define S_XAUIPCSCTCERR    3
2405#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
2406#define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
2407
2408#define S_XAUIPCSALIGNCHANGE    2
2409#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
2410#define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
2411
2412#define S_XGM_INT    0
2413#define V_XGM_INT(x) ((x) << S_XGM_INT)
2414#define F_XGM_INT    V_XGM_INT(1U)
2415
2416#define A_XGM_INT_CAUSE 0x8d8
2417
2418#define A_XGM_XAUI_ACT_CTRL 0x8dc
2419
2420#define S_TXACTENABLE    1
2421#define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
2422#define F_TXACTENABLE    V_TXACTENABLE(1U)
2423
2424#define S_RESET3    23
2425#define V_RESET3(x) ((x) << S_RESET3)
2426#define F_RESET3    V_RESET3(1U)
2427
2428#define S_RESET2    22
2429#define V_RESET2(x) ((x) << S_RESET2)
2430#define F_RESET2    V_RESET2(1U)
2431
2432#define S_RESET1    21
2433#define V_RESET1(x) ((x) << S_RESET1)
2434#define F_RESET1    V_RESET1(1U)
2435
2436#define S_RESET0    20
2437#define V_RESET0(x) ((x) << S_RESET0)
2438#define F_RESET0    V_RESET0(1U)
2439
2440#define S_PWRDN3    19
2441#define V_PWRDN3(x) ((x) << S_PWRDN3)
2442#define F_PWRDN3    V_PWRDN3(1U)
2443
2444#define S_PWRDN2    18
2445#define V_PWRDN2(x) ((x) << S_PWRDN2)
2446#define F_PWRDN2    V_PWRDN2(1U)
2447
2448#define S_PWRDN1    17
2449#define V_PWRDN1(x) ((x) << S_PWRDN1)
2450#define F_PWRDN1    V_PWRDN1(1U)
2451
2452#define S_PWRDN0    16
2453#define V_PWRDN0(x) ((x) << S_PWRDN0)
2454#define F_PWRDN0    V_PWRDN0(1U)
2455
2456#define S_RESETPLL23    15
2457#define V_RESETPLL23(x) ((x) << S_RESETPLL23)
2458#define F_RESETPLL23    V_RESETPLL23(1U)
2459
2460#define S_RESETPLL01    14
2461#define V_RESETPLL01(x) ((x) << S_RESETPLL01)
2462#define F_RESETPLL01    V_RESETPLL01(1U)
2463
2464#define A_XGM_SERDES_STAT0 0x8f0
2465#define A_XGM_SERDES_STAT1 0x8f4
2466#define A_XGM_SERDES_STAT2 0x8f8
2467
2468#define S_LOWSIG0    0
2469#define V_LOWSIG0(x) ((x) << S_LOWSIG0)
2470#define F_LOWSIG0    V_LOWSIG0(1U)
2471
2472#define A_XGM_SERDES_STAT3 0x8fc
2473
2474#define A_XGM_STAT_TX_BYTE_LOW 0x900
2475
2476#define A_XGM_STAT_TX_BYTE_HIGH 0x904
2477
2478#define A_XGM_STAT_TX_FRAME_LOW 0x908
2479
2480#define A_XGM_STAT_TX_FRAME_HIGH 0x90c
2481
2482#define A_XGM_STAT_TX_BCAST 0x910
2483
2484#define A_XGM_STAT_TX_MCAST 0x914
2485
2486#define A_XGM_STAT_TX_PAUSE 0x918
2487
2488#define A_XGM_STAT_TX_64B_FRAMES 0x91c
2489
2490#define A_XGM_STAT_TX_65_127B_FRAMES 0x920
2491
2492#define A_XGM_STAT_TX_128_255B_FRAMES 0x924
2493
2494#define A_XGM_STAT_TX_256_511B_FRAMES 0x928
2495
2496#define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
2497
2498#define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
2499
2500#define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
2501
2502#define A_XGM_STAT_TX_ERR_FRAMES 0x938
2503
2504#define A_XGM_STAT_RX_BYTES_LOW 0x93c
2505
2506#define A_XGM_STAT_RX_BYTES_HIGH 0x940
2507
2508#define A_XGM_STAT_RX_FRAMES_LOW 0x944
2509
2510#define A_XGM_STAT_RX_FRAMES_HIGH 0x948
2511
2512#define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
2513
2514#define A_XGM_STAT_RX_MCAST_FRAMES 0x950
2515
2516#define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
2517
2518#define A_XGM_STAT_RX_64B_FRAMES 0x958
2519
2520#define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
2521
2522#define A_XGM_STAT_RX_128_255B_FRAMES 0x960
2523
2524#define A_XGM_STAT_RX_256_511B_FRAMES 0x964
2525
2526#define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
2527
2528#define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
2529
2530#define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
2531
2532#define A_XGM_STAT_RX_SHORT_FRAMES 0x974
2533
2534#define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
2535
2536#define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
2537
2538#define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
2539
2540#define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
2541
2542#define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
2543
2544#define A_XGM_SERDES_STATUS0 0x98c
2545
2546#define A_XGM_SERDES_STATUS1 0x990
2547
2548#define S_CMULOCK    31
2549#define V_CMULOCK(x) ((x) << S_CMULOCK)
2550#define F_CMULOCK    V_CMULOCK(1U)
2551
2552#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2553
2554#define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2555
2556#define S_TXSPI4SOPCNT    16
2557#define M_TXSPI4SOPCNT    0xffff
2558#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
2559#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
2560
2561#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2562
2563#define XGMAC0_1_BASE_ADDR 0xa00
2564