1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_ADMINQ_CMD_H_ 28#define _I40E_ADMINQ_CMD_H_ 29 30/* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36#define I40E_FW_API_VERSION_MAJOR 0x0001 37#define I40E_FW_API_VERSION_MINOR 0x0002 38 39struct i40e_aq_desc { 40 __le16 flags; 41 __le16 opcode; 42 __le16 datalen; 43 __le16 retval; 44 __le32 cookie_high; 45 __le32 cookie_low; 46 union { 47 struct { 48 __le32 param0; 49 __le32 param1; 50 __le32 param2; 51 __le32 param3; 52 } internal; 53 struct { 54 __le32 param0; 55 __le32 param1; 56 __le32 addr_high; 57 __le32 addr_low; 58 } external; 59 u8 raw[16]; 60 } params; 61}; 62 63/* Flags sub-structure 64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 66 */ 67 68/* command flags and offsets*/ 69#define I40E_AQ_FLAG_DD_SHIFT 0 70#define I40E_AQ_FLAG_CMP_SHIFT 1 71#define I40E_AQ_FLAG_ERR_SHIFT 2 72#define I40E_AQ_FLAG_VFE_SHIFT 3 73#define I40E_AQ_FLAG_LB_SHIFT 9 74#define I40E_AQ_FLAG_RD_SHIFT 10 75#define I40E_AQ_FLAG_VFC_SHIFT 11 76#define I40E_AQ_FLAG_BUF_SHIFT 12 77#define I40E_AQ_FLAG_SI_SHIFT 13 78#define I40E_AQ_FLAG_EI_SHIFT 14 79#define I40E_AQ_FLAG_FE_SHIFT 15 80 81#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 82#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 83#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 84#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 85#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 86#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 87#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 88#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 89#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 90#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 91#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 92 93/* error codes */ 94enum i40e_admin_queue_err { 95 I40E_AQ_RC_OK = 0, /* success */ 96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 97 I40E_AQ_RC_ENOENT = 2, /* No such element */ 98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 100 I40E_AQ_RC_EIO = 5, /* I/O error */ 101 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 103 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 105 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 106 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 108 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */ 115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 117 I40E_AQ_RC_EFBIG = 22, /* File too large */ 118}; 119 120/* Admin Queue command opcodes */ 121enum i40e_admin_queue_opc { 122 /* aq commands */ 123 i40e_aqc_opc_get_version = 0x0001, 124 i40e_aqc_opc_driver_version = 0x0002, 125 i40e_aqc_opc_queue_shutdown = 0x0003, 126 i40e_aqc_opc_set_pf_context = 0x0004, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 i40e_aqc_opc_set_cppm_configuration = 0x0103, 136 i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 137 i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 138 139 /* LAA */ 140 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 141 i40e_aqc_opc_mac_address_read = 0x0107, 142 i40e_aqc_opc_mac_address_write = 0x0108, 143 144 /* PXE */ 145 i40e_aqc_opc_clear_pxe_mode = 0x0110, 146 147 /* internal switch commands */ 148 i40e_aqc_opc_get_switch_config = 0x0200, 149 i40e_aqc_opc_add_statistics = 0x0201, 150 i40e_aqc_opc_remove_statistics = 0x0202, 151 i40e_aqc_opc_set_port_parameters = 0x0203, 152 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 153 154 i40e_aqc_opc_add_vsi = 0x0210, 155 i40e_aqc_opc_update_vsi_parameters = 0x0211, 156 i40e_aqc_opc_get_vsi_parameters = 0x0212, 157 158 i40e_aqc_opc_add_pv = 0x0220, 159 i40e_aqc_opc_update_pv_parameters = 0x0221, 160 i40e_aqc_opc_get_pv_parameters = 0x0222, 161 162 i40e_aqc_opc_add_veb = 0x0230, 163 i40e_aqc_opc_update_veb_parameters = 0x0231, 164 i40e_aqc_opc_get_veb_parameters = 0x0232, 165 166 i40e_aqc_opc_delete_element = 0x0243, 167 168 i40e_aqc_opc_add_macvlan = 0x0250, 169 i40e_aqc_opc_remove_macvlan = 0x0251, 170 i40e_aqc_opc_add_vlan = 0x0252, 171 i40e_aqc_opc_remove_vlan = 0x0253, 172 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 173 i40e_aqc_opc_add_tag = 0x0255, 174 i40e_aqc_opc_remove_tag = 0x0256, 175 i40e_aqc_opc_add_multicast_etag = 0x0257, 176 i40e_aqc_opc_remove_multicast_etag = 0x0258, 177 i40e_aqc_opc_update_tag = 0x0259, 178 i40e_aqc_opc_add_control_packet_filter = 0x025A, 179 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 180 i40e_aqc_opc_add_cloud_filters = 0x025C, 181 i40e_aqc_opc_remove_cloud_filters = 0x025D, 182 183 i40e_aqc_opc_add_mirror_rule = 0x0260, 184 i40e_aqc_opc_delete_mirror_rule = 0x0261, 185 186 /* DCB commands */ 187 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 188 i40e_aqc_opc_dcb_updated = 0x0302, 189 190 /* TX scheduler */ 191 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 192 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 193 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 194 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 195 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 196 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 197 198 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 199 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 200 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 201 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 202 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 203 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 204 i40e_aqc_opc_query_port_ets_config = 0x0419, 205 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 206 i40e_aqc_opc_suspend_port_tx = 0x041B, 207 i40e_aqc_opc_resume_port_tx = 0x041C, 208 i40e_aqc_opc_configure_partition_bw = 0x041D, 209 210 /* hmc */ 211 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 212 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 213 214 /* phy commands*/ 215 i40e_aqc_opc_get_phy_abilities = 0x0600, 216 i40e_aqc_opc_set_phy_config = 0x0601, 217 i40e_aqc_opc_set_mac_config = 0x0603, 218 i40e_aqc_opc_set_link_restart_an = 0x0605, 219 i40e_aqc_opc_get_link_status = 0x0607, 220 i40e_aqc_opc_set_phy_int_mask = 0x0613, 221 i40e_aqc_opc_get_local_advt_reg = 0x0614, 222 i40e_aqc_opc_set_local_advt_reg = 0x0615, 223 i40e_aqc_opc_get_partner_advt = 0x0616, 224 i40e_aqc_opc_set_lb_modes = 0x0618, 225 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 226 i40e_aqc_opc_set_phy_debug = 0x0622, 227 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 228 229 /* NVM commands */ 230 i40e_aqc_opc_nvm_read = 0x0701, 231 i40e_aqc_opc_nvm_erase = 0x0702, 232 i40e_aqc_opc_nvm_update = 0x0703, 233 i40e_aqc_opc_nvm_config_read = 0x0704, 234 i40e_aqc_opc_nvm_config_write = 0x0705, 235 236 /* virtualization commands */ 237 i40e_aqc_opc_send_msg_to_pf = 0x0801, 238 i40e_aqc_opc_send_msg_to_vf = 0x0802, 239 i40e_aqc_opc_send_msg_to_peer = 0x0803, 240 241 /* alternate structure */ 242 i40e_aqc_opc_alternate_write = 0x0900, 243 i40e_aqc_opc_alternate_write_indirect = 0x0901, 244 i40e_aqc_opc_alternate_read = 0x0902, 245 i40e_aqc_opc_alternate_read_indirect = 0x0903, 246 i40e_aqc_opc_alternate_write_done = 0x0904, 247 i40e_aqc_opc_alternate_set_mode = 0x0905, 248 i40e_aqc_opc_alternate_clear_port = 0x0906, 249 250 /* LLDP commands */ 251 i40e_aqc_opc_lldp_get_mib = 0x0A00, 252 i40e_aqc_opc_lldp_update_mib = 0x0A01, 253 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 254 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 255 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 256 i40e_aqc_opc_lldp_stop = 0x0A05, 257 i40e_aqc_opc_lldp_start = 0x0A06, 258 259 /* Tunnel commands */ 260 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 261 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 262 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 263 264 /* Async Events */ 265 i40e_aqc_opc_event_lan_overflow = 0x1001, 266 267 /* OEM commands */ 268 i40e_aqc_opc_oem_parameter_change = 0xFE00, 269 i40e_aqc_opc_oem_device_status_change = 0xFE01, 270 271 /* debug commands */ 272 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 273 i40e_aqc_opc_debug_set_mode = 0xFF01, 274 i40e_aqc_opc_debug_read_reg = 0xFF03, 275 i40e_aqc_opc_debug_write_reg = 0xFF04, 276 i40e_aqc_opc_debug_modify_reg = 0xFF07, 277 i40e_aqc_opc_debug_dump_internals = 0xFF08, 278 i40e_aqc_opc_debug_modify_internals = 0xFF09, 279}; 280 281/* command structures and indirect data structures */ 282 283/* Structure naming conventions: 284 * - no suffix for direct command descriptor structures 285 * - _data for indirect sent data 286 * - _resp for indirect return data (data which is both will use _data) 287 * - _completion for direct return data 288 * - _element_ for repeated elements (may also be _data or _resp) 289 * 290 * Command structures are expected to overlay the params.raw member of the basic 291 * descriptor, and as such cannot exceed 16 bytes in length. 292 */ 293 294/* This macro is used to generate a compilation error if a structure 295 * is not exactly the correct length. It gives a divide by zero error if the 296 * structure is not of the correct size, otherwise it creates an enum that is 297 * never used. 298 */ 299#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 300 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 301 302/* This macro is used extensively to ensure that command structures are 16 303 * bytes in length as they have to map to the raw array of that size. 304 */ 305#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 306 307/* internal (0x00XX) commands */ 308 309/* Get version (direct 0x0001) */ 310struct i40e_aqc_get_version { 311 __le32 rom_ver; 312 __le32 fw_build; 313 __le16 fw_major; 314 __le16 fw_minor; 315 __le16 api_major; 316 __le16 api_minor; 317}; 318 319I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 320 321/* Send driver version (indirect 0x0002) */ 322struct i40e_aqc_driver_version { 323 u8 driver_major_ver; 324 u8 driver_minor_ver; 325 u8 driver_build_ver; 326 u8 driver_subbuild_ver; 327 u8 reserved[4]; 328 __le32 address_high; 329 __le32 address_low; 330}; 331 332I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 333 334/* Queue Shutdown (direct 0x0003) */ 335struct i40e_aqc_queue_shutdown { 336 __le32 driver_unloading; 337#define I40E_AQ_DRIVER_UNLOADING 0x1 338 u8 reserved[12]; 339}; 340 341I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 342 343/* Set PF context (0x0004, direct) */ 344struct i40e_aqc_set_pf_context { 345 u8 pf_id; 346 u8 reserved[15]; 347}; 348 349I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 350 351/* Request resource ownership (direct 0x0008) 352 * Release resource ownership (direct 0x0009) 353 */ 354#define I40E_AQ_RESOURCE_NVM 1 355#define I40E_AQ_RESOURCE_SDP 2 356#define I40E_AQ_RESOURCE_ACCESS_READ 1 357#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 358#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 359#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 360 361struct i40e_aqc_request_resource { 362 __le16 resource_id; 363 __le16 access_type; 364 __le32 timeout; 365 __le32 resource_number; 366 u8 reserved[4]; 367}; 368 369I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 370 371/* Get function capabilities (indirect 0x000A) 372 * Get device capabilities (indirect 0x000B) 373 */ 374struct i40e_aqc_list_capabilites { 375 u8 command_flags; 376#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 377 u8 pf_index; 378 u8 reserved[2]; 379 __le32 count; 380 __le32 addr_high; 381 __le32 addr_low; 382}; 383 384I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 385 386struct i40e_aqc_list_capabilities_element_resp { 387 __le16 id; 388 u8 major_rev; 389 u8 minor_rev; 390 __le32 number; 391 __le32 logical_id; 392 __le32 phys_id; 393 u8 reserved[16]; 394}; 395 396/* list of caps */ 397 398#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 399#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 400#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 401#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 402#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 403#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 404#define I40E_AQ_CAP_ID_SRIOV 0x0012 405#define I40E_AQ_CAP_ID_VF 0x0013 406#define I40E_AQ_CAP_ID_VMDQ 0x0014 407#define I40E_AQ_CAP_ID_8021QBG 0x0015 408#define I40E_AQ_CAP_ID_8021QBR 0x0016 409#define I40E_AQ_CAP_ID_VSI 0x0017 410#define I40E_AQ_CAP_ID_DCB 0x0018 411#define I40E_AQ_CAP_ID_FCOE 0x0021 412#define I40E_AQ_CAP_ID_RSS 0x0040 413#define I40E_AQ_CAP_ID_RXQ 0x0041 414#define I40E_AQ_CAP_ID_TXQ 0x0042 415#define I40E_AQ_CAP_ID_MSIX 0x0043 416#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 417#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 418#define I40E_AQ_CAP_ID_1588 0x0046 419#define I40E_AQ_CAP_ID_IWARP 0x0051 420#define I40E_AQ_CAP_ID_LED 0x0061 421#define I40E_AQ_CAP_ID_SDP 0x0062 422#define I40E_AQ_CAP_ID_MDIO 0x0063 423#define I40E_AQ_CAP_ID_FLEX10 0x00F1 424#define I40E_AQ_CAP_ID_CEM 0x00F2 425 426/* Set CPPM Configuration (direct 0x0103) */ 427struct i40e_aqc_cppm_configuration { 428 __le16 command_flags; 429#define I40E_AQ_CPPM_EN_LTRC 0x0800 430#define I40E_AQ_CPPM_EN_DMCTH 0x1000 431#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 432#define I40E_AQ_CPPM_EN_HPTC 0x4000 433#define I40E_AQ_CPPM_EN_DMARC 0x8000 434 __le16 ttlx; 435 __le32 dmacr; 436 __le16 dmcth; 437 u8 hptc; 438 u8 reserved; 439 __le32 pfltrc; 440}; 441 442I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 443 444/* Set ARP Proxy command / response (indirect 0x0104) */ 445struct i40e_aqc_arp_proxy_data { 446 __le16 command_flags; 447#define I40E_AQ_ARP_INIT_IPV4 0x0008 448#define I40E_AQ_ARP_UNSUP_CTL 0x0010 449#define I40E_AQ_ARP_ENA 0x0020 450#define I40E_AQ_ARP_ADD_IPV4 0x0040 451#define I40E_AQ_ARP_DEL_IPV4 0x0080 452 __le16 table_id; 453 __le32 pfpm_proxyfc; 454 __le32 ip_addr; 455 u8 mac_addr[6]; 456}; 457 458/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 459struct i40e_aqc_ns_proxy_data { 460 __le16 table_idx_mac_addr_0; 461 __le16 table_idx_mac_addr_1; 462 __le16 table_idx_ipv6_0; 463 __le16 table_idx_ipv6_1; 464 __le16 control; 465#define I40E_AQ_NS_PROXY_ADD_0 0x0100 466#define I40E_AQ_NS_PROXY_DEL_0 0x0200 467#define I40E_AQ_NS_PROXY_ADD_1 0x0400 468#define I40E_AQ_NS_PROXY_DEL_1 0x0800 469#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 470#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 471#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 472#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 473#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 474#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 475#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 476 u8 mac_addr_0[6]; 477 u8 mac_addr_1[6]; 478 u8 local_mac_addr[6]; 479 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 480 u8 ipv6_addr_1[16]; 481}; 482 483/* Manage LAA Command (0x0106) - obsolete */ 484struct i40e_aqc_mng_laa { 485 __le16 command_flags; 486#define I40E_AQ_LAA_FLAG_WR 0x8000 487 u8 reserved[2]; 488 __le32 sal; 489 __le16 sah; 490 u8 reserved2[6]; 491}; 492 493/* Manage MAC Address Read Command (indirect 0x0107) */ 494struct i40e_aqc_mac_address_read { 495 __le16 command_flags; 496#define I40E_AQC_LAN_ADDR_VALID 0x10 497#define I40E_AQC_SAN_ADDR_VALID 0x20 498#define I40E_AQC_PORT_ADDR_VALID 0x40 499#define I40E_AQC_WOL_ADDR_VALID 0x80 500#define I40E_AQC_ADDR_VALID_MASK 0xf0 501 u8 reserved[6]; 502 __le32 addr_high; 503 __le32 addr_low; 504}; 505 506I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 507 508struct i40e_aqc_mac_address_read_data { 509 u8 pf_lan_mac[6]; 510 u8 pf_san_mac[6]; 511 u8 port_mac[6]; 512 u8 pf_wol_mac[6]; 513}; 514 515I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 516 517/* Manage MAC Address Write Command (0x0108) */ 518struct i40e_aqc_mac_address_write { 519 __le16 command_flags; 520#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 521#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 522#define I40E_AQC_WRITE_TYPE_PORT 0x8000 523#define I40E_AQC_WRITE_TYPE_MASK 0xc000 524 __le16 mac_sah; 525 __le32 mac_sal; 526 u8 reserved[8]; 527}; 528 529I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 530 531/* PXE commands (0x011x) */ 532 533/* Clear PXE Command and response (direct 0x0110) */ 534struct i40e_aqc_clear_pxe { 535 u8 rx_cnt; 536 u8 reserved[15]; 537}; 538 539I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 540 541/* Switch configuration commands (0x02xx) */ 542 543/* Used by many indirect commands that only pass an seid and a buffer in the 544 * command 545 */ 546struct i40e_aqc_switch_seid { 547 __le16 seid; 548 u8 reserved[6]; 549 __le32 addr_high; 550 __le32 addr_low; 551}; 552 553I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 554 555/* Get Switch Configuration command (indirect 0x0200) 556 * uses i40e_aqc_switch_seid for the descriptor 557 */ 558struct i40e_aqc_get_switch_config_header_resp { 559 __le16 num_reported; 560 __le16 num_total; 561 u8 reserved[12]; 562}; 563 564struct i40e_aqc_switch_config_element_resp { 565 u8 element_type; 566#define I40E_AQ_SW_ELEM_TYPE_MAC 1 567#define I40E_AQ_SW_ELEM_TYPE_PF 2 568#define I40E_AQ_SW_ELEM_TYPE_VF 3 569#define I40E_AQ_SW_ELEM_TYPE_EMP 4 570#define I40E_AQ_SW_ELEM_TYPE_BMC 5 571#define I40E_AQ_SW_ELEM_TYPE_PV 16 572#define I40E_AQ_SW_ELEM_TYPE_VEB 17 573#define I40E_AQ_SW_ELEM_TYPE_PA 18 574#define I40E_AQ_SW_ELEM_TYPE_VSI 19 575 u8 revision; 576#define I40E_AQ_SW_ELEM_REV_1 1 577 __le16 seid; 578 __le16 uplink_seid; 579 __le16 downlink_seid; 580 u8 reserved[3]; 581 u8 connection_type; 582#define I40E_AQ_CONN_TYPE_REGULAR 0x1 583#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 584#define I40E_AQ_CONN_TYPE_CASCADED 0x3 585 __le16 scheduler_id; 586 __le16 element_info; 587}; 588 589/* Get Switch Configuration (indirect 0x0200) 590 * an array of elements are returned in the response buffer 591 * the first in the array is the header, remainder are elements 592 */ 593struct i40e_aqc_get_switch_config_resp { 594 struct i40e_aqc_get_switch_config_header_resp header; 595 struct i40e_aqc_switch_config_element_resp element[1]; 596}; 597 598/* Add Statistics (direct 0x0201) 599 * Remove Statistics (direct 0x0202) 600 */ 601struct i40e_aqc_add_remove_statistics { 602 __le16 seid; 603 __le16 vlan; 604 __le16 stat_index; 605 u8 reserved[10]; 606}; 607 608I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 609 610/* Set Port Parameters command (direct 0x0203) */ 611struct i40e_aqc_set_port_parameters { 612 __le16 command_flags; 613#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 614#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 615#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 616 __le16 bad_frame_vsi; 617 __le16 default_seid; /* reserved for command */ 618 u8 reserved[10]; 619}; 620 621I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 622 623/* Get Switch Resource Allocation (indirect 0x0204) */ 624struct i40e_aqc_get_switch_resource_alloc { 625 u8 num_entries; /* reserved for command */ 626 u8 reserved[7]; 627 __le32 addr_high; 628 __le32 addr_low; 629}; 630 631I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 632 633/* expect an array of these structs in the response buffer */ 634struct i40e_aqc_switch_resource_alloc_element_resp { 635 u8 resource_type; 636#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 637#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 638#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 639#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 640#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 641#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 642#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 643#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 644#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 645#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 646#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 647#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 648#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 649#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 650#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 651#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 652#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 653#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 654#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 655 u8 reserved1; 656 __le16 guaranteed; 657 __le16 total; 658 __le16 used; 659 __le16 total_unalloced; 660 u8 reserved2[6]; 661}; 662 663/* Add VSI (indirect 0x0210) 664 * this indirect command uses struct i40e_aqc_vsi_properties_data 665 * as the indirect buffer (128 bytes) 666 * 667 * Update VSI (indirect 0x211) 668 * uses the same data structure as Add VSI 669 * 670 * Get VSI (indirect 0x0212) 671 * uses the same completion and data structure as Add VSI 672 */ 673struct i40e_aqc_add_get_update_vsi { 674 __le16 uplink_seid; 675 u8 connection_type; 676#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 677#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 678#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 679 u8 reserved1; 680 u8 vf_id; 681 u8 reserved2; 682 __le16 vsi_flags; 683#define I40E_AQ_VSI_TYPE_SHIFT 0x0 684#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 685#define I40E_AQ_VSI_TYPE_VF 0x0 686#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 687#define I40E_AQ_VSI_TYPE_PF 0x2 688#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 689#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 690 __le32 addr_high; 691 __le32 addr_low; 692}; 693 694I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 695 696struct i40e_aqc_add_get_update_vsi_completion { 697 __le16 seid; 698 __le16 vsi_number; 699 __le16 vsi_used; 700 __le16 vsi_free; 701 __le32 addr_high; 702 __le32 addr_low; 703}; 704 705I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 706 707struct i40e_aqc_vsi_properties_data { 708 /* first 96 byte are written by SW */ 709 __le16 valid_sections; 710#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 711#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 712#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 713#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 714#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 715#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 716#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 717#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 718#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 719#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 720 /* switch section */ 721 __le16 switch_id; /* 12bit id combined with flags below */ 722#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 723#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 724#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 725#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 726#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 727 u8 sw_reserved[2]; 728 /* security section */ 729 u8 sec_flags; 730#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 731#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 732#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 733 u8 sec_reserved; 734 /* VLAN section */ 735 __le16 pvid; /* VLANS include priority bits */ 736 __le16 fcoe_pvid; 737 u8 port_vlan_flags; 738#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 739#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 740 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 741#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 742#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 743#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 744#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 745#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 746#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 747 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 748#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 749#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 750#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 751#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 752 u8 pvlan_reserved[3]; 753 /* ingress egress up sections */ 754 __le32 ingress_table; /* bitmap, 3 bits per up */ 755#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 756#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 757 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 758#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 759#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 760 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 761#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 762#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 763 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 764#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 765#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 766 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 767#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 768#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 769 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 770#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 771#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 772 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 773#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 774#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 775 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 776#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 777#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 778 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 779 __le32 egress_table; /* same defines as for ingress table */ 780 /* cascaded PV section */ 781 __le16 cas_pv_tag; 782 u8 cas_pv_flags; 783#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 784#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 785 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 786#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 787#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 788#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 789#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 790#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 791#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 792 u8 cas_pv_reserved; 793 /* queue mapping section */ 794 __le16 mapping_flags; 795#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 796#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 797 __le16 queue_mapping[16]; 798#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 799#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 800 __le16 tc_mapping[8]; 801#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 802#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 803 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 804#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 805#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 806 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 807 /* queueing option section */ 808 u8 queueing_opt_flags; 809#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 810#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 811 u8 queueing_opt_reserved[3]; 812 /* scheduler section */ 813 u8 up_enable_bits; 814 u8 sched_reserved; 815 /* outer up section */ 816 __le32 outer_up_table; /* same structure and defines as ingress table */ 817 u8 cmd_reserved[8]; 818 /* last 32 bytes are written by FW */ 819 __le16 qs_handle[8]; 820#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 821 __le16 stat_counter_idx; 822 __le16 sched_id; 823 u8 resp_reserved[12]; 824}; 825 826I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 827 828/* Add Port Virtualizer (direct 0x0220) 829 * also used for update PV (direct 0x0221) but only flags are used 830 * (IS_CTRL_PORT only works on add PV) 831 */ 832struct i40e_aqc_add_update_pv { 833 __le16 command_flags; 834#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 835#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 836#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 837#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 838 __le16 uplink_seid; 839 __le16 connected_seid; 840 u8 reserved[10]; 841}; 842 843I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 844 845struct i40e_aqc_add_update_pv_completion { 846 /* reserved for update; for add also encodes error if rc == ENOSPC */ 847 __le16 pv_seid; 848#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 849#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 850#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 851#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 852 u8 reserved[14]; 853}; 854 855I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 856 857/* Get PV Params (direct 0x0222) 858 * uses i40e_aqc_switch_seid for the descriptor 859 */ 860 861struct i40e_aqc_get_pv_params_completion { 862 __le16 seid; 863 __le16 default_stag; 864 __le16 pv_flags; /* same flags as add_pv */ 865#define I40E_AQC_GET_PV_PV_TYPE 0x1 866#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 867#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 868 u8 reserved[8]; 869 __le16 default_port_seid; 870}; 871 872I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 873 874/* Add VEB (direct 0x0230) */ 875struct i40e_aqc_add_veb { 876 __le16 uplink_seid; 877 __le16 downlink_seid; 878 __le16 veb_flags; 879#define I40E_AQC_ADD_VEB_FLOATING 0x1 880#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 881#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 882 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 883#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 884#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 885#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 886 u8 enable_tcs; 887 u8 reserved[9]; 888}; 889 890I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 891 892struct i40e_aqc_add_veb_completion { 893 u8 reserved[6]; 894 __le16 switch_seid; 895 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 896 __le16 veb_seid; 897#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 898#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 899#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 900#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 901 __le16 statistic_index; 902 __le16 vebs_used; 903 __le16 vebs_free; 904}; 905 906I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 907 908/* Get VEB Parameters (direct 0x0232) 909 * uses i40e_aqc_switch_seid for the descriptor 910 */ 911struct i40e_aqc_get_veb_parameters_completion { 912 __le16 seid; 913 __le16 switch_id; 914 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 915 __le16 statistic_index; 916 __le16 vebs_used; 917 __le16 vebs_free; 918 u8 reserved[4]; 919}; 920 921I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 922 923/* Delete Element (direct 0x0243) 924 * uses the generic i40e_aqc_switch_seid 925 */ 926 927/* Add MAC-VLAN (indirect 0x0250) */ 928 929/* used for the command for most vlan commands */ 930struct i40e_aqc_macvlan { 931 __le16 num_addresses; 932 __le16 seid[3]; 933#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 934#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 935 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 936#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 937 __le32 addr_high; 938 __le32 addr_low; 939}; 940 941I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 942 943/* indirect data for command and response */ 944struct i40e_aqc_add_macvlan_element_data { 945 u8 mac_addr[6]; 946 __le16 vlan_tag; 947 __le16 flags; 948#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 949#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 950#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 951#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 952 __le16 queue_number; 953#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 954#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 955 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 956 /* response section */ 957 u8 match_method; 958#define I40E_AQC_MM_PERFECT_MATCH 0x01 959#define I40E_AQC_MM_HASH_MATCH 0x02 960#define I40E_AQC_MM_ERR_NO_RES 0xFF 961 u8 reserved1[3]; 962}; 963 964struct i40e_aqc_add_remove_macvlan_completion { 965 __le16 perfect_mac_used; 966 __le16 perfect_mac_free; 967 __le16 unicast_hash_free; 968 __le16 multicast_hash_free; 969 __le32 addr_high; 970 __le32 addr_low; 971}; 972 973I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 974 975/* Remove MAC-VLAN (indirect 0x0251) 976 * uses i40e_aqc_macvlan for the descriptor 977 * data points to an array of num_addresses of elements 978 */ 979 980struct i40e_aqc_remove_macvlan_element_data { 981 u8 mac_addr[6]; 982 __le16 vlan_tag; 983 u8 flags; 984#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 985#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 986#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 987#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 988 u8 reserved[3]; 989 /* reply section */ 990 u8 error_code; 991#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 992#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 993 u8 reply_reserved[3]; 994}; 995 996/* Add VLAN (indirect 0x0252) 997 * Remove VLAN (indirect 0x0253) 998 * use the generic i40e_aqc_macvlan for the command 999 */ 1000struct i40e_aqc_add_remove_vlan_element_data { 1001 __le16 vlan_tag; 1002 u8 vlan_flags; 1003/* flags for add VLAN */ 1004#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1005#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1006#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \ 1007 I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1008#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1009#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1010#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1011#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1012#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1013#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1014#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1015#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1016#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1017/* flags for remove VLAN */ 1018#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1019 u8 reserved; 1020 u8 result; 1021/* flags for add VLAN */ 1022#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1023#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1024#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1025/* flags for remove VLAN */ 1026#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1027#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1028 u8 reserved1[3]; 1029}; 1030 1031struct i40e_aqc_add_remove_vlan_completion { 1032 u8 reserved[4]; 1033 __le16 vlans_used; 1034 __le16 vlans_free; 1035 __le32 addr_high; 1036 __le32 addr_low; 1037}; 1038 1039/* Set VSI Promiscuous Modes (direct 0x0254) */ 1040struct i40e_aqc_set_vsi_promiscuous_modes { 1041 __le16 promiscuous_flags; 1042 __le16 valid_flags; 1043/* flags used for both fields above */ 1044#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1045#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1046#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1047#define I40E_AQC_SET_VSI_DEFAULT 0x08 1048#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1049 __le16 seid; 1050#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1051 __le16 vlan_tag; 1052#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1053 u8 reserved[8]; 1054}; 1055 1056I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1057 1058/* Add S/E-tag command (direct 0x0255) 1059 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1060 */ 1061struct i40e_aqc_add_tag { 1062 __le16 flags; 1063#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1064 __le16 seid; 1065#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1066#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1067 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1068 __le16 tag; 1069 __le16 queue_number; 1070 u8 reserved[8]; 1071}; 1072 1073I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1074 1075struct i40e_aqc_add_remove_tag_completion { 1076 u8 reserved[12]; 1077 __le16 tags_used; 1078 __le16 tags_free; 1079}; 1080 1081I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1082 1083/* Remove S/E-tag command (direct 0x0256) 1084 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1085 */ 1086struct i40e_aqc_remove_tag { 1087 __le16 seid; 1088#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1089#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1090 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1091 __le16 tag; 1092 u8 reserved[12]; 1093}; 1094 1095/* Add multicast E-Tag (direct 0x0257) 1096 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1097 * and no external data 1098 */ 1099struct i40e_aqc_add_remove_mcast_etag { 1100 __le16 pv_seid; 1101 __le16 etag; 1102 u8 num_unicast_etags; 1103 u8 reserved[3]; 1104 __le32 addr_high; /* address of array of 2-byte s-tags */ 1105 __le32 addr_low; 1106}; 1107 1108I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1109 1110struct i40e_aqc_add_remove_mcast_etag_completion { 1111 u8 reserved[4]; 1112 __le16 mcast_etags_used; 1113 __le16 mcast_etags_free; 1114 __le32 addr_high; 1115 __le32 addr_low; 1116 1117}; 1118 1119I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1120 1121/* Update S/E-Tag (direct 0x0259) */ 1122struct i40e_aqc_update_tag { 1123 __le16 seid; 1124#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1125#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1126 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1127 __le16 old_tag; 1128 __le16 new_tag; 1129 u8 reserved[10]; 1130}; 1131 1132I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1133 1134struct i40e_aqc_update_tag_completion { 1135 u8 reserved[12]; 1136 __le16 tags_used; 1137 __le16 tags_free; 1138}; 1139 1140I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1141 1142/* Add Control Packet filter (direct 0x025A) 1143 * Remove Control Packet filter (direct 0x025B) 1144 * uses the i40e_aqc_add_oveb_cloud, 1145 * and the generic direct completion structure 1146 */ 1147struct i40e_aqc_add_remove_control_packet_filter { 1148 u8 mac[6]; 1149 __le16 etype; 1150 __le16 flags; 1151#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1152#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1153#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1154#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1155#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1156 __le16 seid; 1157#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1158#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1159 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1160 __le16 queue; 1161 u8 reserved[2]; 1162}; 1163 1164I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1165 1166struct i40e_aqc_add_remove_control_packet_filter_completion { 1167 __le16 mac_etype_used; 1168 __le16 etype_used; 1169 __le16 mac_etype_free; 1170 __le16 etype_free; 1171 u8 reserved[8]; 1172}; 1173 1174I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1175 1176/* Add Cloud filters (indirect 0x025C) 1177 * Remove Cloud filters (indirect 0x025D) 1178 * uses the i40e_aqc_add_remove_cloud_filters, 1179 * and the generic indirect completion structure 1180 */ 1181struct i40e_aqc_add_remove_cloud_filters { 1182 u8 num_filters; 1183 u8 reserved; 1184 __le16 seid; 1185#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1186#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1187 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1188 u8 reserved2[4]; 1189 __le32 addr_high; 1190 __le32 addr_low; 1191}; 1192 1193I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1194 1195struct i40e_aqc_add_remove_cloud_filters_element_data { 1196 u8 outer_mac[6]; 1197 u8 inner_mac[6]; 1198 __le16 inner_vlan; 1199 union { 1200 struct { 1201 u8 reserved[12]; 1202 u8 data[4]; 1203 } v4; 1204 struct { 1205 u8 data[16]; 1206 } v6; 1207 } ipaddr; 1208 __le16 flags; 1209#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1210#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1211 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1212/* 0x0000 reserved */ 1213#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1214/* 0x0002 reserved */ 1215#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1216#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1217/* 0x0005 reserved */ 1218#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1219/* 0x0007 reserved */ 1220/* 0x0008 reserved */ 1221#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1222#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1223#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1224#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1225 1226#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1227#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1228#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1229#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1230#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1231 1232#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1233#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1234#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1235#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1236#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1237#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1238 1239 __le32 tenant_id; 1240 u8 reserved[4]; 1241 __le16 queue_number; 1242#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1243#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \ 1244 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1245 u8 reserved2[14]; 1246 /* response section */ 1247 u8 allocation_result; 1248#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1249#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1250 u8 response_reserved[7]; 1251}; 1252 1253struct i40e_aqc_remove_cloud_filters_completion { 1254 __le16 perfect_ovlan_used; 1255 __le16 perfect_ovlan_free; 1256 __le16 vlan_used; 1257 __le16 vlan_free; 1258 __le32 addr_high; 1259 __le32 addr_low; 1260}; 1261 1262I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1263 1264/* Add Mirror Rule (indirect or direct 0x0260) 1265 * Delete Mirror Rule (indirect or direct 0x0261) 1266 * note: some rule types (4,5) do not use an external buffer. 1267 * take care to set the flags correctly. 1268 */ 1269struct i40e_aqc_add_delete_mirror_rule { 1270 __le16 seid; 1271 __le16 rule_type; 1272#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1273#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1274 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1275#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1276#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1277#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1278#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1279#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1280 __le16 num_entries; 1281 __le16 destination; /* VSI for add, rule id for delete */ 1282 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1283 __le32 addr_low; 1284}; 1285 1286I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1287 1288struct i40e_aqc_add_delete_mirror_rule_completion { 1289 u8 reserved[2]; 1290 __le16 rule_id; /* only used on add */ 1291 __le16 mirror_rules_used; 1292 __le16 mirror_rules_free; 1293 __le32 addr_high; 1294 __le32 addr_low; 1295}; 1296 1297I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1298 1299/* DCB 0x03xx*/ 1300 1301/* PFC Ignore (direct 0x0301) 1302 * the command and response use the same descriptor structure 1303 */ 1304struct i40e_aqc_pfc_ignore { 1305 u8 tc_bitmap; 1306 u8 command_flags; /* unused on response */ 1307#define I40E_AQC_PFC_IGNORE_SET 0x80 1308#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1309 u8 reserved[14]; 1310}; 1311 1312I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1313 1314/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1315 * with no parameters 1316 */ 1317 1318/* TX scheduler 0x04xx */ 1319 1320/* Almost all the indirect commands use 1321 * this generic struct to pass the SEID in param0 1322 */ 1323struct i40e_aqc_tx_sched_ind { 1324 __le16 vsi_seid; 1325 u8 reserved[6]; 1326 __le32 addr_high; 1327 __le32 addr_low; 1328}; 1329 1330I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1331 1332/* Several commands respond with a set of queue set handles */ 1333struct i40e_aqc_qs_handles_resp { 1334 __le16 qs_handles[8]; 1335}; 1336 1337/* Configure VSI BW limits (direct 0x0400) */ 1338struct i40e_aqc_configure_vsi_bw_limit { 1339 __le16 vsi_seid; 1340 u8 reserved[2]; 1341 __le16 credit; 1342 u8 reserved1[2]; 1343 u8 max_credit; /* 0-3, limit = 2^max */ 1344 u8 reserved2[7]; 1345}; 1346 1347I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1348 1349/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1350 * responds with i40e_aqc_qs_handles_resp 1351 */ 1352struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1353 u8 tc_valid_bits; 1354 u8 reserved[15]; 1355 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1356 1357 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1358 __le16 tc_bw_max[2]; 1359 u8 reserved1[28]; 1360}; 1361 1362/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1363 * responds with i40e_aqc_qs_handles_resp 1364 */ 1365struct i40e_aqc_configure_vsi_tc_bw_data { 1366 u8 tc_valid_bits; 1367 u8 reserved[3]; 1368 u8 tc_bw_credits[8]; 1369 u8 reserved1[4]; 1370 __le16 qs_handles[8]; 1371}; 1372 1373/* Query vsi bw configuration (indirect 0x0408) */ 1374struct i40e_aqc_query_vsi_bw_config_resp { 1375 u8 tc_valid_bits; 1376 u8 tc_suspended_bits; 1377 u8 reserved[14]; 1378 __le16 qs_handles[8]; 1379 u8 reserved1[4]; 1380 __le16 port_bw_limit; 1381 u8 reserved2[2]; 1382 u8 max_bw; /* 0-3, limit = 2^max */ 1383 u8 reserved3[23]; 1384}; 1385 1386/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1387struct i40e_aqc_query_vsi_ets_sla_config_resp { 1388 u8 tc_valid_bits; 1389 u8 reserved[3]; 1390 u8 share_credits[8]; 1391 __le16 credits[8]; 1392 1393 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1394 __le16 tc_bw_max[2]; 1395}; 1396 1397/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1398struct i40e_aqc_configure_switching_comp_bw_limit { 1399 __le16 seid; 1400 u8 reserved[2]; 1401 __le16 credit; 1402 u8 reserved1[2]; 1403 u8 max_bw; /* 0-3, limit = 2^max */ 1404 u8 reserved2[7]; 1405}; 1406 1407I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1408 1409/* Enable Physical Port ETS (indirect 0x0413) 1410 * Modify Physical Port ETS (indirect 0x0414) 1411 * Disable Physical Port ETS (indirect 0x0415) 1412 */ 1413struct i40e_aqc_configure_switching_comp_ets_data { 1414 u8 reserved[4]; 1415 u8 tc_valid_bits; 1416 u8 seepage; 1417#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1418 u8 tc_strict_priority_flags; 1419 u8 reserved1[17]; 1420 u8 tc_bw_share_credits[8]; 1421 u8 reserved2[96]; 1422}; 1423 1424/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1425struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1426 u8 tc_valid_bits; 1427 u8 reserved[15]; 1428 __le16 tc_bw_credit[8]; 1429 1430 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1431 __le16 tc_bw_max[2]; 1432 u8 reserved1[28]; 1433}; 1434 1435/* Configure Switching Component Bandwidth Allocation per Tc 1436 * (indirect 0x0417) 1437 */ 1438struct i40e_aqc_configure_switching_comp_bw_config_data { 1439 u8 tc_valid_bits; 1440 u8 reserved[2]; 1441 u8 absolute_credits; /* bool */ 1442 u8 tc_bw_share_credits[8]; 1443 u8 reserved1[20]; 1444}; 1445 1446/* Query Switching Component Configuration (indirect 0x0418) */ 1447struct i40e_aqc_query_switching_comp_ets_config_resp { 1448 u8 tc_valid_bits; 1449 u8 reserved[35]; 1450 __le16 port_bw_limit; 1451 u8 reserved1[2]; 1452 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1453 u8 reserved2[23]; 1454}; 1455 1456/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1457struct i40e_aqc_query_port_ets_config_resp { 1458 u8 reserved[4]; 1459 u8 tc_valid_bits; 1460 u8 reserved1; 1461 u8 tc_strict_priority_bits; 1462 u8 reserved2; 1463 u8 tc_bw_share_credits[8]; 1464 __le16 tc_bw_limits[8]; 1465 1466 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1467 __le16 tc_bw_max[2]; 1468 u8 reserved3[32]; 1469}; 1470 1471/* Query Switching Component Bandwidth Allocation per Traffic Type 1472 * (indirect 0x041A) 1473 */ 1474struct i40e_aqc_query_switching_comp_bw_config_resp { 1475 u8 tc_valid_bits; 1476 u8 reserved[2]; 1477 u8 absolute_credits_enable; /* bool */ 1478 u8 tc_bw_share_credits[8]; 1479 __le16 tc_bw_limits[8]; 1480 1481 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1482 __le16 tc_bw_max[2]; 1483}; 1484 1485/* Suspend/resume port TX traffic 1486 * (direct 0x041B and 0x041C) uses the generic SEID struct 1487 */ 1488 1489/* Configure partition BW 1490 * (indirect 0x041D) 1491 */ 1492struct i40e_aqc_configure_partition_bw_data { 1493 __le16 pf_valid_bits; 1494 u8 min_bw[16]; /* guaranteed bandwidth */ 1495 u8 max_bw[16]; /* bandwidth limit */ 1496}; 1497 1498/* Get and set the active HMC resource profile and status. 1499 * (direct 0x0500) and (direct 0x0501) 1500 */ 1501struct i40e_aq_get_set_hmc_resource_profile { 1502 u8 pm_profile; 1503 u8 pe_vf_enabled; 1504 u8 reserved[14]; 1505}; 1506 1507I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1508 1509enum i40e_aq_hmc_profile { 1510 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1511 I40E_HMC_PROFILE_DEFAULT = 1, 1512 I40E_HMC_PROFILE_FAVOR_VF = 2, 1513 I40E_HMC_PROFILE_EQUAL = 3, 1514}; 1515 1516#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1517#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1518 1519/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1520 1521/* set in param0 for get phy abilities to report qualified modules */ 1522#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1523#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1524 1525enum i40e_aq_phy_type { 1526 I40E_PHY_TYPE_SGMII = 0x0, 1527 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1528 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1529 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1530 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1531 I40E_PHY_TYPE_XAUI = 0x5, 1532 I40E_PHY_TYPE_XFI = 0x6, 1533 I40E_PHY_TYPE_SFI = 0x7, 1534 I40E_PHY_TYPE_XLAUI = 0x8, 1535 I40E_PHY_TYPE_XLPPI = 0x9, 1536 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1537 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1538 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1539 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1540 I40E_PHY_TYPE_100BASE_TX = 0x11, 1541 I40E_PHY_TYPE_1000BASE_T = 0x12, 1542 I40E_PHY_TYPE_10GBASE_T = 0x13, 1543 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1544 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1545 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1546 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1547 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1548 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1549 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1550 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1551 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1552 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1553 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1554 I40E_PHY_TYPE_MAX 1555}; 1556 1557#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1558#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1559#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1560#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1561#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1562 1563enum i40e_aq_link_speed { 1564 I40E_LINK_SPEED_UNKNOWN = 0, 1565 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1566 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1567 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1568 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1569 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1570}; 1571 1572struct i40e_aqc_module_desc { 1573 u8 oui[3]; 1574 u8 reserved1; 1575 u8 part_number[16]; 1576 u8 revision[4]; 1577 u8 reserved2[8]; 1578}; 1579 1580struct i40e_aq_get_phy_abilities_resp { 1581 __le32 phy_type; /* bitmap using the above enum for offsets */ 1582 u8 link_speed; /* bitmap using the above enum bit patterns */ 1583 u8 abilities; 1584#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1585#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1586#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1587#define I40E_AQ_PHY_LINK_ENABLED 0x08 1588#define I40E_AQ_PHY_AN_ENABLED 0x10 1589#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1590 __le16 eee_capability; 1591#define I40E_AQ_EEE_100BASE_TX 0x0002 1592#define I40E_AQ_EEE_1000BASE_T 0x0004 1593#define I40E_AQ_EEE_10GBASE_T 0x0008 1594#define I40E_AQ_EEE_1000BASE_KX 0x0010 1595#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1596#define I40E_AQ_EEE_10GBASE_KR 0x0040 1597 __le32 eeer_val; 1598 u8 d3_lpan; 1599#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1600 u8 reserved[3]; 1601 u8 phy_id[4]; 1602 u8 module_type[3]; 1603 u8 qualified_module_count; 1604#define I40E_AQ_PHY_MAX_QMS 16 1605 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1606}; 1607 1608/* Set PHY Config (direct 0x0601) */ 1609struct i40e_aq_set_phy_config { /* same bits as above in all */ 1610 __le32 phy_type; 1611 u8 link_speed; 1612 u8 abilities; 1613/* bits 0-2 use the values from get_phy_abilities_resp */ 1614#define I40E_AQ_PHY_ENABLE_LINK 0x08 1615#define I40E_AQ_PHY_ENABLE_AN 0x10 1616#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1617 __le16 eee_capability; 1618 __le32 eeer; 1619 u8 low_power_ctrl; 1620 u8 reserved[3]; 1621}; 1622 1623I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1624 1625/* Set MAC Config command data structure (direct 0x0603) */ 1626struct i40e_aq_set_mac_config { 1627 __le16 max_frame_size; 1628 u8 params; 1629#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1630#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1631#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1632#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1633#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1634#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1635#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1636#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1637#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1638#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1639#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1640#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1641#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1642#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1643 u8 tx_timer_priority; /* bitmap */ 1644 __le16 tx_timer_value; 1645 __le16 fc_refresh_threshold; 1646 u8 reserved[8]; 1647}; 1648 1649I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1650 1651/* Restart Auto-Negotiation (direct 0x605) */ 1652struct i40e_aqc_set_link_restart_an { 1653 u8 command; 1654#define I40E_AQ_PHY_RESTART_AN 0x02 1655#define I40E_AQ_PHY_LINK_ENABLE 0x04 1656 u8 reserved[15]; 1657}; 1658 1659I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1660 1661/* Get Link Status cmd & response data structure (direct 0x0607) */ 1662struct i40e_aqc_get_link_status { 1663 __le16 command_flags; /* only field set on command */ 1664#define I40E_AQ_LSE_MASK 0x3 1665#define I40E_AQ_LSE_NOP 0x0 1666#define I40E_AQ_LSE_DISABLE 0x2 1667#define I40E_AQ_LSE_ENABLE 0x3 1668/* only response uses this flag */ 1669#define I40E_AQ_LSE_IS_ENABLED 0x1 1670 u8 phy_type; /* i40e_aq_phy_type */ 1671 u8 link_speed; /* i40e_aq_link_speed */ 1672 u8 link_info; 1673#define I40E_AQ_LINK_UP 0x01 1674#define I40E_AQ_LINK_FAULT 0x02 1675#define I40E_AQ_LINK_FAULT_TX 0x04 1676#define I40E_AQ_LINK_FAULT_RX 0x08 1677#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1678#define I40E_AQ_MEDIA_AVAILABLE 0x40 1679#define I40E_AQ_SIGNAL_DETECT 0x80 1680 u8 an_info; 1681#define I40E_AQ_AN_COMPLETED 0x01 1682#define I40E_AQ_LP_AN_ABILITY 0x02 1683#define I40E_AQ_PD_FAULT 0x04 1684#define I40E_AQ_FEC_EN 0x08 1685#define I40E_AQ_PHY_LOW_POWER 0x10 1686#define I40E_AQ_LINK_PAUSE_TX 0x20 1687#define I40E_AQ_LINK_PAUSE_RX 0x40 1688#define I40E_AQ_QUALIFIED_MODULE 0x80 1689 u8 ext_info; 1690#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1691#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1692#define I40E_AQ_LINK_TX_SHIFT 0x02 1693#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1694#define I40E_AQ_LINK_TX_ACTIVE 0x00 1695#define I40E_AQ_LINK_TX_DRAINED 0x01 1696#define I40E_AQ_LINK_TX_FLUSHED 0x03 1697#define I40E_AQ_LINK_FORCED_40G 0x10 1698 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1699 __le16 max_frame_size; 1700 u8 config; 1701#define I40E_AQ_CONFIG_CRC_ENA 0x04 1702#define I40E_AQ_CONFIG_PACING_MASK 0x78 1703 u8 reserved[5]; 1704}; 1705 1706I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1707 1708/* Set event mask command (direct 0x613) */ 1709struct i40e_aqc_set_phy_int_mask { 1710 u8 reserved[8]; 1711 __le16 event_mask; 1712#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1713#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1714#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1715#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1716#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1717#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1718#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1719#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1720#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1721 u8 reserved1[6]; 1722}; 1723 1724I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1725 1726/* Get Local AN advt register (direct 0x0614) 1727 * Set Local AN advt register (direct 0x0615) 1728 * Get Link Partner AN advt register (direct 0x0616) 1729 */ 1730struct i40e_aqc_an_advt_reg { 1731 __le32 local_an_reg0; 1732 __le16 local_an_reg1; 1733 u8 reserved[10]; 1734}; 1735 1736I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1737 1738/* Set Loopback mode (0x0618) */ 1739struct i40e_aqc_set_lb_mode { 1740 __le16 lb_mode; 1741#define I40E_AQ_LB_PHY_LOCAL 0x01 1742#define I40E_AQ_LB_PHY_REMOTE 0x02 1743#define I40E_AQ_LB_MAC_LOCAL 0x04 1744 u8 reserved[14]; 1745}; 1746 1747I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1748 1749/* Set PHY Debug command (0x0622) */ 1750struct i40e_aqc_set_phy_debug { 1751 u8 command_flags; 1752#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1753#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1754#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1755 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1756#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1757#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1758#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1759#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1760 u8 reserved[15]; 1761}; 1762 1763I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1764 1765enum i40e_aq_phy_reg_type { 1766 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1767 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1768 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1769}; 1770 1771/* NVM Read command (indirect 0x0701) 1772 * NVM Erase commands (direct 0x0702) 1773 * NVM Update commands (indirect 0x0703) 1774 */ 1775struct i40e_aqc_nvm_update { 1776 u8 command_flags; 1777#define I40E_AQ_NVM_LAST_CMD 0x01 1778#define I40E_AQ_NVM_FLASH_ONLY 0x80 1779 u8 module_pointer; 1780 __le16 length; 1781 __le32 offset; 1782 __le32 addr_high; 1783 __le32 addr_low; 1784}; 1785 1786I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1787 1788/* NVM Config Read (indirect 0x0704) */ 1789struct i40e_aqc_nvm_config_read { 1790 __le16 cmd_flags; 1791#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1792#define ANVM_READ_SINGLE_FEATURE 0 1793#define ANVM_READ_MULTIPLE_FEATURES 1 1794 __le16 element_count; 1795 __le16 element_id; /* Feature/field ID */ 1796 u8 reserved[2]; 1797 __le32 address_high; 1798 __le32 address_low; 1799}; 1800 1801I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1802 1803/* NVM Config Write (indirect 0x0705) */ 1804struct i40e_aqc_nvm_config_write { 1805 __le16 cmd_flags; 1806 __le16 element_count; 1807 u8 reserved[4]; 1808 __le32 address_high; 1809 __le32 address_low; 1810}; 1811 1812I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1813 1814struct i40e_aqc_nvm_config_data_feature { 1815 __le16 feature_id; 1816 __le16 instance_id; 1817 __le16 feature_options; 1818 __le16 feature_selection; 1819}; 1820 1821struct i40e_aqc_nvm_config_data_immediate_field { 1822#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2 1823 __le16 field_id; 1824 __le16 instance_id; 1825 __le16 field_options; 1826 __le16 field_value; 1827}; 1828 1829/* Send to PF command (indirect 0x0801) id is only used by PF 1830 * Send to VF command (indirect 0x0802) id is only used by PF 1831 * Send to Peer PF command (indirect 0x0803) 1832 */ 1833struct i40e_aqc_pf_vf_message { 1834 __le32 id; 1835 u8 reserved[4]; 1836 __le32 addr_high; 1837 __le32 addr_low; 1838}; 1839 1840I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1841 1842/* Alternate structure */ 1843 1844/* Direct write (direct 0x0900) 1845 * Direct read (direct 0x0902) 1846 */ 1847struct i40e_aqc_alternate_write { 1848 __le32 address0; 1849 __le32 data0; 1850 __le32 address1; 1851 __le32 data1; 1852}; 1853 1854I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1855 1856/* Indirect write (indirect 0x0901) 1857 * Indirect read (indirect 0x0903) 1858 */ 1859 1860struct i40e_aqc_alternate_ind_write { 1861 __le32 address; 1862 __le32 length; 1863 __le32 addr_high; 1864 __le32 addr_low; 1865}; 1866 1867I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1868 1869/* Done alternate write (direct 0x0904) 1870 * uses i40e_aq_desc 1871 */ 1872struct i40e_aqc_alternate_write_done { 1873 __le16 cmd_flags; 1874#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1875#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1876#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1877#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1878 u8 reserved[14]; 1879}; 1880 1881I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1882 1883/* Set OEM mode (direct 0x0905) */ 1884struct i40e_aqc_alternate_set_mode { 1885 __le32 mode; 1886#define I40E_AQ_ALTERNATE_MODE_NONE 0 1887#define I40E_AQ_ALTERNATE_MODE_OEM 1 1888 u8 reserved[12]; 1889}; 1890 1891I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1892 1893/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1894 1895/* async events 0x10xx */ 1896 1897/* Lan Queue Overflow Event (direct, 0x1001) */ 1898struct i40e_aqc_lan_overflow { 1899 __le32 prtdcb_rupto; 1900 __le32 otx_ctl; 1901 u8 reserved[8]; 1902}; 1903 1904I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1905 1906/* Get LLDP MIB (indirect 0x0A00) */ 1907struct i40e_aqc_lldp_get_mib { 1908 u8 type; 1909 u8 reserved1; 1910#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1911#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1912#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1913#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1914#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1915#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1916#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1917#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1918#define I40E_AQ_LLDP_TX_SHIFT 0x4 1919#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1920/* TX pause flags use I40E_AQ_LINK_TX_* above */ 1921 __le16 local_len; 1922 __le16 remote_len; 1923 u8 reserved2[2]; 1924 __le32 addr_high; 1925 __le32 addr_low; 1926}; 1927 1928I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1929 1930/* Configure LLDP MIB Change Event (direct 0x0A01) 1931 * also used for the event (with type in the command field) 1932 */ 1933struct i40e_aqc_lldp_update_mib { 1934 u8 command; 1935#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1936#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1937 u8 reserved[7]; 1938 __le32 addr_high; 1939 __le32 addr_low; 1940}; 1941 1942I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 1943 1944/* Add LLDP TLV (indirect 0x0A02) 1945 * Delete LLDP TLV (indirect 0x0A04) 1946 */ 1947struct i40e_aqc_lldp_add_tlv { 1948 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1949 u8 reserved1[1]; 1950 __le16 len; 1951 u8 reserved2[4]; 1952 __le32 addr_high; 1953 __le32 addr_low; 1954}; 1955 1956I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 1957 1958/* Update LLDP TLV (indirect 0x0A03) */ 1959struct i40e_aqc_lldp_update_tlv { 1960 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1961 u8 reserved; 1962 __le16 old_len; 1963 __le16 new_offset; 1964 __le16 new_len; 1965 __le32 addr_high; 1966 __le32 addr_low; 1967}; 1968 1969I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 1970 1971/* Stop LLDP (direct 0x0A05) */ 1972struct i40e_aqc_lldp_stop { 1973 u8 command; 1974#define I40E_AQ_LLDP_AGENT_STOP 0x0 1975#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 1976 u8 reserved[15]; 1977}; 1978 1979I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 1980 1981/* Start LLDP (direct 0x0A06) */ 1982 1983struct i40e_aqc_lldp_start { 1984 u8 command; 1985#define I40E_AQ_LLDP_AGENT_START 0x1 1986 u8 reserved[15]; 1987}; 1988 1989I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 1990 1991/* Apply MIB changes (0x0A07) 1992 * uses the generic struc as it contains no data 1993 */ 1994 1995/* Add Udp Tunnel command and completion (direct 0x0B00) */ 1996struct i40e_aqc_add_udp_tunnel { 1997 __le16 udp_port; 1998 u8 reserved0[3]; 1999 u8 protocol_type; 2000#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2001#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2002#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2003 u8 reserved1[10]; 2004}; 2005 2006I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2007 2008struct i40e_aqc_add_udp_tunnel_completion { 2009 __le16 udp_port; 2010 u8 filter_entry_index; 2011 u8 multiple_pfs; 2012#define I40E_AQC_SINGLE_PF 0x0 2013#define I40E_AQC_MULTIPLE_PFS 0x1 2014 u8 total_filters; 2015 u8 reserved[11]; 2016}; 2017 2018I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2019 2020/* remove UDP Tunnel command (0x0B01) */ 2021struct i40e_aqc_remove_udp_tunnel { 2022 u8 reserved[2]; 2023 u8 index; /* 0 to 15 */ 2024 u8 reserved2[13]; 2025}; 2026 2027I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2028 2029struct i40e_aqc_del_udp_tunnel_completion { 2030 __le16 udp_port; 2031 u8 index; /* 0 to 15 */ 2032 u8 multiple_pfs; 2033 u8 total_filters_used; 2034 u8 reserved1[11]; 2035}; 2036 2037I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2038 2039/* tunnel key structure 0x0B10 */ 2040 2041struct i40e_aqc_tunnel_key_structure { 2042 u8 key1_off; 2043 u8 key2_off; 2044 u8 key1_len; /* 0 to 15 */ 2045 u8 key2_len; /* 0 to 15 */ 2046 u8 flags; 2047#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2048/* response flags */ 2049#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2050#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2051#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2052 u8 network_key_index; 2053#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2054#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2055#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2056#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2057 u8 reserved[10]; 2058}; 2059 2060I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2061 2062/* OEM mode commands (direct 0xFE0x) */ 2063struct i40e_aqc_oem_param_change { 2064 __le32 param_type; 2065#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2066#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2067#define I40E_AQ_OEM_PARAM_MAC 2 2068 __le32 param_value1; 2069 u8 param_value2[8]; 2070}; 2071 2072I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2073 2074struct i40e_aqc_oem_state_change { 2075 __le32 state; 2076#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2077#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2078 u8 reserved[12]; 2079}; 2080 2081I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2082 2083/* debug commands */ 2084 2085/* get device id (0xFF00) uses the generic structure */ 2086 2087/* set test more (0xFF01, internal) */ 2088 2089struct i40e_acq_set_test_mode { 2090 u8 mode; 2091#define I40E_AQ_TEST_PARTIAL 0 2092#define I40E_AQ_TEST_FULL 1 2093#define I40E_AQ_TEST_NVM 2 2094 u8 reserved[3]; 2095 u8 command; 2096#define I40E_AQ_TEST_OPEN 0 2097#define I40E_AQ_TEST_CLOSE 1 2098#define I40E_AQ_TEST_INC 2 2099 u8 reserved2[3]; 2100 __le32 address_high; 2101 __le32 address_low; 2102}; 2103 2104I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2105 2106/* Debug Read Register command (0xFF03) 2107 * Debug Write Register command (0xFF04) 2108 */ 2109struct i40e_aqc_debug_reg_read_write { 2110 __le32 reserved; 2111 __le32 address; 2112 __le32 value_high; 2113 __le32 value_low; 2114}; 2115 2116I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2117 2118/* Scatter/gather Reg Read (indirect 0xFF05) 2119 * Scatter/gather Reg Write (indirect 0xFF06) 2120 */ 2121 2122/* i40e_aq_desc is used for the command */ 2123struct i40e_aqc_debug_reg_sg_element_data { 2124 __le32 address; 2125 __le32 value; 2126}; 2127 2128/* Debug Modify register (direct 0xFF07) */ 2129struct i40e_aqc_debug_modify_reg { 2130 __le32 address; 2131 __le32 value; 2132 __le32 clear_mask; 2133 __le32 set_mask; 2134}; 2135 2136I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2137 2138/* dump internal data (0xFF08, indirect) */ 2139 2140#define I40E_AQ_CLUSTER_ID_AUX 0 2141#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2142#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2143#define I40E_AQ_CLUSTER_ID_HMC 3 2144#define I40E_AQ_CLUSTER_ID_MAC0 4 2145#define I40E_AQ_CLUSTER_ID_MAC1 5 2146#define I40E_AQ_CLUSTER_ID_MAC2 6 2147#define I40E_AQ_CLUSTER_ID_MAC3 7 2148#define I40E_AQ_CLUSTER_ID_DCB 8 2149#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2150#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2151#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2152 2153struct i40e_aqc_debug_dump_internals { 2154 u8 cluster_id; 2155 u8 table_id; 2156 __le16 data_size; 2157 __le32 idx; 2158 __le32 address_high; 2159 __le32 address_low; 2160}; 2161 2162I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2163 2164struct i40e_aqc_debug_modify_internals { 2165 u8 cluster_id; 2166 u8 cluster_specific_params[7]; 2167 __le32 address_high; 2168 __le32 address_low; 2169}; 2170 2171I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2172 2173#endif 2174