1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_ADMINQ_CMD_H_ 28#define _I40E_ADMINQ_CMD_H_ 29 30/* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36#define I40E_FW_API_VERSION_MAJOR 0x0001 37#define I40E_FW_API_VERSION_MINOR 0x0002 38#define I40E_FW_API_VERSION_A0_MINOR 0x0000 39 40struct i40e_aq_desc { 41 __le16 flags; 42 __le16 opcode; 43 __le16 datalen; 44 __le16 retval; 45 __le32 cookie_high; 46 __le32 cookie_low; 47 union { 48 struct { 49 __le32 param0; 50 __le32 param1; 51 __le32 param2; 52 __le32 param3; 53 } internal; 54 struct { 55 __le32 param0; 56 __le32 param1; 57 __le32 addr_high; 58 __le32 addr_low; 59 } external; 60 u8 raw[16]; 61 } params; 62}; 63 64/* Flags sub-structure 65 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 66 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 67 */ 68 69/* command flags and offsets*/ 70#define I40E_AQ_FLAG_DD_SHIFT 0 71#define I40E_AQ_FLAG_CMP_SHIFT 1 72#define I40E_AQ_FLAG_ERR_SHIFT 2 73#define I40E_AQ_FLAG_VFE_SHIFT 3 74#define I40E_AQ_FLAG_LB_SHIFT 9 75#define I40E_AQ_FLAG_RD_SHIFT 10 76#define I40E_AQ_FLAG_VFC_SHIFT 11 77#define I40E_AQ_FLAG_BUF_SHIFT 12 78#define I40E_AQ_FLAG_SI_SHIFT 13 79#define I40E_AQ_FLAG_EI_SHIFT 14 80#define I40E_AQ_FLAG_FE_SHIFT 15 81 82#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 83#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 84#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 85#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 86#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 87#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 88#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 89#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 90#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 91#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 92#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 93 94/* error codes */ 95enum i40e_admin_queue_err { 96 I40E_AQ_RC_OK = 0, /* success */ 97 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 98 I40E_AQ_RC_ENOENT = 2, /* No such element */ 99 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 100 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 101 I40E_AQ_RC_EIO = 5, /* I/O error */ 102 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 103 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 104 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 105 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 106 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 107 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 108 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 109 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 110 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 111 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 112 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 113 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 114 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 115 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */ 116 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 117 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 118 I40E_AQ_RC_EFBIG = 22, /* File too large */ 119}; 120 121/* Admin Queue command opcodes */ 122enum i40e_admin_queue_opc { 123 /* aq commands */ 124 i40e_aqc_opc_get_version = 0x0001, 125 i40e_aqc_opc_driver_version = 0x0002, 126 i40e_aqc_opc_queue_shutdown = 0x0003, 127 i40e_aqc_opc_set_pf_context = 0x0004, 128 129 /* resource ownership */ 130 i40e_aqc_opc_request_resource = 0x0008, 131 i40e_aqc_opc_release_resource = 0x0009, 132 133 i40e_aqc_opc_list_func_capabilities = 0x000A, 134 i40e_aqc_opc_list_dev_capabilities = 0x000B, 135 136 i40e_aqc_opc_set_cppm_configuration = 0x0103, 137 i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 138 i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 139 140 /* LAA */ 141 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 142 i40e_aqc_opc_mac_address_read = 0x0107, 143 i40e_aqc_opc_mac_address_write = 0x0108, 144 145 /* PXE */ 146 i40e_aqc_opc_clear_pxe_mode = 0x0110, 147 148 /* internal switch commands */ 149 i40e_aqc_opc_get_switch_config = 0x0200, 150 i40e_aqc_opc_add_statistics = 0x0201, 151 i40e_aqc_opc_remove_statistics = 0x0202, 152 i40e_aqc_opc_set_port_parameters = 0x0203, 153 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 154 155 i40e_aqc_opc_add_vsi = 0x0210, 156 i40e_aqc_opc_update_vsi_parameters = 0x0211, 157 i40e_aqc_opc_get_vsi_parameters = 0x0212, 158 159 i40e_aqc_opc_add_pv = 0x0220, 160 i40e_aqc_opc_update_pv_parameters = 0x0221, 161 i40e_aqc_opc_get_pv_parameters = 0x0222, 162 163 i40e_aqc_opc_add_veb = 0x0230, 164 i40e_aqc_opc_update_veb_parameters = 0x0231, 165 i40e_aqc_opc_get_veb_parameters = 0x0232, 166 167 i40e_aqc_opc_delete_element = 0x0243, 168 169 i40e_aqc_opc_add_macvlan = 0x0250, 170 i40e_aqc_opc_remove_macvlan = 0x0251, 171 i40e_aqc_opc_add_vlan = 0x0252, 172 i40e_aqc_opc_remove_vlan = 0x0253, 173 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 174 i40e_aqc_opc_add_tag = 0x0255, 175 i40e_aqc_opc_remove_tag = 0x0256, 176 i40e_aqc_opc_add_multicast_etag = 0x0257, 177 i40e_aqc_opc_remove_multicast_etag = 0x0258, 178 i40e_aqc_opc_update_tag = 0x0259, 179 i40e_aqc_opc_add_control_packet_filter = 0x025A, 180 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 181 i40e_aqc_opc_add_cloud_filters = 0x025C, 182 i40e_aqc_opc_remove_cloud_filters = 0x025D, 183 184 i40e_aqc_opc_add_mirror_rule = 0x0260, 185 i40e_aqc_opc_delete_mirror_rule = 0x0261, 186 187 /* DCB commands */ 188 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 189 i40e_aqc_opc_dcb_updated = 0x0302, 190 191 /* TX scheduler */ 192 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 193 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 194 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 195 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 196 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 197 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 198 199 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 200 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 201 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 202 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 203 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 204 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 205 i40e_aqc_opc_query_port_ets_config = 0x0419, 206 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 207 i40e_aqc_opc_suspend_port_tx = 0x041B, 208 i40e_aqc_opc_resume_port_tx = 0x041C, 209 i40e_aqc_opc_configure_partition_bw = 0x041D, 210 211 /* hmc */ 212 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 213 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 214 215 /* phy commands*/ 216 i40e_aqc_opc_get_phy_abilities = 0x0600, 217 i40e_aqc_opc_set_phy_config = 0x0601, 218 i40e_aqc_opc_set_mac_config = 0x0603, 219 i40e_aqc_opc_set_link_restart_an = 0x0605, 220 i40e_aqc_opc_get_link_status = 0x0607, 221 i40e_aqc_opc_set_phy_int_mask = 0x0613, 222 i40e_aqc_opc_get_local_advt_reg = 0x0614, 223 i40e_aqc_opc_set_local_advt_reg = 0x0615, 224 i40e_aqc_opc_get_partner_advt = 0x0616, 225 i40e_aqc_opc_set_lb_modes = 0x0618, 226 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 227 i40e_aqc_opc_set_phy_debug = 0x0622, 228 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 229 230 /* NVM commands */ 231 i40e_aqc_opc_nvm_read = 0x0701, 232 i40e_aqc_opc_nvm_erase = 0x0702, 233 i40e_aqc_opc_nvm_update = 0x0703, 234 i40e_aqc_opc_nvm_config_read = 0x0704, 235 i40e_aqc_opc_nvm_config_write = 0x0705, 236 237 /* virtualization commands */ 238 i40e_aqc_opc_send_msg_to_pf = 0x0801, 239 i40e_aqc_opc_send_msg_to_vf = 0x0802, 240 i40e_aqc_opc_send_msg_to_peer = 0x0803, 241 242 /* alternate structure */ 243 i40e_aqc_opc_alternate_write = 0x0900, 244 i40e_aqc_opc_alternate_write_indirect = 0x0901, 245 i40e_aqc_opc_alternate_read = 0x0902, 246 i40e_aqc_opc_alternate_read_indirect = 0x0903, 247 i40e_aqc_opc_alternate_write_done = 0x0904, 248 i40e_aqc_opc_alternate_set_mode = 0x0905, 249 i40e_aqc_opc_alternate_clear_port = 0x0906, 250 251 /* LLDP commands */ 252 i40e_aqc_opc_lldp_get_mib = 0x0A00, 253 i40e_aqc_opc_lldp_update_mib = 0x0A01, 254 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 255 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 256 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 257 i40e_aqc_opc_lldp_stop = 0x0A05, 258 i40e_aqc_opc_lldp_start = 0x0A06, 259 260 /* Tunnel commands */ 261 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 262 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 263 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 264 265 /* Async Events */ 266 i40e_aqc_opc_event_lan_overflow = 0x1001, 267 268 /* OEM commands */ 269 i40e_aqc_opc_oem_parameter_change = 0xFE00, 270 i40e_aqc_opc_oem_device_status_change = 0xFE01, 271 272 /* debug commands */ 273 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 274 i40e_aqc_opc_debug_set_mode = 0xFF01, 275 i40e_aqc_opc_debug_read_reg = 0xFF03, 276 i40e_aqc_opc_debug_write_reg = 0xFF04, 277 i40e_aqc_opc_debug_modify_reg = 0xFF07, 278 i40e_aqc_opc_debug_dump_internals = 0xFF08, 279 i40e_aqc_opc_debug_modify_internals = 0xFF09, 280}; 281 282/* command structures and indirect data structures */ 283 284/* Structure naming conventions: 285 * - no suffix for direct command descriptor structures 286 * - _data for indirect sent data 287 * - _resp for indirect return data (data which is both will use _data) 288 * - _completion for direct return data 289 * - _element_ for repeated elements (may also be _data or _resp) 290 * 291 * Command structures are expected to overlay the params.raw member of the basic 292 * descriptor, and as such cannot exceed 16 bytes in length. 293 */ 294 295/* This macro is used to generate a compilation error if a structure 296 * is not exactly the correct length. It gives a divide by zero error if the 297 * structure is not of the correct size, otherwise it creates an enum that is 298 * never used. 299 */ 300#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 302 303/* This macro is used extensively to ensure that command structures are 16 304 * bytes in length as they have to map to the raw array of that size. 305 */ 306#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 307 308/* internal (0x00XX) commands */ 309 310/* Get version (direct 0x0001) */ 311struct i40e_aqc_get_version { 312 __le32 rom_ver; 313 __le32 fw_build; 314 __le16 fw_major; 315 __le16 fw_minor; 316 __le16 api_major; 317 __le16 api_minor; 318}; 319 320I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 321 322/* Send driver version (indirect 0x0002) */ 323struct i40e_aqc_driver_version { 324 u8 driver_major_ver; 325 u8 driver_minor_ver; 326 u8 driver_build_ver; 327 u8 driver_subbuild_ver; 328 u8 reserved[4]; 329 __le32 address_high; 330 __le32 address_low; 331}; 332 333I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 334 335/* Queue Shutdown (direct 0x0003) */ 336struct i40e_aqc_queue_shutdown { 337 __le32 driver_unloading; 338#define I40E_AQ_DRIVER_UNLOADING 0x1 339 u8 reserved[12]; 340}; 341 342I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 343 344/* Set PF context (0x0004, direct) */ 345struct i40e_aqc_set_pf_context { 346 u8 pf_id; 347 u8 reserved[15]; 348}; 349 350I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 351 352/* Request resource ownership (direct 0x0008) 353 * Release resource ownership (direct 0x0009) 354 */ 355#define I40E_AQ_RESOURCE_NVM 1 356#define I40E_AQ_RESOURCE_SDP 2 357#define I40E_AQ_RESOURCE_ACCESS_READ 1 358#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 359#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 360#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 361 362struct i40e_aqc_request_resource { 363 __le16 resource_id; 364 __le16 access_type; 365 __le32 timeout; 366 __le32 resource_number; 367 u8 reserved[4]; 368}; 369 370I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 371 372/* Get function capabilities (indirect 0x000A) 373 * Get device capabilities (indirect 0x000B) 374 */ 375struct i40e_aqc_list_capabilites { 376 u8 command_flags; 377#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 378 u8 pf_index; 379 u8 reserved[2]; 380 __le32 count; 381 __le32 addr_high; 382 __le32 addr_low; 383}; 384 385I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 386 387struct i40e_aqc_list_capabilities_element_resp { 388 __le16 id; 389 u8 major_rev; 390 u8 minor_rev; 391 __le32 number; 392 __le32 logical_id; 393 __le32 phys_id; 394 u8 reserved[16]; 395}; 396 397/* list of caps */ 398 399#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 400#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 401#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 402#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 403#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 404#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 405#define I40E_AQ_CAP_ID_SRIOV 0x0012 406#define I40E_AQ_CAP_ID_VF 0x0013 407#define I40E_AQ_CAP_ID_VMDQ 0x0014 408#define I40E_AQ_CAP_ID_8021QBG 0x0015 409#define I40E_AQ_CAP_ID_8021QBR 0x0016 410#define I40E_AQ_CAP_ID_VSI 0x0017 411#define I40E_AQ_CAP_ID_DCB 0x0018 412#define I40E_AQ_CAP_ID_FCOE 0x0021 413#define I40E_AQ_CAP_ID_RSS 0x0040 414#define I40E_AQ_CAP_ID_RXQ 0x0041 415#define I40E_AQ_CAP_ID_TXQ 0x0042 416#define I40E_AQ_CAP_ID_MSIX 0x0043 417#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 418#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 419#define I40E_AQ_CAP_ID_1588 0x0046 420#define I40E_AQ_CAP_ID_IWARP 0x0051 421#define I40E_AQ_CAP_ID_LED 0x0061 422#define I40E_AQ_CAP_ID_SDP 0x0062 423#define I40E_AQ_CAP_ID_MDIO 0x0063 424#define I40E_AQ_CAP_ID_FLEX10 0x00F1 425#define I40E_AQ_CAP_ID_CEM 0x00F2 426 427/* Set CPPM Configuration (direct 0x0103) */ 428struct i40e_aqc_cppm_configuration { 429 __le16 command_flags; 430#define I40E_AQ_CPPM_EN_LTRC 0x0800 431#define I40E_AQ_CPPM_EN_DMCTH 0x1000 432#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 433#define I40E_AQ_CPPM_EN_HPTC 0x4000 434#define I40E_AQ_CPPM_EN_DMARC 0x8000 435 __le16 ttlx; 436 __le32 dmacr; 437 __le16 dmcth; 438 u8 hptc; 439 u8 reserved; 440 __le32 pfltrc; 441}; 442 443I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 444 445/* Set ARP Proxy command / response (indirect 0x0104) */ 446struct i40e_aqc_arp_proxy_data { 447 __le16 command_flags; 448#define I40E_AQ_ARP_INIT_IPV4 0x0008 449#define I40E_AQ_ARP_UNSUP_CTL 0x0010 450#define I40E_AQ_ARP_ENA 0x0020 451#define I40E_AQ_ARP_ADD_IPV4 0x0040 452#define I40E_AQ_ARP_DEL_IPV4 0x0080 453 __le16 table_id; 454 __le32 pfpm_proxyfc; 455 __le32 ip_addr; 456 u8 mac_addr[6]; 457}; 458 459/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 460struct i40e_aqc_ns_proxy_data { 461 __le16 table_idx_mac_addr_0; 462 __le16 table_idx_mac_addr_1; 463 __le16 table_idx_ipv6_0; 464 __le16 table_idx_ipv6_1; 465 __le16 control; 466#define I40E_AQ_NS_PROXY_ADD_0 0x0100 467#define I40E_AQ_NS_PROXY_DEL_0 0x0200 468#define I40E_AQ_NS_PROXY_ADD_1 0x0400 469#define I40E_AQ_NS_PROXY_DEL_1 0x0800 470#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 471#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 472#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 473#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 474#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 475#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 476#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 477 u8 mac_addr_0[6]; 478 u8 mac_addr_1[6]; 479 u8 local_mac_addr[6]; 480 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 481 u8 ipv6_addr_1[16]; 482}; 483 484/* Manage LAA Command (0x0106) - obsolete */ 485struct i40e_aqc_mng_laa { 486 __le16 command_flags; 487#define I40E_AQ_LAA_FLAG_WR 0x8000 488 u8 reserved[2]; 489 __le32 sal; 490 __le16 sah; 491 u8 reserved2[6]; 492}; 493 494/* Manage MAC Address Read Command (indirect 0x0107) */ 495struct i40e_aqc_mac_address_read { 496 __le16 command_flags; 497#define I40E_AQC_LAN_ADDR_VALID 0x10 498#define I40E_AQC_SAN_ADDR_VALID 0x20 499#define I40E_AQC_PORT_ADDR_VALID 0x40 500#define I40E_AQC_WOL_ADDR_VALID 0x80 501#define I40E_AQC_ADDR_VALID_MASK 0xf0 502 u8 reserved[6]; 503 __le32 addr_high; 504 __le32 addr_low; 505}; 506 507I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 508 509struct i40e_aqc_mac_address_read_data { 510 u8 pf_lan_mac[6]; 511 u8 pf_san_mac[6]; 512 u8 port_mac[6]; 513 u8 pf_wol_mac[6]; 514}; 515 516I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 517 518/* Manage MAC Address Write Command (0x0108) */ 519struct i40e_aqc_mac_address_write { 520 __le16 command_flags; 521#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 522#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 523#define I40E_AQC_WRITE_TYPE_PORT 0x8000 524#define I40E_AQC_WRITE_TYPE_MASK 0xc000 525 __le16 mac_sah; 526 __le32 mac_sal; 527 u8 reserved[8]; 528}; 529 530I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 531 532/* PXE commands (0x011x) */ 533 534/* Clear PXE Command and response (direct 0x0110) */ 535struct i40e_aqc_clear_pxe { 536 u8 rx_cnt; 537 u8 reserved[15]; 538}; 539 540I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 541 542/* Switch configuration commands (0x02xx) */ 543 544/* Used by many indirect commands that only pass an seid and a buffer in the 545 * command 546 */ 547struct i40e_aqc_switch_seid { 548 __le16 seid; 549 u8 reserved[6]; 550 __le32 addr_high; 551 __le32 addr_low; 552}; 553 554I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 555 556/* Get Switch Configuration command (indirect 0x0200) 557 * uses i40e_aqc_switch_seid for the descriptor 558 */ 559struct i40e_aqc_get_switch_config_header_resp { 560 __le16 num_reported; 561 __le16 num_total; 562 u8 reserved[12]; 563}; 564 565struct i40e_aqc_switch_config_element_resp { 566 u8 element_type; 567#define I40E_AQ_SW_ELEM_TYPE_MAC 1 568#define I40E_AQ_SW_ELEM_TYPE_PF 2 569#define I40E_AQ_SW_ELEM_TYPE_VF 3 570#define I40E_AQ_SW_ELEM_TYPE_EMP 4 571#define I40E_AQ_SW_ELEM_TYPE_BMC 5 572#define I40E_AQ_SW_ELEM_TYPE_PV 16 573#define I40E_AQ_SW_ELEM_TYPE_VEB 17 574#define I40E_AQ_SW_ELEM_TYPE_PA 18 575#define I40E_AQ_SW_ELEM_TYPE_VSI 19 576 u8 revision; 577#define I40E_AQ_SW_ELEM_REV_1 1 578 __le16 seid; 579 __le16 uplink_seid; 580 __le16 downlink_seid; 581 u8 reserved[3]; 582 u8 connection_type; 583#define I40E_AQ_CONN_TYPE_REGULAR 0x1 584#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 585#define I40E_AQ_CONN_TYPE_CASCADED 0x3 586 __le16 scheduler_id; 587 __le16 element_info; 588}; 589 590/* Get Switch Configuration (indirect 0x0200) 591 * an array of elements are returned in the response buffer 592 * the first in the array is the header, remainder are elements 593 */ 594struct i40e_aqc_get_switch_config_resp { 595 struct i40e_aqc_get_switch_config_header_resp header; 596 struct i40e_aqc_switch_config_element_resp element[1]; 597}; 598 599/* Add Statistics (direct 0x0201) 600 * Remove Statistics (direct 0x0202) 601 */ 602struct i40e_aqc_add_remove_statistics { 603 __le16 seid; 604 __le16 vlan; 605 __le16 stat_index; 606 u8 reserved[10]; 607}; 608 609I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 610 611/* Set Port Parameters command (direct 0x0203) */ 612struct i40e_aqc_set_port_parameters { 613 __le16 command_flags; 614#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 615#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 616#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 617 __le16 bad_frame_vsi; 618 __le16 default_seid; /* reserved for command */ 619 u8 reserved[10]; 620}; 621 622I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 623 624/* Get Switch Resource Allocation (indirect 0x0204) */ 625struct i40e_aqc_get_switch_resource_alloc { 626 u8 num_entries; /* reserved for command */ 627 u8 reserved[7]; 628 __le32 addr_high; 629 __le32 addr_low; 630}; 631 632I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 633 634/* expect an array of these structs in the response buffer */ 635struct i40e_aqc_switch_resource_alloc_element_resp { 636 u8 resource_type; 637#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 638#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 639#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 640#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 641#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 642#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 643#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 644#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 645#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 646#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 647#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 648#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 649#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 650#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 651#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 652#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 653#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 654#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 655#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 656 u8 reserved1; 657 __le16 guaranteed; 658 __le16 total; 659 __le16 used; 660 __le16 total_unalloced; 661 u8 reserved2[6]; 662}; 663 664/* Add VSI (indirect 0x0210) 665 * this indirect command uses struct i40e_aqc_vsi_properties_data 666 * as the indirect buffer (128 bytes) 667 * 668 * Update VSI (indirect 0x211) 669 * uses the same data structure as Add VSI 670 * 671 * Get VSI (indirect 0x0212) 672 * uses the same completion and data structure as Add VSI 673 */ 674struct i40e_aqc_add_get_update_vsi { 675 __le16 uplink_seid; 676 u8 connection_type; 677#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 678#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 679#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 680 u8 reserved1; 681 u8 vf_id; 682 u8 reserved2; 683 __le16 vsi_flags; 684#define I40E_AQ_VSI_TYPE_SHIFT 0x0 685#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 686#define I40E_AQ_VSI_TYPE_VF 0x0 687#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 688#define I40E_AQ_VSI_TYPE_PF 0x2 689#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 690#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 691 __le32 addr_high; 692 __le32 addr_low; 693}; 694 695I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 696 697struct i40e_aqc_add_get_update_vsi_completion { 698 __le16 seid; 699 __le16 vsi_number; 700 __le16 vsi_used; 701 __le16 vsi_free; 702 __le32 addr_high; 703 __le32 addr_low; 704}; 705 706I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 707 708struct i40e_aqc_vsi_properties_data { 709 /* first 96 byte are written by SW */ 710 __le16 valid_sections; 711#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 712#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 713#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 714#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 715#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 716#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 717#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 718#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 719#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 720#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 721 /* switch section */ 722 __le16 switch_id; /* 12bit id combined with flags below */ 723#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 724#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 725#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 726#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 727#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 728 u8 sw_reserved[2]; 729 /* security section */ 730 u8 sec_flags; 731#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 732#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 733#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 734 u8 sec_reserved; 735 /* VLAN section */ 736 __le16 pvid; /* VLANS include priority bits */ 737 __le16 fcoe_pvid; 738 u8 port_vlan_flags; 739#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 740#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 741 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 742#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 743#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 744#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 745#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 746#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 747#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 748 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 749#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 750#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 751#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 752#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 753 u8 pvlan_reserved[3]; 754 /* ingress egress up sections */ 755 __le32 ingress_table; /* bitmap, 3 bits per up */ 756#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 757#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 758 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 759#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 760#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 761 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 762#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 763#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 764 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 765#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 766#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 767 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 768#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 769#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 770 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 771#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 772#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 773 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 774#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 775#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 776 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 777#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 778#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 779 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 780 __le32 egress_table; /* same defines as for ingress table */ 781 /* cascaded PV section */ 782 __le16 cas_pv_tag; 783 u8 cas_pv_flags; 784#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 785#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 786 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 787#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 788#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 789#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 790#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 791#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 792#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 793 u8 cas_pv_reserved; 794 /* queue mapping section */ 795 __le16 mapping_flags; 796#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 797#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 798 __le16 queue_mapping[16]; 799#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 800#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 801 __le16 tc_mapping[8]; 802#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 803#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 804 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 805#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 806#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 807 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 808 /* queueing option section */ 809 u8 queueing_opt_flags; 810#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 811#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 812 u8 queueing_opt_reserved[3]; 813 /* scheduler section */ 814 u8 up_enable_bits; 815 u8 sched_reserved; 816 /* outer up section */ 817 __le32 outer_up_table; /* same structure and defines as ingress table */ 818 u8 cmd_reserved[8]; 819 /* last 32 bytes are written by FW */ 820 __le16 qs_handle[8]; 821#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 822 __le16 stat_counter_idx; 823 __le16 sched_id; 824 u8 resp_reserved[12]; 825}; 826 827I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 828 829/* Add Port Virtualizer (direct 0x0220) 830 * also used for update PV (direct 0x0221) but only flags are used 831 * (IS_CTRL_PORT only works on add PV) 832 */ 833struct i40e_aqc_add_update_pv { 834 __le16 command_flags; 835#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 836#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 837#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 838#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 839 __le16 uplink_seid; 840 __le16 connected_seid; 841 u8 reserved[10]; 842}; 843 844I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 845 846struct i40e_aqc_add_update_pv_completion { 847 /* reserved for update; for add also encodes error if rc == ENOSPC */ 848 __le16 pv_seid; 849#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 850#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 851#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 852#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 853 u8 reserved[14]; 854}; 855 856I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 857 858/* Get PV Params (direct 0x0222) 859 * uses i40e_aqc_switch_seid for the descriptor 860 */ 861 862struct i40e_aqc_get_pv_params_completion { 863 __le16 seid; 864 __le16 default_stag; 865 __le16 pv_flags; /* same flags as add_pv */ 866#define I40E_AQC_GET_PV_PV_TYPE 0x1 867#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 868#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 869 u8 reserved[8]; 870 __le16 default_port_seid; 871}; 872 873I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 874 875/* Add VEB (direct 0x0230) */ 876struct i40e_aqc_add_veb { 877 __le16 uplink_seid; 878 __le16 downlink_seid; 879 __le16 veb_flags; 880#define I40E_AQC_ADD_VEB_FLOATING 0x1 881#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 882#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 883 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 884#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 885#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 886#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 887 u8 enable_tcs; 888 u8 reserved[9]; 889}; 890 891I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 892 893struct i40e_aqc_add_veb_completion { 894 u8 reserved[6]; 895 __le16 switch_seid; 896 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 897 __le16 veb_seid; 898#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 899#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 900#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 901#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 902 __le16 statistic_index; 903 __le16 vebs_used; 904 __le16 vebs_free; 905}; 906 907I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 908 909/* Get VEB Parameters (direct 0x0232) 910 * uses i40e_aqc_switch_seid for the descriptor 911 */ 912struct i40e_aqc_get_veb_parameters_completion { 913 __le16 seid; 914 __le16 switch_id; 915 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 916 __le16 statistic_index; 917 __le16 vebs_used; 918 __le16 vebs_free; 919 u8 reserved[4]; 920}; 921 922I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 923 924/* Delete Element (direct 0x0243) 925 * uses the generic i40e_aqc_switch_seid 926 */ 927 928/* Add MAC-VLAN (indirect 0x0250) */ 929 930/* used for the command for most vlan commands */ 931struct i40e_aqc_macvlan { 932 __le16 num_addresses; 933 __le16 seid[3]; 934#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 935#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 936 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 937#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 938 __le32 addr_high; 939 __le32 addr_low; 940}; 941 942I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 943 944/* indirect data for command and response */ 945struct i40e_aqc_add_macvlan_element_data { 946 u8 mac_addr[6]; 947 __le16 vlan_tag; 948 __le16 flags; 949#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 950#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 951#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 952#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 953 __le16 queue_number; 954#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 955#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 956 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 957 /* response section */ 958 u8 match_method; 959#define I40E_AQC_MM_PERFECT_MATCH 0x01 960#define I40E_AQC_MM_HASH_MATCH 0x02 961#define I40E_AQC_MM_ERR_NO_RES 0xFF 962 u8 reserved1[3]; 963}; 964 965struct i40e_aqc_add_remove_macvlan_completion { 966 __le16 perfect_mac_used; 967 __le16 perfect_mac_free; 968 __le16 unicast_hash_free; 969 __le16 multicast_hash_free; 970 __le32 addr_high; 971 __le32 addr_low; 972}; 973 974I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 975 976/* Remove MAC-VLAN (indirect 0x0251) 977 * uses i40e_aqc_macvlan for the descriptor 978 * data points to an array of num_addresses of elements 979 */ 980 981struct i40e_aqc_remove_macvlan_element_data { 982 u8 mac_addr[6]; 983 __le16 vlan_tag; 984 u8 flags; 985#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 986#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 987#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 988#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 989 u8 reserved[3]; 990 /* reply section */ 991 u8 error_code; 992#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 993#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 994 u8 reply_reserved[3]; 995}; 996 997/* Add VLAN (indirect 0x0252) 998 * Remove VLAN (indirect 0x0253) 999 * use the generic i40e_aqc_macvlan for the command 1000 */ 1001struct i40e_aqc_add_remove_vlan_element_data { 1002 __le16 vlan_tag; 1003 u8 vlan_flags; 1004/* flags for add VLAN */ 1005#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1006#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1007#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \ 1008 I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1009#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1010#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1011#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1012#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1013#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1014#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1015#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1016#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1017#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1018/* flags for remove VLAN */ 1019#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1020 u8 reserved; 1021 u8 result; 1022/* flags for add VLAN */ 1023#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1024#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1025#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1026/* flags for remove VLAN */ 1027#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1028#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1029 u8 reserved1[3]; 1030}; 1031 1032struct i40e_aqc_add_remove_vlan_completion { 1033 u8 reserved[4]; 1034 __le16 vlans_used; 1035 __le16 vlans_free; 1036 __le32 addr_high; 1037 __le32 addr_low; 1038}; 1039 1040/* Set VSI Promiscuous Modes (direct 0x0254) */ 1041struct i40e_aqc_set_vsi_promiscuous_modes { 1042 __le16 promiscuous_flags; 1043 __le16 valid_flags; 1044/* flags used for both fields above */ 1045#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1046#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1047#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1048#define I40E_AQC_SET_VSI_DEFAULT 0x08 1049#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1050 __le16 seid; 1051#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1052 __le16 vlan_tag; 1053#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1054 u8 reserved[8]; 1055}; 1056 1057I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1058 1059/* Add S/E-tag command (direct 0x0255) 1060 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1061 */ 1062struct i40e_aqc_add_tag { 1063 __le16 flags; 1064#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1065 __le16 seid; 1066#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1067#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1068 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1069 __le16 tag; 1070 __le16 queue_number; 1071 u8 reserved[8]; 1072}; 1073 1074I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1075 1076struct i40e_aqc_add_remove_tag_completion { 1077 u8 reserved[12]; 1078 __le16 tags_used; 1079 __le16 tags_free; 1080}; 1081 1082I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1083 1084/* Remove S/E-tag command (direct 0x0256) 1085 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1086 */ 1087struct i40e_aqc_remove_tag { 1088 __le16 seid; 1089#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1090#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1091 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1092 __le16 tag; 1093 u8 reserved[12]; 1094}; 1095 1096/* Add multicast E-Tag (direct 0x0257) 1097 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1098 * and no external data 1099 */ 1100struct i40e_aqc_add_remove_mcast_etag { 1101 __le16 pv_seid; 1102 __le16 etag; 1103 u8 num_unicast_etags; 1104 u8 reserved[3]; 1105 __le32 addr_high; /* address of array of 2-byte s-tags */ 1106 __le32 addr_low; 1107}; 1108 1109I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1110 1111struct i40e_aqc_add_remove_mcast_etag_completion { 1112 u8 reserved[4]; 1113 __le16 mcast_etags_used; 1114 __le16 mcast_etags_free; 1115 __le32 addr_high; 1116 __le32 addr_low; 1117 1118}; 1119 1120I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1121 1122/* Update S/E-Tag (direct 0x0259) */ 1123struct i40e_aqc_update_tag { 1124 __le16 seid; 1125#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1126#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1127 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1128 __le16 old_tag; 1129 __le16 new_tag; 1130 u8 reserved[10]; 1131}; 1132 1133I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1134 1135struct i40e_aqc_update_tag_completion { 1136 u8 reserved[12]; 1137 __le16 tags_used; 1138 __le16 tags_free; 1139}; 1140 1141I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1142 1143/* Add Control Packet filter (direct 0x025A) 1144 * Remove Control Packet filter (direct 0x025B) 1145 * uses the i40e_aqc_add_oveb_cloud, 1146 * and the generic direct completion structure 1147 */ 1148struct i40e_aqc_add_remove_control_packet_filter { 1149 u8 mac[6]; 1150 __le16 etype; 1151 __le16 flags; 1152#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1153#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1154#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1155#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1156#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1157 __le16 seid; 1158#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1159#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1160 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1161 __le16 queue; 1162 u8 reserved[2]; 1163}; 1164 1165I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1166 1167struct i40e_aqc_add_remove_control_packet_filter_completion { 1168 __le16 mac_etype_used; 1169 __le16 etype_used; 1170 __le16 mac_etype_free; 1171 __le16 etype_free; 1172 u8 reserved[8]; 1173}; 1174 1175I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1176 1177/* Add Cloud filters (indirect 0x025C) 1178 * Remove Cloud filters (indirect 0x025D) 1179 * uses the i40e_aqc_add_remove_cloud_filters, 1180 * and the generic indirect completion structure 1181 */ 1182struct i40e_aqc_add_remove_cloud_filters { 1183 u8 num_filters; 1184 u8 reserved; 1185 __le16 seid; 1186#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1187#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1188 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1189 u8 reserved2[4]; 1190 __le32 addr_high; 1191 __le32 addr_low; 1192}; 1193 1194I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1195 1196struct i40e_aqc_add_remove_cloud_filters_element_data { 1197 u8 outer_mac[6]; 1198 u8 inner_mac[6]; 1199 __le16 inner_vlan; 1200 union { 1201 struct { 1202 u8 reserved[12]; 1203 u8 data[4]; 1204 } v4; 1205 struct { 1206 u8 data[16]; 1207 } v6; 1208 } ipaddr; 1209 __le16 flags; 1210#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1211#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1212 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1213#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE 0x0002 1214#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE 0x0004 1215#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL 0x0007 1216/* 0x0000 reserved */ 1217#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1218/* 0x0002 reserved */ 1219#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1220#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1221/* 0x0005 reserved */ 1222#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1223/* 0x0007 reserved */ 1224/* 0x0008 reserved */ 1225#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1226#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1227#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1228#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1229 1230#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1231#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1232#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1233#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1234#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1235 1236#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1237#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1238#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1239#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1240#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1241#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1242 1243 __le32 tenant_id; 1244 u8 reserved[4]; 1245 __le16 queue_number; 1246#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1247#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \ 1248 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1249 u8 reserved2[14]; 1250 /* response section */ 1251 u8 allocation_result; 1252#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1253#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1254 u8 response_reserved[7]; 1255}; 1256 1257struct i40e_aqc_remove_cloud_filters_completion { 1258 __le16 perfect_ovlan_used; 1259 __le16 perfect_ovlan_free; 1260 __le16 vlan_used; 1261 __le16 vlan_free; 1262 __le32 addr_high; 1263 __le32 addr_low; 1264}; 1265 1266I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1267 1268/* Add Mirror Rule (indirect or direct 0x0260) 1269 * Delete Mirror Rule (indirect or direct 0x0261) 1270 * note: some rule types (4,5) do not use an external buffer. 1271 * take care to set the flags correctly. 1272 */ 1273struct i40e_aqc_add_delete_mirror_rule { 1274 __le16 seid; 1275 __le16 rule_type; 1276#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1277#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1278 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1279#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1280#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1281#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1282#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1283#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1284 __le16 num_entries; 1285 __le16 destination; /* VSI for add, rule id for delete */ 1286 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1287 __le32 addr_low; 1288}; 1289 1290I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1291 1292struct i40e_aqc_add_delete_mirror_rule_completion { 1293 u8 reserved[2]; 1294 __le16 rule_id; /* only used on add */ 1295 __le16 mirror_rules_used; 1296 __le16 mirror_rules_free; 1297 __le32 addr_high; 1298 __le32 addr_low; 1299}; 1300 1301I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1302 1303/* DCB 0x03xx*/ 1304 1305/* PFC Ignore (direct 0x0301) 1306 * the command and response use the same descriptor structure 1307 */ 1308struct i40e_aqc_pfc_ignore { 1309 u8 tc_bitmap; 1310 u8 command_flags; /* unused on response */ 1311#define I40E_AQC_PFC_IGNORE_SET 0x80 1312#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1313 u8 reserved[14]; 1314}; 1315 1316I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1317 1318/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1319 * with no parameters 1320 */ 1321 1322/* TX scheduler 0x04xx */ 1323 1324/* Almost all the indirect commands use 1325 * this generic struct to pass the SEID in param0 1326 */ 1327struct i40e_aqc_tx_sched_ind { 1328 __le16 vsi_seid; 1329 u8 reserved[6]; 1330 __le32 addr_high; 1331 __le32 addr_low; 1332}; 1333 1334I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1335 1336/* Several commands respond with a set of queue set handles */ 1337struct i40e_aqc_qs_handles_resp { 1338 __le16 qs_handles[8]; 1339}; 1340 1341/* Configure VSI BW limits (direct 0x0400) */ 1342struct i40e_aqc_configure_vsi_bw_limit { 1343 __le16 vsi_seid; 1344 u8 reserved[2]; 1345 __le16 credit; 1346 u8 reserved1[2]; 1347 u8 max_credit; /* 0-3, limit = 2^max */ 1348 u8 reserved2[7]; 1349}; 1350 1351I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1352 1353/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1354 * responds with i40e_aqc_qs_handles_resp 1355 */ 1356struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1357 u8 tc_valid_bits; 1358 u8 reserved[15]; 1359 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1360 1361 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1362 __le16 tc_bw_max[2]; 1363 u8 reserved1[28]; 1364}; 1365 1366/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1367 * responds with i40e_aqc_qs_handles_resp 1368 */ 1369struct i40e_aqc_configure_vsi_tc_bw_data { 1370 u8 tc_valid_bits; 1371 u8 reserved[3]; 1372 u8 tc_bw_credits[8]; 1373 u8 reserved1[4]; 1374 __le16 qs_handles[8]; 1375}; 1376 1377/* Query vsi bw configuration (indirect 0x0408) */ 1378struct i40e_aqc_query_vsi_bw_config_resp { 1379 u8 tc_valid_bits; 1380 u8 tc_suspended_bits; 1381 u8 reserved[14]; 1382 __le16 qs_handles[8]; 1383 u8 reserved1[4]; 1384 __le16 port_bw_limit; 1385 u8 reserved2[2]; 1386 u8 max_bw; /* 0-3, limit = 2^max */ 1387 u8 reserved3[23]; 1388}; 1389 1390/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1391struct i40e_aqc_query_vsi_ets_sla_config_resp { 1392 u8 tc_valid_bits; 1393 u8 reserved[3]; 1394 u8 share_credits[8]; 1395 __le16 credits[8]; 1396 1397 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1398 __le16 tc_bw_max[2]; 1399}; 1400 1401/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1402struct i40e_aqc_configure_switching_comp_bw_limit { 1403 __le16 seid; 1404 u8 reserved[2]; 1405 __le16 credit; 1406 u8 reserved1[2]; 1407 u8 max_bw; /* 0-3, limit = 2^max */ 1408 u8 reserved2[7]; 1409}; 1410 1411I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1412 1413/* Enable Physical Port ETS (indirect 0x0413) 1414 * Modify Physical Port ETS (indirect 0x0414) 1415 * Disable Physical Port ETS (indirect 0x0415) 1416 */ 1417struct i40e_aqc_configure_switching_comp_ets_data { 1418 u8 reserved[4]; 1419 u8 tc_valid_bits; 1420 u8 seepage; 1421#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1422 u8 tc_strict_priority_flags; 1423 u8 reserved1[17]; 1424 u8 tc_bw_share_credits[8]; 1425 u8 reserved2[96]; 1426}; 1427 1428/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1429struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1430 u8 tc_valid_bits; 1431 u8 reserved[15]; 1432 __le16 tc_bw_credit[8]; 1433 1434 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1435 __le16 tc_bw_max[2]; 1436 u8 reserved1[28]; 1437}; 1438 1439/* Configure Switching Component Bandwidth Allocation per Tc 1440 * (indirect 0x0417) 1441 */ 1442struct i40e_aqc_configure_switching_comp_bw_config_data { 1443 u8 tc_valid_bits; 1444 u8 reserved[2]; 1445 u8 absolute_credits; /* bool */ 1446 u8 tc_bw_share_credits[8]; 1447 u8 reserved1[20]; 1448}; 1449 1450/* Query Switching Component Configuration (indirect 0x0418) */ 1451struct i40e_aqc_query_switching_comp_ets_config_resp { 1452 u8 tc_valid_bits; 1453 u8 reserved[35]; 1454 __le16 port_bw_limit; 1455 u8 reserved1[2]; 1456 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1457 u8 reserved2[23]; 1458}; 1459 1460/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1461struct i40e_aqc_query_port_ets_config_resp { 1462 u8 reserved[4]; 1463 u8 tc_valid_bits; 1464 u8 reserved1; 1465 u8 tc_strict_priority_bits; 1466 u8 reserved2; 1467 u8 tc_bw_share_credits[8]; 1468 __le16 tc_bw_limits[8]; 1469 1470 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1471 __le16 tc_bw_max[2]; 1472 u8 reserved3[32]; 1473}; 1474 1475/* Query Switching Component Bandwidth Allocation per Traffic Type 1476 * (indirect 0x041A) 1477 */ 1478struct i40e_aqc_query_switching_comp_bw_config_resp { 1479 u8 tc_valid_bits; 1480 u8 reserved[2]; 1481 u8 absolute_credits_enable; /* bool */ 1482 u8 tc_bw_share_credits[8]; 1483 __le16 tc_bw_limits[8]; 1484 1485 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1486 __le16 tc_bw_max[2]; 1487}; 1488 1489/* Suspend/resume port TX traffic 1490 * (direct 0x041B and 0x041C) uses the generic SEID struct 1491 */ 1492 1493/* Configure partition BW 1494 * (indirect 0x041D) 1495 */ 1496struct i40e_aqc_configure_partition_bw_data { 1497 __le16 pf_valid_bits; 1498 u8 min_bw[16]; /* guaranteed bandwidth */ 1499 u8 max_bw[16]; /* bandwidth limit */ 1500}; 1501 1502/* Get and set the active HMC resource profile and status. 1503 * (direct 0x0500) and (direct 0x0501) 1504 */ 1505struct i40e_aq_get_set_hmc_resource_profile { 1506 u8 pm_profile; 1507 u8 pe_vf_enabled; 1508 u8 reserved[14]; 1509}; 1510 1511I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1512 1513enum i40e_aq_hmc_profile { 1514 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1515 I40E_HMC_PROFILE_DEFAULT = 1, 1516 I40E_HMC_PROFILE_FAVOR_VF = 2, 1517 I40E_HMC_PROFILE_EQUAL = 3, 1518}; 1519 1520#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1521#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1522 1523/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1524 1525/* set in param0 for get phy abilities to report qualified modules */ 1526#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1527#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1528 1529enum i40e_aq_phy_type { 1530 I40E_PHY_TYPE_SGMII = 0x0, 1531 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1532 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1533 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1534 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1535 I40E_PHY_TYPE_XAUI = 0x5, 1536 I40E_PHY_TYPE_XFI = 0x6, 1537 I40E_PHY_TYPE_SFI = 0x7, 1538 I40E_PHY_TYPE_XLAUI = 0x8, 1539 I40E_PHY_TYPE_XLPPI = 0x9, 1540 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1541 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1542 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1543 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1544 I40E_PHY_TYPE_100BASE_TX = 0x11, 1545 I40E_PHY_TYPE_1000BASE_T = 0x12, 1546 I40E_PHY_TYPE_10GBASE_T = 0x13, 1547 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1548 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1549 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1550 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1551 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1552 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1553 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1554 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1555 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1556 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1557 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1558 I40E_PHY_TYPE_MAX 1559}; 1560 1561#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1562#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1563#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1564#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1565#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1566 1567enum i40e_aq_link_speed { 1568 I40E_LINK_SPEED_UNKNOWN = 0, 1569 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1570 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1571 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1572 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1573 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1574}; 1575 1576struct i40e_aqc_module_desc { 1577 u8 oui[3]; 1578 u8 reserved1; 1579 u8 part_number[16]; 1580 u8 revision[4]; 1581 u8 reserved2[8]; 1582}; 1583 1584struct i40e_aq_get_phy_abilities_resp { 1585 __le32 phy_type; /* bitmap using the above enum for offsets */ 1586 u8 link_speed; /* bitmap using the above enum bit patterns */ 1587 u8 abilities; 1588#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1589#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1590#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1591#define I40E_AQ_PHY_LINK_ENABLED 0x08 1592#define I40E_AQ_PHY_AN_ENABLED 0x10 1593#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1594 __le16 eee_capability; 1595#define I40E_AQ_EEE_100BASE_TX 0x0002 1596#define I40E_AQ_EEE_1000BASE_T 0x0004 1597#define I40E_AQ_EEE_10GBASE_T 0x0008 1598#define I40E_AQ_EEE_1000BASE_KX 0x0010 1599#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1600#define I40E_AQ_EEE_10GBASE_KR 0x0040 1601 __le32 eeer_val; 1602 u8 d3_lpan; 1603#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1604 u8 reserved[3]; 1605 u8 phy_id[4]; 1606 u8 module_type[3]; 1607 u8 qualified_module_count; 1608#define I40E_AQ_PHY_MAX_QMS 16 1609 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1610}; 1611 1612/* Set PHY Config (direct 0x0601) */ 1613struct i40e_aq_set_phy_config { /* same bits as above in all */ 1614 __le32 phy_type; 1615 u8 link_speed; 1616 u8 abilities; 1617/* bits 0-2 use the values from get_phy_abilities_resp */ 1618#define I40E_AQ_PHY_ENABLE_LINK 0x08 1619#define I40E_AQ_PHY_ENABLE_AN 0x10 1620#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1621 __le16 eee_capability; 1622 __le32 eeer; 1623 u8 low_power_ctrl; 1624 u8 reserved[3]; 1625}; 1626 1627I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1628 1629/* Set MAC Config command data structure (direct 0x0603) */ 1630struct i40e_aq_set_mac_config { 1631 __le16 max_frame_size; 1632 u8 params; 1633#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1634#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1635#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1636#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1637#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1638#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1639#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1640#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1641#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1642#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1643#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1644#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1645#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1646#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1647 u8 tx_timer_priority; /* bitmap */ 1648 __le16 tx_timer_value; 1649 __le16 fc_refresh_threshold; 1650 u8 reserved[8]; 1651}; 1652 1653I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1654 1655/* Restart Auto-Negotiation (direct 0x605) */ 1656struct i40e_aqc_set_link_restart_an { 1657 u8 command; 1658#define I40E_AQ_PHY_RESTART_AN 0x02 1659#define I40E_AQ_PHY_LINK_ENABLE 0x04 1660 u8 reserved[15]; 1661}; 1662 1663I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1664 1665/* Get Link Status cmd & response data structure (direct 0x0607) */ 1666struct i40e_aqc_get_link_status { 1667 __le16 command_flags; /* only field set on command */ 1668#define I40E_AQ_LSE_MASK 0x3 1669#define I40E_AQ_LSE_NOP 0x0 1670#define I40E_AQ_LSE_DISABLE 0x2 1671#define I40E_AQ_LSE_ENABLE 0x3 1672/* only response uses this flag */ 1673#define I40E_AQ_LSE_IS_ENABLED 0x1 1674 u8 phy_type; /* i40e_aq_phy_type */ 1675 u8 link_speed; /* i40e_aq_link_speed */ 1676 u8 link_info; 1677#define I40E_AQ_LINK_UP 0x01 1678#define I40E_AQ_LINK_FAULT 0x02 1679#define I40E_AQ_LINK_FAULT_TX 0x04 1680#define I40E_AQ_LINK_FAULT_RX 0x08 1681#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1682#define I40E_AQ_MEDIA_AVAILABLE 0x40 1683#define I40E_AQ_SIGNAL_DETECT 0x80 1684 u8 an_info; 1685#define I40E_AQ_AN_COMPLETED 0x01 1686#define I40E_AQ_LP_AN_ABILITY 0x02 1687#define I40E_AQ_PD_FAULT 0x04 1688#define I40E_AQ_FEC_EN 0x08 1689#define I40E_AQ_PHY_LOW_POWER 0x10 1690#define I40E_AQ_LINK_PAUSE_TX 0x20 1691#define I40E_AQ_LINK_PAUSE_RX 0x40 1692#define I40E_AQ_QUALIFIED_MODULE 0x80 1693 u8 ext_info; 1694#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1695#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1696#define I40E_AQ_LINK_TX_SHIFT 0x02 1697#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1698#define I40E_AQ_LINK_TX_ACTIVE 0x00 1699#define I40E_AQ_LINK_TX_DRAINED 0x01 1700#define I40E_AQ_LINK_TX_FLUSHED 0x03 1701#define I40E_AQ_LINK_FORCED_40G 0x10 1702 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1703 __le16 max_frame_size; 1704 u8 config; 1705#define I40E_AQ_CONFIG_CRC_ENA 0x04 1706#define I40E_AQ_CONFIG_PACING_MASK 0x78 1707 u8 reserved[5]; 1708}; 1709 1710I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1711 1712/* Set event mask command (direct 0x613) */ 1713struct i40e_aqc_set_phy_int_mask { 1714 u8 reserved[8]; 1715 __le16 event_mask; 1716#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1717#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1718#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1719#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1720#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1721#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1722#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1723#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1724#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1725 u8 reserved1[6]; 1726}; 1727 1728I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1729 1730/* Get Local AN advt register (direct 0x0614) 1731 * Set Local AN advt register (direct 0x0615) 1732 * Get Link Partner AN advt register (direct 0x0616) 1733 */ 1734struct i40e_aqc_an_advt_reg { 1735 __le32 local_an_reg0; 1736 __le16 local_an_reg1; 1737 u8 reserved[10]; 1738}; 1739 1740I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1741 1742/* Set Loopback mode (0x0618) */ 1743struct i40e_aqc_set_lb_mode { 1744 __le16 lb_mode; 1745#define I40E_AQ_LB_PHY_LOCAL 0x01 1746#define I40E_AQ_LB_PHY_REMOTE 0x02 1747#define I40E_AQ_LB_MAC_LOCAL 0x04 1748 u8 reserved[14]; 1749}; 1750 1751I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1752 1753/* Set PHY Debug command (0x0622) */ 1754struct i40e_aqc_set_phy_debug { 1755 u8 command_flags; 1756#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1757#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1758#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1759 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1760#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1761#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1762#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1763#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1764 u8 reserved[15]; 1765}; 1766 1767I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1768 1769enum i40e_aq_phy_reg_type { 1770 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1771 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1772 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1773}; 1774 1775/* NVM Read command (indirect 0x0701) 1776 * NVM Erase commands (direct 0x0702) 1777 * NVM Update commands (indirect 0x0703) 1778 */ 1779struct i40e_aqc_nvm_update { 1780 u8 command_flags; 1781#define I40E_AQ_NVM_LAST_CMD 0x01 1782#define I40E_AQ_NVM_FLASH_ONLY 0x80 1783 u8 module_pointer; 1784 __le16 length; 1785 __le32 offset; 1786 __le32 addr_high; 1787 __le32 addr_low; 1788}; 1789 1790I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1791 1792/* NVM Config Read (indirect 0x0704) */ 1793struct i40e_aqc_nvm_config_read { 1794 __le16 cmd_flags; 1795#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1796#define ANVM_READ_SINGLE_FEATURE 0 1797#define ANVM_READ_MULTIPLE_FEATURES 1 1798 __le16 element_count; 1799 __le16 element_id; /* Feature/field ID */ 1800 u8 reserved[2]; 1801 __le32 address_high; 1802 __le32 address_low; 1803}; 1804 1805I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1806 1807/* NVM Config Write (indirect 0x0705) */ 1808struct i40e_aqc_nvm_config_write { 1809 __le16 cmd_flags; 1810 __le16 element_count; 1811 u8 reserved[4]; 1812 __le32 address_high; 1813 __le32 address_low; 1814}; 1815 1816I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1817 1818struct i40e_aqc_nvm_config_data_feature { 1819 __le16 feature_id; 1820 __le16 instance_id; 1821 __le16 feature_options; 1822 __le16 feature_selection; 1823}; 1824 1825struct i40e_aqc_nvm_config_data_immediate_field { 1826#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2 1827 __le16 field_id; 1828 __le16 instance_id; 1829 __le16 field_options; 1830 __le16 field_value; 1831}; 1832 1833/* Send to PF command (indirect 0x0801) id is only used by PF 1834 * Send to VF command (indirect 0x0802) id is only used by PF 1835 * Send to Peer PF command (indirect 0x0803) 1836 */ 1837struct i40e_aqc_pf_vf_message { 1838 __le32 id; 1839 u8 reserved[4]; 1840 __le32 addr_high; 1841 __le32 addr_low; 1842}; 1843 1844I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1845 1846/* Alternate structure */ 1847 1848/* Direct write (direct 0x0900) 1849 * Direct read (direct 0x0902) 1850 */ 1851struct i40e_aqc_alternate_write { 1852 __le32 address0; 1853 __le32 data0; 1854 __le32 address1; 1855 __le32 data1; 1856}; 1857 1858I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1859 1860/* Indirect write (indirect 0x0901) 1861 * Indirect read (indirect 0x0903) 1862 */ 1863 1864struct i40e_aqc_alternate_ind_write { 1865 __le32 address; 1866 __le32 length; 1867 __le32 addr_high; 1868 __le32 addr_low; 1869}; 1870 1871I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1872 1873/* Done alternate write (direct 0x0904) 1874 * uses i40e_aq_desc 1875 */ 1876struct i40e_aqc_alternate_write_done { 1877 __le16 cmd_flags; 1878#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1879#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1880#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1881#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1882 u8 reserved[14]; 1883}; 1884 1885I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1886 1887/* Set OEM mode (direct 0x0905) */ 1888struct i40e_aqc_alternate_set_mode { 1889 __le32 mode; 1890#define I40E_AQ_ALTERNATE_MODE_NONE 0 1891#define I40E_AQ_ALTERNATE_MODE_OEM 1 1892 u8 reserved[12]; 1893}; 1894 1895I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1896 1897/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1898 1899/* async events 0x10xx */ 1900 1901/* Lan Queue Overflow Event (direct, 0x1001) */ 1902struct i40e_aqc_lan_overflow { 1903 __le32 prtdcb_rupto; 1904 __le32 otx_ctl; 1905 u8 reserved[8]; 1906}; 1907 1908I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1909 1910/* Get LLDP MIB (indirect 0x0A00) */ 1911struct i40e_aqc_lldp_get_mib { 1912 u8 type; 1913 u8 reserved1; 1914#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1915#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1916#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1917#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1918#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1919#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1920#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1921#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1922#define I40E_AQ_LLDP_TX_SHIFT 0x4 1923#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1924/* TX pause flags use I40E_AQ_LINK_TX_* above */ 1925 __le16 local_len; 1926 __le16 remote_len; 1927 u8 reserved2[2]; 1928 __le32 addr_high; 1929 __le32 addr_low; 1930}; 1931 1932I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1933 1934/* Configure LLDP MIB Change Event (direct 0x0A01) 1935 * also used for the event (with type in the command field) 1936 */ 1937struct i40e_aqc_lldp_update_mib { 1938 u8 command; 1939#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1940#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1941 u8 reserved[7]; 1942 __le32 addr_high; 1943 __le32 addr_low; 1944}; 1945 1946I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 1947 1948/* Add LLDP TLV (indirect 0x0A02) 1949 * Delete LLDP TLV (indirect 0x0A04) 1950 */ 1951struct i40e_aqc_lldp_add_tlv { 1952 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1953 u8 reserved1[1]; 1954 __le16 len; 1955 u8 reserved2[4]; 1956 __le32 addr_high; 1957 __le32 addr_low; 1958}; 1959 1960I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 1961 1962/* Update LLDP TLV (indirect 0x0A03) */ 1963struct i40e_aqc_lldp_update_tlv { 1964 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1965 u8 reserved; 1966 __le16 old_len; 1967 __le16 new_offset; 1968 __le16 new_len; 1969 __le32 addr_high; 1970 __le32 addr_low; 1971}; 1972 1973I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 1974 1975/* Stop LLDP (direct 0x0A05) */ 1976struct i40e_aqc_lldp_stop { 1977 u8 command; 1978#define I40E_AQ_LLDP_AGENT_STOP 0x0 1979#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 1980 u8 reserved[15]; 1981}; 1982 1983I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 1984 1985/* Start LLDP (direct 0x0A06) */ 1986 1987struct i40e_aqc_lldp_start { 1988 u8 command; 1989#define I40E_AQ_LLDP_AGENT_START 0x1 1990 u8 reserved[15]; 1991}; 1992 1993I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 1994 1995/* Apply MIB changes (0x0A07) 1996 * uses the generic struc as it contains no data 1997 */ 1998 1999/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2000struct i40e_aqc_add_udp_tunnel { 2001 __le16 udp_port; 2002 u8 reserved0[3]; 2003 u8 protocol_type; 2004#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2005#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2006#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2007 u8 reserved1[10]; 2008}; 2009 2010I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2011 2012struct i40e_aqc_add_udp_tunnel_completion { 2013 __le16 udp_port; 2014 u8 filter_entry_index; 2015 u8 multiple_pfs; 2016#define I40E_AQC_SINGLE_PF 0x0 2017#define I40E_AQC_MULTIPLE_PFS 0x1 2018 u8 total_filters; 2019 u8 reserved[11]; 2020}; 2021 2022I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2023 2024/* remove UDP Tunnel command (0x0B01) */ 2025struct i40e_aqc_remove_udp_tunnel { 2026 u8 reserved[2]; 2027 u8 index; /* 0 to 15 */ 2028 u8 pf_filters; 2029 u8 total_filters; 2030 u8 reserved2[11]; 2031}; 2032 2033I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2034 2035struct i40e_aqc_del_udp_tunnel_completion { 2036 __le16 udp_port; 2037 u8 index; /* 0 to 15 */ 2038 u8 multiple_pfs; 2039 u8 total_filters_used; 2040 u8 reserved; 2041 u8 tunnels_free; 2042 u8 reserved1[9]; 2043}; 2044 2045I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2046 2047/* tunnel key structure 0x0B10 */ 2048 2049struct i40e_aqc_tunnel_key_structure_A0 { 2050 __le16 key1_off; 2051 __le16 key1_len; 2052 __le16 key2_off; 2053 __le16 key2_len; 2054 __le16 flags; 2055#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2056/* response flags */ 2057#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2058#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2059#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2060 u8 resreved[6]; 2061}; 2062 2063I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); 2064 2065struct i40e_aqc_tunnel_key_structure { 2066 u8 key1_off; 2067 u8 key2_off; 2068 u8 key1_len; /* 0 to 15 */ 2069 u8 key2_len; /* 0 to 15 */ 2070 u8 flags; 2071#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2072/* response flags */ 2073#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2074#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2075#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2076 u8 network_key_index; 2077#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2078#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2079#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2080#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2081 u8 reserved[10]; 2082}; 2083 2084I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2085 2086/* OEM mode commands (direct 0xFE0x) */ 2087struct i40e_aqc_oem_param_change { 2088 __le32 param_type; 2089#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2090#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2091#define I40E_AQ_OEM_PARAM_MAC 2 2092 __le32 param_value1; 2093 u8 param_value2[8]; 2094}; 2095 2096I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2097 2098struct i40e_aqc_oem_state_change { 2099 __le32 state; 2100#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2101#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2102 u8 reserved[12]; 2103}; 2104 2105I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2106 2107/* debug commands */ 2108 2109/* get device id (0xFF00) uses the generic structure */ 2110 2111/* set test more (0xFF01, internal) */ 2112 2113struct i40e_acq_set_test_mode { 2114 u8 mode; 2115#define I40E_AQ_TEST_PARTIAL 0 2116#define I40E_AQ_TEST_FULL 1 2117#define I40E_AQ_TEST_NVM 2 2118 u8 reserved[3]; 2119 u8 command; 2120#define I40E_AQ_TEST_OPEN 0 2121#define I40E_AQ_TEST_CLOSE 1 2122#define I40E_AQ_TEST_INC 2 2123 u8 reserved2[3]; 2124 __le32 address_high; 2125 __le32 address_low; 2126}; 2127 2128I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2129 2130/* Debug Read Register command (0xFF03) 2131 * Debug Write Register command (0xFF04) 2132 */ 2133struct i40e_aqc_debug_reg_read_write { 2134 __le32 reserved; 2135 __le32 address; 2136 __le32 value_high; 2137 __le32 value_low; 2138}; 2139 2140I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2141 2142/* Scatter/gather Reg Read (indirect 0xFF05) 2143 * Scatter/gather Reg Write (indirect 0xFF06) 2144 */ 2145 2146/* i40e_aq_desc is used for the command */ 2147struct i40e_aqc_debug_reg_sg_element_data { 2148 __le32 address; 2149 __le32 value; 2150}; 2151 2152/* Debug Modify register (direct 0xFF07) */ 2153struct i40e_aqc_debug_modify_reg { 2154 __le32 address; 2155 __le32 value; 2156 __le32 clear_mask; 2157 __le32 set_mask; 2158}; 2159 2160I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2161 2162/* dump internal data (0xFF08, indirect) */ 2163 2164#define I40E_AQ_CLUSTER_ID_AUX 0 2165#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2166#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2167#define I40E_AQ_CLUSTER_ID_HMC 3 2168#define I40E_AQ_CLUSTER_ID_MAC0 4 2169#define I40E_AQ_CLUSTER_ID_MAC1 5 2170#define I40E_AQ_CLUSTER_ID_MAC2 6 2171#define I40E_AQ_CLUSTER_ID_MAC3 7 2172#define I40E_AQ_CLUSTER_ID_DCB 8 2173#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2174#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2175#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2176 2177struct i40e_aqc_debug_dump_internals { 2178 u8 cluster_id; 2179 u8 table_id; 2180 __le16 data_size; 2181 __le32 idx; 2182 __le32 address_high; 2183 __le32 address_low; 2184}; 2185 2186I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2187 2188struct i40e_aqc_debug_modify_internals { 2189 u8 cluster_id; 2190 u8 cluster_specific_params[7]; 2191 __le32 address_high; 2192 __le32 address_low; 2193}; 2194 2195I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2196 2197#endif 2198