1/* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 * 5 * This code was derived from the Intel e1000e Linux driver. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#ifndef _PCH_GBE_H_ 21#define _PCH_GBE_H_ 22 23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 24 25#include <linux/mii.h> 26#include <linux/delay.h> 27#include <linux/pci.h> 28#include <linux/netdevice.h> 29#include <linux/etherdevice.h> 30#include <linux/ethtool.h> 31#include <linux/vmalloc.h> 32#include <net/ip.h> 33#include <net/tcp.h> 34#include <net/udp.h> 35 36/** 37 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers 38 * @high Denotes the 1st to 4th byte from the initial of MAC address 39 * @low Denotes the 5th to 6th byte from the initial of MAC address 40 */ 41struct pch_gbe_regs_mac_adr { 42 u32 high; 43 u32 low; 44}; 45/** 46 * pch_udc_regs - Structure holding values of MAC registers 47 */ 48struct pch_gbe_regs { 49 u32 INT_ST; 50 u32 INT_EN; 51 u32 MODE; 52 u32 RESET; 53 u32 TCPIP_ACC; 54 u32 EX_LIST; 55 u32 INT_ST_HOLD; 56 u32 PHY_INT_CTRL; 57 u32 MAC_RX_EN; 58 u32 RX_FCTRL; 59 u32 PAUSE_REQ; 60 u32 RX_MODE; 61 u32 TX_MODE; 62 u32 RX_FIFO_ST; 63 u32 TX_FIFO_ST; 64 u32 TX_FID; 65 u32 TX_RESULT; 66 u32 PAUSE_PKT1; 67 u32 PAUSE_PKT2; 68 u32 PAUSE_PKT3; 69 u32 PAUSE_PKT4; 70 u32 PAUSE_PKT5; 71 u32 reserve[2]; 72 struct pch_gbe_regs_mac_adr mac_adr[16]; 73 u32 ADDR_MASK; 74 u32 MIIM; 75 u32 MAC_ADDR_LOAD; 76 u32 RGMII_ST; 77 u32 RGMII_CTRL; 78 u32 reserve3[3]; 79 u32 DMA_CTRL; 80 u32 reserve4[3]; 81 u32 RX_DSC_BASE; 82 u32 RX_DSC_SIZE; 83 u32 RX_DSC_HW_P; 84 u32 RX_DSC_HW_P_HLD; 85 u32 RX_DSC_SW_P; 86 u32 reserve5[3]; 87 u32 TX_DSC_BASE; 88 u32 TX_DSC_SIZE; 89 u32 TX_DSC_HW_P; 90 u32 TX_DSC_HW_P_HLD; 91 u32 TX_DSC_SW_P; 92 u32 reserve6[3]; 93 u32 RX_DMA_ST; 94 u32 TX_DMA_ST; 95 u32 reserve7[2]; 96 u32 WOL_ST; 97 u32 WOL_CTRL; 98 u32 WOL_ADDR_MASK; 99}; 100 101/* Interrupt Status */ 102/* Interrupt Status Hold */ 103/* Interrupt Enable */ 104#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */ 105#define PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */ 106#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */ 107#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */ 108#define PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */ 109#define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */ 110#define PCH_GBE_INT_TX_CMPLT 0x00000100 /* MAC Transmission Complete */ 111#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 /* DMA Transfer Complete */ 112#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */ 113#define PCH_GBE_INT_TX_DMA_ERR 0x00000800 /* Transmission DMA Error */ 114#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 /* Pause Transmission complete */ 115#define PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */ 116#define PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */ 117#define PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */ 118#define PCH_GBE_INT_TCPIP_ERR 0x10000000 /* TCP/IP Accelerator Error */ 119 120/* Mode */ 121#define PCH_GBE_MODE_MII_ETHER 0x00000000 /* GIGA Ethernet Mode [MII] */ 122#define PCH_GBE_MODE_GMII_ETHER 0x80000000 /* GIGA Ethernet Mode [GMII] */ 123#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 /* Duplex Mode [half duplex] */ 124#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */ 125#define PCH_GBE_MODE_FR_BST 0x04000000 /* Frame bursting is done */ 126 127/* Reset */ 128#define PCH_GBE_ALL_RST 0x80000000 /* All reset */ 129#define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */ 130#define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */ 131 132/* TCP/IP Accelerator Control */ 133#define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */ 134#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */ 135#define PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */ 136#define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */ 137 138/* MAC RX Enable */ 139#define PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */ 140 141/* RX Flow Control */ 142#define PCH_GBE_FL_CTRL_EN 0x80000000 /* Pause packet is enabled */ 143 144/* Pause Packet Request */ 145#define PCH_GBE_PS_PKT_RQ 0x80000000 /* Pause packet Request */ 146 147/* RX Mode */ 148#define PCH_GBE_ADD_FIL_EN 0x80000000 /* Address Filtering Enable */ 149/* Multicast Filtering Enable */ 150#define PCH_GBE_MLT_FIL_EN 0x40000000 151/* Receive Almost Empty Threshold */ 152#define PCH_GBE_RH_ALM_EMP_4 0x00000000 /* 4 words */ 153#define PCH_GBE_RH_ALM_EMP_8 0x00004000 /* 8 words */ 154#define PCH_GBE_RH_ALM_EMP_16 0x00008000 /* 16 words */ 155#define PCH_GBE_RH_ALM_EMP_32 0x0000C000 /* 32 words */ 156/* Receive Almost Full Threshold */ 157#define PCH_GBE_RH_ALM_FULL_4 0x00000000 /* 4 words */ 158#define PCH_GBE_RH_ALM_FULL_8 0x00001000 /* 8 words */ 159#define PCH_GBE_RH_ALM_FULL_16 0x00002000 /* 16 words */ 160#define PCH_GBE_RH_ALM_FULL_32 0x00003000 /* 32 words */ 161/* RX FIFO Read Triger Threshold */ 162#define PCH_GBE_RH_RD_TRG_4 0x00000000 /* 4 words */ 163#define PCH_GBE_RH_RD_TRG_8 0x00000200 /* 8 words */ 164#define PCH_GBE_RH_RD_TRG_16 0x00000400 /* 16 words */ 165#define PCH_GBE_RH_RD_TRG_32 0x00000600 /* 32 words */ 166#define PCH_GBE_RH_RD_TRG_64 0x00000800 /* 64 words */ 167#define PCH_GBE_RH_RD_TRG_128 0x00000A00 /* 128 words */ 168#define PCH_GBE_RH_RD_TRG_256 0x00000C00 /* 256 words */ 169#define PCH_GBE_RH_RD_TRG_512 0x00000E00 /* 512 words */ 170 171/* Receive Descriptor bit definitions */ 172#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400 173#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200 174#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100 175#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000C0 176#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080 177#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040 178#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020 179#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010 180#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008 181#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004 182#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002 183#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001 184#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200 185#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100 186#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080 187#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040 188#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020 189#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010 190#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008 191#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004 192#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002 193#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001 194 195/* Transmit Descriptor bit definitions */ 196#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008 197#define PCH_GBE_TXD_CTRL_ITAG 0x0004 198#define PCH_GBE_TXD_CTRL_ICRC 0x0002 199#define PCH_GBE_TXD_CTRL_APAD 0x0001 200#define PCH_GBE_TXD_WORDS_SHIFT 2 201#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000 202#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000 203#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800 204#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400 205#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200 206#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100 207#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080 208#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040 209#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020 210#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010 211#define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK 0x000F 212 213/* TX Mode */ 214#define PCH_GBE_TM_NO_RTRY 0x80000000 /* No Retransmission */ 215#define PCH_GBE_TM_LONG_PKT 0x40000000 /* Long Packt TX Enable */ 216#define PCH_GBE_TM_ST_AND_FD 0x20000000 /* Stare and Forward */ 217#define PCH_GBE_TM_SHORT_PKT 0x10000000 /* Short Packet TX Enable */ 218#define PCH_GBE_TM_LTCOL_RETX 0x08000000 /* Retransmission at Late Collision */ 219/* Frame Start Threshold */ 220#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 /* 4 words */ 221#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 /* 8 words */ 222#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 /* 16 words */ 223#define PCH_GBE_TM_TH_TX_STRT_32 0x0000C000 /* 32 words */ 224/* Transmit Almost Empty Threshold */ 225#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 /* 4 words */ 226#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 /* 8 words */ 227#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 /* 16 words */ 228#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 /* 32 words */ 229#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 /* 64 words */ 230#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 /* 128 words */ 231#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 /* 256 words */ 232#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 /* 512 words */ 233/* Transmit Almost Full Threshold */ 234#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 /* 4 words */ 235#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 /* 8 words */ 236#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 /* 16 words */ 237#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 /* 32 words */ 238 239/* RX FIFO Status */ 240#define PCH_GBE_RF_ALM_FULL 0x80000000 /* RX FIFO is almost full. */ 241#define PCH_GBE_RF_ALM_EMP 0x40000000 /* RX FIFO is almost empty. */ 242#define PCH_GBE_RF_RD_TRG 0x20000000 /* Become more than RH_RD_TRG. */ 243#define PCH_GBE_RF_STRWD 0x1FFE0000 /* The word count of RX FIFO. */ 244#define PCH_GBE_RF_RCVING 0x00010000 /* Stored in RX FIFO. */ 245 246/* MAC Address Mask */ 247#define PCH_GBE_BUSY 0x80000000 248 249/* MIIM */ 250#define PCH_GBE_MIIM_OPER_WRITE 0x04000000 251#define PCH_GBE_MIIM_OPER_READ 0x00000000 252#define PCH_GBE_MIIM_OPER_READY 0x04000000 253#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21 254#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16 255 256/* RGMII Status */ 257#define PCH_GBE_LINK_UP 0x80000008 258#define PCH_GBE_RXC_SPEED_MSK 0x00000006 259#define PCH_GBE_RXC_SPEED_2_5M 0x00000000 /* 2.5MHz */ 260#define PCH_GBE_RXC_SPEED_25M 0x00000002 /* 25MHz */ 261#define PCH_GBE_RXC_SPEED_125M 0x00000004 /* 100MHz */ 262#define PCH_GBE_DUPLEX_FULL 0x00000001 263 264/* RGMII Control */ 265#define PCH_GBE_CRS_SEL 0x00000010 266#define PCH_GBE_RGMII_RATE_125M 0x00000000 267#define PCH_GBE_RGMII_RATE_25M 0x00000008 268#define PCH_GBE_RGMII_RATE_2_5M 0x0000000C 269#define PCH_GBE_RGMII_MODE_GMII 0x00000000 270#define PCH_GBE_RGMII_MODE_RGMII 0x00000002 271#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000 272#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001 273 274/* DMA Control */ 275#define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */ 276#define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */ 277 278/* RX DMA STATUS */ 279#define PCH_GBE_IDLE_CHECK 0xFFFFFFFE 280 281/* Wake On LAN Status */ 282#define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */ 283#define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */ 284 285/* The Frame registered in Address Recognizer */ 286#define PCH_GBE_WLS_IND 0x00000002 287#define PCH_GBE_WLS_MP 0x00000001 /* Magic packet Address */ 288 289/* Wake On LAN Control */ 290#define PCH_GBE_WLC_WOL_MODE 0x00010000 291#define PCH_GBE_WLC_IGN_TLONG 0x00000100 292#define PCH_GBE_WLC_IGN_TSHRT 0x00000080 293#define PCH_GBE_WLC_IGN_OCTER 0x00000040 294#define PCH_GBE_WLC_IGN_NBLER 0x00000020 295#define PCH_GBE_WLC_IGN_CRCER 0x00000010 296#define PCH_GBE_WLC_BR 0x00000008 297#define PCH_GBE_WLC_MLT 0x00000004 298#define PCH_GBE_WLC_IND 0x00000002 299#define PCH_GBE_WLC_MP 0x00000001 300 301/* Wake On LAN Address Mask */ 302#define PCH_GBE_WLA_BUSY 0x80000000 303 304 305 306/* TX/RX descriptor defines */ 307#define PCH_GBE_MAX_TXD 4096 308#define PCH_GBE_DEFAULT_TXD 256 309#define PCH_GBE_MIN_TXD 8 310#define PCH_GBE_MAX_RXD 4096 311#define PCH_GBE_DEFAULT_RXD 256 312#define PCH_GBE_MIN_RXD 8 313 314/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 315#define PCH_GBE_TX_DESC_MULTIPLE 8 316#define PCH_GBE_RX_DESC_MULTIPLE 8 317 318/* Read/Write operation is done through MII Management IF */ 319#define PCH_GBE_HAL_MIIM_READ ((u32)0x00000000) 320#define PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000) 321 322/* flow control values */ 323#define PCH_GBE_FC_NONE 0 324#define PCH_GBE_FC_RX_PAUSE 1 325#define PCH_GBE_FC_TX_PAUSE 2 326#define PCH_GBE_FC_FULL 3 327#define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL 328 329 330struct pch_gbe_hw; 331/** 332 * struct pch_gbe_functions - HAL APi function pointer 333 * @get_bus_info: for pch_gbe_hal_get_bus_info 334 * @init_hw: for pch_gbe_hal_init_hw 335 * @read_phy_reg: for pch_gbe_hal_read_phy_reg 336 * @write_phy_reg: for pch_gbe_hal_write_phy_reg 337 * @reset_phy: for pch_gbe_hal_phy_hw_reset 338 * @sw_reset_phy: for pch_gbe_hal_phy_sw_reset 339 * @power_up_phy: for pch_gbe_hal_power_up_phy 340 * @power_down_phy: for pch_gbe_hal_power_down_phy 341 * @read_mac_addr: for pch_gbe_hal_read_mac_addr 342 */ 343struct pch_gbe_functions { 344 void (*get_bus_info) (struct pch_gbe_hw *); 345 s32 (*init_hw) (struct pch_gbe_hw *); 346 s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *); 347 s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16); 348 void (*reset_phy) (struct pch_gbe_hw *); 349 void (*sw_reset_phy) (struct pch_gbe_hw *); 350 void (*power_up_phy) (struct pch_gbe_hw *hw); 351 void (*power_down_phy) (struct pch_gbe_hw *hw); 352 s32 (*read_mac_addr) (struct pch_gbe_hw *); 353}; 354 355/** 356 * struct pch_gbe_mac_info - MAC information 357 * @addr[6]: Store the MAC address 358 * @fc: Mode of flow control 359 * @fc_autoneg: Auto negotiation enable for flow control setting 360 * @tx_fc_enable: Enable flag of Transmit flow control 361 * @max_frame_size: Max transmit frame size 362 * @min_frame_size: Min transmit frame size 363 * @autoneg: Auto negotiation enable 364 * @link_speed: Link speed 365 * @link_duplex: Link duplex 366 */ 367struct pch_gbe_mac_info { 368 u8 addr[6]; 369 u8 fc; 370 u8 fc_autoneg; 371 u8 tx_fc_enable; 372 u32 max_frame_size; 373 u32 min_frame_size; 374 u8 autoneg; 375 u16 link_speed; 376 u16 link_duplex; 377}; 378 379/** 380 * struct pch_gbe_phy_info - PHY information 381 * @addr: PHY address 382 * @id: PHY's identifier 383 * @revision: PHY's revision 384 * @reset_delay_us: HW reset delay time[us] 385 * @autoneg_advertised: Autoneg advertised 386 */ 387struct pch_gbe_phy_info { 388 u32 addr; 389 u32 id; 390 u32 revision; 391 u32 reset_delay_us; 392 u16 autoneg_advertised; 393}; 394 395/*! 396 * @ingroup Gigabit Ether driver Layer 397 * @struct pch_gbe_bus_info 398 * @brief Bus information 399 */ 400struct pch_gbe_bus_info { 401 u8 type; 402 u8 speed; 403 u8 width; 404}; 405 406/*! 407 * @ingroup Gigabit Ether driver Layer 408 * @struct pch_gbe_hw 409 * @brief Hardware information 410 */ 411struct pch_gbe_hw { 412 void *back; 413 414 struct pch_gbe_regs __iomem *reg; 415 spinlock_t miim_lock; 416 417 const struct pch_gbe_functions *func; 418 struct pch_gbe_mac_info mac; 419 struct pch_gbe_phy_info phy; 420 struct pch_gbe_bus_info bus; 421}; 422 423/** 424 * struct pch_gbe_rx_desc - Receive Descriptor 425 * @buffer_addr: RX Frame Buffer Address 426 * @tcp_ip_status: TCP/IP Accelerator Status 427 * @rx_words_eob: RX word count and Byte position 428 * @gbec_status: GMAC Status 429 * @dma_status: DMA Status 430 * @reserved1: Reserved 431 * @reserved2: Reserved 432 */ 433struct pch_gbe_rx_desc { 434 u32 buffer_addr; 435 u32 tcp_ip_status; 436 u16 rx_words_eob; 437 u16 gbec_status; 438 u8 dma_status; 439 u8 reserved1; 440 u16 reserved2; 441}; 442 443/** 444 * struct pch_gbe_tx_desc - Transmit Descriptor 445 * @buffer_addr: TX Frame Buffer Address 446 * @length: Data buffer length 447 * @reserved1: Reserved 448 * @tx_words_eob: TX word count and Byte position 449 * @tx_frame_ctrl: TX Frame Control 450 * @dma_status: DMA Status 451 * @reserved2: Reserved 452 * @gbec_status: GMAC Status 453 */ 454struct pch_gbe_tx_desc { 455 u32 buffer_addr; 456 u16 length; 457 u16 reserved1; 458 u16 tx_words_eob; 459 u16 tx_frame_ctrl; 460 u8 dma_status; 461 u8 reserved2; 462 u16 gbec_status; 463}; 464 465 466/** 467 * struct pch_gbe_buffer - Buffer information 468 * @skb: pointer to a socket buffer 469 * @dma: DMA address 470 * @time_stamp: time stamp 471 * @length: data size 472 */ 473struct pch_gbe_buffer { 474 struct sk_buff *skb; 475 dma_addr_t dma; 476 unsigned char *rx_buffer; 477 unsigned long time_stamp; 478 u16 length; 479 bool mapped; 480}; 481 482/** 483 * struct pch_gbe_tx_ring - tx ring information 484 * @tx_lock: spinlock structs 485 * @desc: pointer to the descriptor ring memory 486 * @dma: physical address of the descriptor ring 487 * @size: length of descriptor ring in bytes 488 * @count: number of descriptors in the ring 489 * @next_to_use: next descriptor to associate a buffer with 490 * @next_to_clean: next descriptor to check for DD status bit 491 * @buffer_info: array of buffer information structs 492 */ 493struct pch_gbe_tx_ring { 494 spinlock_t tx_lock; 495 struct pch_gbe_tx_desc *desc; 496 dma_addr_t dma; 497 unsigned int size; 498 unsigned int count; 499 unsigned int next_to_use; 500 unsigned int next_to_clean; 501 struct pch_gbe_buffer *buffer_info; 502}; 503 504/** 505 * struct pch_gbe_rx_ring - rx ring information 506 * @desc: pointer to the descriptor ring memory 507 * @dma: physical address of the descriptor ring 508 * @size: length of descriptor ring in bytes 509 * @count: number of descriptors in the ring 510 * @next_to_use: next descriptor to associate a buffer with 511 * @next_to_clean: next descriptor to check for DD status bit 512 * @buffer_info: array of buffer information structs 513 */ 514struct pch_gbe_rx_ring { 515 struct pch_gbe_rx_desc *desc; 516 dma_addr_t dma; 517 unsigned char *rx_buff_pool; 518 dma_addr_t rx_buff_pool_logic; 519 unsigned int rx_buff_pool_size; 520 unsigned int size; 521 unsigned int count; 522 unsigned int next_to_use; 523 unsigned int next_to_clean; 524 struct pch_gbe_buffer *buffer_info; 525}; 526 527/** 528 * struct pch_gbe_hw_stats - Statistics counters collected by the MAC 529 * @rx_packets: total packets received 530 * @tx_packets: total packets transmitted 531 * @rx_bytes: total bytes received 532 * @tx_bytes: total bytes transmitted 533 * @rx_errors: bad packets received 534 * @tx_errors: packet transmit problems 535 * @rx_dropped: no space in Linux buffers 536 * @tx_dropped: no space available in Linux 537 * @multicast: multicast packets received 538 * @collisions: collisions 539 * @rx_crc_errors: received packet with crc error 540 * @rx_frame_errors: received frame alignment error 541 * @rx_alloc_buff_failed: allocate failure of a receive buffer 542 * @tx_length_errors: transmit length error 543 * @tx_aborted_errors: transmit aborted error 544 * @tx_carrier_errors: transmit carrier error 545 * @tx_timeout_count: Number of transmit timeout 546 * @tx_restart_count: Number of transmit restert 547 * @intr_rx_dsc_empty_count: Interrupt count of receive descriptor empty 548 * @intr_rx_frame_err_count: Interrupt count of receive frame error 549 * @intr_rx_fifo_err_count: Interrupt count of receive FIFO error 550 * @intr_rx_dma_err_count: Interrupt count of receive DMA error 551 * @intr_tx_fifo_err_count: Interrupt count of transmit FIFO error 552 * @intr_tx_dma_err_count: Interrupt count of transmit DMA error 553 * @intr_tcpip_err_count: Interrupt count of TCP/IP Accelerator 554 */ 555struct pch_gbe_hw_stats { 556 u32 rx_packets; 557 u32 tx_packets; 558 u32 rx_bytes; 559 u32 tx_bytes; 560 u32 rx_errors; 561 u32 tx_errors; 562 u32 rx_dropped; 563 u32 tx_dropped; 564 u32 multicast; 565 u32 collisions; 566 u32 rx_crc_errors; 567 u32 rx_frame_errors; 568 u32 rx_alloc_buff_failed; 569 u32 tx_length_errors; 570 u32 tx_aborted_errors; 571 u32 tx_carrier_errors; 572 u32 tx_timeout_count; 573 u32 tx_restart_count; 574 u32 intr_rx_dsc_empty_count; 575 u32 intr_rx_frame_err_count; 576 u32 intr_rx_fifo_err_count; 577 u32 intr_rx_dma_err_count; 578 u32 intr_tx_fifo_err_count; 579 u32 intr_tx_dma_err_count; 580 u32 intr_tcpip_err_count; 581}; 582 583/** 584 * struct pch_gbe_privdata - PCI Device ID driver data 585 * @phy_tx_clk_delay: Bool, configure the PHY TX delay in software 586 * @phy_disable_hibernate: Bool, disable PHY hibernation 587 * @platform_init: Platform initialization callback, called from 588 * probe, prior to PHY initialization. 589 */ 590struct pch_gbe_privdata { 591 bool phy_tx_clk_delay; 592 bool phy_disable_hibernate; 593 int (*platform_init)(struct pci_dev *pdev); 594}; 595 596/** 597 * struct pch_gbe_adapter - board specific private data structure 598 * @stats_lock: Spinlock structure for status 599 * @ethtool_lock: Spinlock structure for ethtool 600 * @irq_sem: Semaphore for interrupt 601 * @netdev: Pointer of network device structure 602 * @pdev: Pointer of pci device structure 603 * @polling_netdev: Pointer of polling network device structure 604 * @napi: NAPI structure 605 * @hw: Pointer of hardware structure 606 * @stats: Hardware status 607 * @reset_task: Reset task 608 * @mii: MII information structure 609 * @watchdog_timer: Watchdog timer list 610 * @wake_up_evt: Wake up event 611 * @config_space: Configuration space 612 * @msg_enable: Driver message level 613 * @led_status: LED status 614 * @tx_ring: Pointer of Tx descriptor ring structure 615 * @rx_ring: Pointer of Rx descriptor ring structure 616 * @rx_buffer_len: Receive buffer length 617 * @tx_queue_len: Transmit queue length 618 * @have_msi: PCI MSI mode flag 619 * @pch_gbe_privdata: PCI Device ID driver_data 620 */ 621 622struct pch_gbe_adapter { 623 spinlock_t stats_lock; 624 spinlock_t ethtool_lock; 625 atomic_t irq_sem; 626 struct net_device *netdev; 627 struct pci_dev *pdev; 628 struct net_device *polling_netdev; 629 struct napi_struct napi; 630 struct pch_gbe_hw hw; 631 struct pch_gbe_hw_stats stats; 632 struct work_struct reset_task; 633 struct mii_if_info mii; 634 struct timer_list watchdog_timer; 635 u32 wake_up_evt; 636 u32 *config_space; 637 unsigned long led_status; 638 struct pch_gbe_tx_ring *tx_ring; 639 struct pch_gbe_rx_ring *rx_ring; 640 unsigned long rx_buffer_len; 641 unsigned long tx_queue_len; 642 bool have_msi; 643 bool rx_stop_flag; 644 int hwts_tx_en; 645 int hwts_rx_en; 646 struct pci_dev *ptp_pdev; 647 struct pch_gbe_privdata *pdata; 648}; 649 650#define pch_gbe_hw_to_adapter(hw) container_of(hw, struct pch_gbe_adapter, hw) 651 652extern const char pch_driver_version[]; 653 654/* pch_gbe_main.c */ 655int pch_gbe_up(struct pch_gbe_adapter *adapter); 656void pch_gbe_down(struct pch_gbe_adapter *adapter); 657void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter); 658void pch_gbe_reset(struct pch_gbe_adapter *adapter); 659int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter, 660 struct pch_gbe_tx_ring *txdr); 661int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter, 662 struct pch_gbe_rx_ring *rxdr); 663void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter, 664 struct pch_gbe_tx_ring *tx_ring); 665void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter, 666 struct pch_gbe_rx_ring *rx_ring); 667void pch_gbe_update_stats(struct pch_gbe_adapter *adapter); 668u32 pch_ch_control_read(struct pci_dev *pdev); 669void pch_ch_control_write(struct pci_dev *pdev, u32 val); 670u32 pch_ch_event_read(struct pci_dev *pdev); 671void pch_ch_event_write(struct pci_dev *pdev, u32 val); 672u32 pch_src_uuid_lo_read(struct pci_dev *pdev); 673u32 pch_src_uuid_hi_read(struct pci_dev *pdev); 674u64 pch_rx_snap_read(struct pci_dev *pdev); 675u64 pch_tx_snap_read(struct pci_dev *pdev); 676int pch_set_station_address(u8 *addr, struct pci_dev *pdev); 677 678/* pch_gbe_param.c */ 679void pch_gbe_check_options(struct pch_gbe_adapter *adapter); 680 681/* pch_gbe_ethtool.c */ 682void pch_gbe_set_ethtool_ops(struct net_device *netdev); 683 684/* pch_gbe_mac.c */ 685s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw); 686s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw); 687u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, 688 u16 data); 689#endif /* _PCH_GBE_H_ */ 690