1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _HW_H_ 19#define _HW_H_ 20 21#include "targaddrs.h" 22 23/* QCA988X 1.0 definitions (unsupported) */ 24#define QCA988X_HW_1_0_CHIP_ID_REV 0x0 25 26/* QCA988X 2.0 definitions */ 27#define QCA988X_HW_2_0_VERSION 0x4100016c 28#define QCA988X_HW_2_0_CHIP_ID_REV 0x2 29#define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0" 30#define QCA988X_HW_2_0_FW_FILE "firmware.bin" 31#define QCA988X_HW_2_0_FW_3_FILE "firmware-3.bin" 32#define QCA988X_HW_2_0_OTP_FILE "otp.bin" 33#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 34#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 35 36#define ATH10K_FW_API2_FILE "firmware-2.bin" 37#define ATH10K_FW_API3_FILE "firmware-3.bin" 38 39#define ATH10K_FW_UTF_FILE "utf.bin" 40 41/* includes also the null byte */ 42#define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 43 44#define REG_DUMP_COUNT_QCA988X 60 45 46struct ath10k_fw_ie { 47 __le32 id; 48 __le32 len; 49 u8 data[0]; 50}; 51 52enum ath10k_fw_ie_type { 53 ATH10K_FW_IE_FW_VERSION = 0, 54 ATH10K_FW_IE_TIMESTAMP = 1, 55 ATH10K_FW_IE_FEATURES = 2, 56 ATH10K_FW_IE_FW_IMAGE = 3, 57 ATH10K_FW_IE_OTP_IMAGE = 4, 58}; 59 60/* Known pecularities: 61 * - current FW doesn't support raw rx mode (last tested v599) 62 * - current FW dumps upon raw tx mode (last tested v599) 63 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 64 * - raw have FCS, nwifi doesn't 65 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 66 * param, llc/snap) are aligned to 4byte boundaries each */ 67enum ath10k_hw_txrx_mode { 68 ATH10K_HW_TXRX_RAW = 0, 69 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 70 ATH10K_HW_TXRX_ETHERNET = 2, 71 72 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 73 ATH10K_HW_TXRX_MGMT = 3, 74}; 75 76enum ath10k_mcast2ucast_mode { 77 ATH10K_MCAST2UCAST_DISABLED = 0, 78 ATH10K_MCAST2UCAST_ENABLED = 1, 79}; 80 81/* Target specific defines for MAIN firmware */ 82#define TARGET_NUM_VDEVS 8 83#define TARGET_NUM_PEER_AST 2 84#define TARGET_NUM_WDS_ENTRIES 32 85#define TARGET_DMA_BURST_SIZE 0 86#define TARGET_MAC_AGGR_DELIM 0 87#define TARGET_AST_SKID_LIMIT 16 88#define TARGET_NUM_PEERS 16 89#define TARGET_NUM_OFFLOAD_PEERS 0 90#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 91#define TARGET_NUM_PEER_KEYS 2 92#define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS))) 93#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 94#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 95#define TARGET_RX_TIMEOUT_LO_PRI 100 96#define TARGET_RX_TIMEOUT_HI_PRI 40 97 98/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and 99 * avoid a very expensive re-alignment in mac80211. */ 100#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 101 102#define TARGET_SCAN_MAX_PENDING_REQS 4 103#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 104#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 105#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 106#define TARGET_GTK_OFFLOAD_MAX_VDEV 3 107#define TARGET_NUM_MCAST_GROUPS 0 108#define TARGET_NUM_MCAST_TABLE_ELEMS 0 109#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 110#define TARGET_TX_DBG_LOG_SIZE 1024 111#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 112#define TARGET_VOW_CONFIG 0 113#define TARGET_NUM_MSDU_DESC (1024 + 400) 114#define TARGET_MAX_FRAG_ENTRIES 0 115 116/* Target specific defines for 10.X firmware */ 117#define TARGET_10X_NUM_VDEVS 16 118#define TARGET_10X_NUM_PEER_AST 2 119#define TARGET_10X_NUM_WDS_ENTRIES 32 120#define TARGET_10X_DMA_BURST_SIZE 0 121#define TARGET_10X_MAC_AGGR_DELIM 0 122#define TARGET_10X_AST_SKID_LIMIT 16 123#define TARGET_10X_NUM_PEERS (128 + (TARGET_10X_NUM_VDEVS)) 124#define TARGET_10X_NUM_PEERS_MAX 128 125#define TARGET_10X_NUM_OFFLOAD_PEERS 0 126#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 127#define TARGET_10X_NUM_PEER_KEYS 2 128#define TARGET_10X_NUM_TIDS 256 129#define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 130#define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 131#define TARGET_10X_RX_TIMEOUT_LO_PRI 100 132#define TARGET_10X_RX_TIMEOUT_HI_PRI 40 133#define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 134#define TARGET_10X_SCAN_MAX_PENDING_REQS 4 135#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 136#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 137#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 138#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 139#define TARGET_10X_NUM_MCAST_GROUPS 0 140#define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 141#define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 142#define TARGET_10X_TX_DBG_LOG_SIZE 1024 143#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 144#define TARGET_10X_VOW_CONFIG 0 145#define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 146#define TARGET_10X_MAX_FRAG_ENTRIES 0 147 148/* Number of Copy Engines supported */ 149#define CE_COUNT 8 150 151/* 152 * Total number of PCIe MSI interrupts requested for all interrupt sources. 153 * PCIe standard forces this to be a power of 2. 154 * Some Host OS's limit MSI requests that can be granted to 8 155 * so for now we abide by this limit and avoid requesting more 156 * than that. 157 */ 158#define MSI_NUM_REQUEST_LOG2 3 159#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) 160 161/* 162 * Granted MSIs are assigned as follows: 163 * Firmware uses the first 164 * Remaining MSIs, if any, are used by Copy Engines 165 * This mapping is known to both Target firmware and Host software. 166 * It may be changed as long as Host and Target are kept in sync. 167 */ 168/* MSI for firmware (errors, etc.) */ 169#define MSI_ASSIGN_FW 0 170 171/* MSIs for Copy Engines */ 172#define MSI_ASSIGN_CE_INITIAL 1 173#define MSI_ASSIGN_CE_MAX 7 174 175/* as of IP3.7.1 */ 176#define RTC_STATE_V_ON 3 177 178#define RTC_STATE_COLD_RESET_MASK 0x00000400 179#define RTC_STATE_V_LSB 0 180#define RTC_STATE_V_MASK 0x00000007 181#define RTC_STATE_ADDRESS 0x0000 182#define PCIE_SOC_WAKE_V_MASK 0x00000001 183#define PCIE_SOC_WAKE_ADDRESS 0x0004 184#define PCIE_SOC_WAKE_RESET 0x00000000 185#define SOC_GLOBAL_RESET_ADDRESS 0x0008 186 187#define RTC_SOC_BASE_ADDRESS 0x00004000 188#define RTC_WMAC_BASE_ADDRESS 0x00005000 189#define MAC_COEX_BASE_ADDRESS 0x00006000 190#define BT_COEX_BASE_ADDRESS 0x00007000 191#define SOC_PCIE_BASE_ADDRESS 0x00008000 192#define SOC_CORE_BASE_ADDRESS 0x00009000 193#define WLAN_UART_BASE_ADDRESS 0x0000c000 194#define WLAN_SI_BASE_ADDRESS 0x00010000 195#define WLAN_GPIO_BASE_ADDRESS 0x00014000 196#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 197#define WLAN_MAC_BASE_ADDRESS 0x00020000 198#define EFUSE_BASE_ADDRESS 0x00030000 199#define FPGA_REG_BASE_ADDRESS 0x00039000 200#define WLAN_UART2_BASE_ADDRESS 0x00054c00 201#define CE_WRAPPER_BASE_ADDRESS 0x00057000 202#define CE0_BASE_ADDRESS 0x00057400 203#define CE1_BASE_ADDRESS 0x00057800 204#define CE2_BASE_ADDRESS 0x00057c00 205#define CE3_BASE_ADDRESS 0x00058000 206#define CE4_BASE_ADDRESS 0x00058400 207#define CE5_BASE_ADDRESS 0x00058800 208#define CE6_BASE_ADDRESS 0x00058c00 209#define CE7_BASE_ADDRESS 0x00059000 210#define DBI_BASE_ADDRESS 0x00060000 211#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 212#define PCIE_LOCAL_BASE_ADDRESS 0x00080000 213 214#define SOC_RESET_CONTROL_ADDRESS 0x00000000 215#define SOC_RESET_CONTROL_OFFSET 0x00000000 216#define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 217#define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 218#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 219#define SOC_CPU_CLOCK_OFFSET 0x00000020 220#define SOC_CPU_CLOCK_STANDARD_LSB 0 221#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 222#define SOC_CLOCK_CONTROL_OFFSET 0x00000028 223#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 224#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 225#define SOC_LPO_CAL_OFFSET 0x000000e0 226#define SOC_LPO_CAL_ENABLE_LSB 20 227#define SOC_LPO_CAL_ENABLE_MASK 0x00100000 228#define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 229#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 230 231#define SOC_CHIP_ID_ADDRESS 0x000000ec 232#define SOC_CHIP_ID_REV_LSB 8 233#define SOC_CHIP_ID_REV_MASK 0x00000f00 234 235#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 236#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 237#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 238#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 239 240#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 241#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 242#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 243#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 244#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 245#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 246#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 247#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 248 249#define CLOCK_GPIO_OFFSET 0xffffffff 250#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 251#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 252 253#define SI_CONFIG_OFFSET 0x00000000 254#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 255#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 256#define SI_CONFIG_I2C_LSB 16 257#define SI_CONFIG_I2C_MASK 0x00010000 258#define SI_CONFIG_POS_SAMPLE_LSB 7 259#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 260#define SI_CONFIG_INACTIVE_DATA_LSB 5 261#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 262#define SI_CONFIG_INACTIVE_CLK_LSB 4 263#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 264#define SI_CONFIG_DIVIDER_LSB 0 265#define SI_CONFIG_DIVIDER_MASK 0x0000000f 266#define SI_CS_OFFSET 0x00000004 267#define SI_CS_DONE_ERR_MASK 0x00000400 268#define SI_CS_DONE_INT_MASK 0x00000200 269#define SI_CS_START_LSB 8 270#define SI_CS_START_MASK 0x00000100 271#define SI_CS_RX_CNT_LSB 4 272#define SI_CS_RX_CNT_MASK 0x000000f0 273#define SI_CS_TX_CNT_LSB 0 274#define SI_CS_TX_CNT_MASK 0x0000000f 275 276#define SI_TX_DATA0_OFFSET 0x00000008 277#define SI_TX_DATA1_OFFSET 0x0000000c 278#define SI_RX_DATA0_OFFSET 0x00000010 279#define SI_RX_DATA1_OFFSET 0x00000014 280 281#define CORE_CTRL_CPU_INTR_MASK 0x00002000 282#define CORE_CTRL_ADDRESS 0x0000 283#define PCIE_INTR_ENABLE_ADDRESS 0x0008 284#define PCIE_INTR_CAUSE_ADDRESS 0x000c 285#define PCIE_INTR_CLR_ADDRESS 0x0014 286#define SCRATCH_3_ADDRESS 0x0030 287#define CPU_INTR_ADDRESS 0x0010 288 289/* Firmware indications to the Host via SCRATCH_3 register. */ 290#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) 291#define FW_IND_EVENT_PENDING 1 292#define FW_IND_INITIALIZED 2 293 294/* HOST_REG interrupt from firmware */ 295#define PCIE_INTR_FIRMWARE_MASK 0x00000400 296#define PCIE_INTR_CE_MASK_ALL 0x0007f800 297 298#define DRAM_BASE_ADDRESS 0x00400000 299 300#define MISSING 0 301 302#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 303#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 304#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 305#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 306#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 307#define RESET_CONTROL_MBOX_RST_MASK MISSING 308#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 309#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 310#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 311#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 312#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 313#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 314#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 315#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 316#define LOCAL_SCRATCH_OFFSET 0x18 317#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 318#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 319#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 320#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 321#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 322#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 323#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 324#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 325#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 326#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 327#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 328#define MBOX_BASE_ADDRESS MISSING 329#define INT_STATUS_ENABLE_ERROR_LSB MISSING 330#define INT_STATUS_ENABLE_ERROR_MASK MISSING 331#define INT_STATUS_ENABLE_CPU_LSB MISSING 332#define INT_STATUS_ENABLE_CPU_MASK MISSING 333#define INT_STATUS_ENABLE_COUNTER_LSB MISSING 334#define INT_STATUS_ENABLE_COUNTER_MASK MISSING 335#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 336#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 337#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 338#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 339#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 340#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 341#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 342#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 343#define INT_STATUS_ENABLE_ADDRESS MISSING 344#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 345#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 346#define HOST_INT_STATUS_ADDRESS MISSING 347#define CPU_INT_STATUS_ADDRESS MISSING 348#define ERROR_INT_STATUS_ADDRESS MISSING 349#define ERROR_INT_STATUS_WAKEUP_MASK MISSING 350#define ERROR_INT_STATUS_WAKEUP_LSB MISSING 351#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 352#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 353#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 354#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 355#define COUNT_DEC_ADDRESS MISSING 356#define HOST_INT_STATUS_CPU_MASK MISSING 357#define HOST_INT_STATUS_CPU_LSB MISSING 358#define HOST_INT_STATUS_ERROR_MASK MISSING 359#define HOST_INT_STATUS_ERROR_LSB MISSING 360#define HOST_INT_STATUS_COUNTER_MASK MISSING 361#define HOST_INT_STATUS_COUNTER_LSB MISSING 362#define RX_LOOKAHEAD_VALID_ADDRESS MISSING 363#define WINDOW_DATA_ADDRESS MISSING 364#define WINDOW_READ_ADDR_ADDRESS MISSING 365#define WINDOW_WRITE_ADDR_ADDRESS MISSING 366 367#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 368 369#endif /* _HW_H_ */ 370