15e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* 25e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Copyright (c) 2005-2011 Atheros Communications Inc. 35e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 45e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * 55e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Permission to use, copy, modify, and/or distribute this software for any 65e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * purpose with or without fee is hereby granted, provided that the above 75e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * copyright notice and this permission notice appear in all copies. 85e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * 95e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 105e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 115e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 125e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 135e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 145e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 155e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 165e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo */ 175e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 185e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#ifndef _HW_H_ 195e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define _HW_H_ 205e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 215e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#include "targaddrs.h" 225e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 23e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo/* QCA988X 1.0 definitions (unsupported) */ 24e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo#define QCA988X_HW_1_0_CHIP_ID_REV 0x0 25e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo 265e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* QCA988X 2.0 definitions */ 275e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_VERSION 0x4100016c 28e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo#define QCA988X_HW_2_0_CHIP_ID_REV 0x2 295e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0" 305e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_FW_FILE "firmware.bin" 3124c88f7807fb7c723690474d0a5d3441468185d9Michal Kazior#define QCA988X_HW_2_0_FW_3_FILE "firmware-3.bin" 325e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_OTP_FILE "otp.bin" 335e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 345e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 355e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 361a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo#define ATH10K_FW_API2_FILE "firmware-2.bin" 3724c88f7807fb7c723690474d0a5d3441468185d9Michal Kazior#define ATH10K_FW_API3_FILE "firmware-3.bin" 381a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo 3943d2a30fa80166243498fc6b8c841828ce52fcc1Kalle Valo#define ATH10K_FW_UTF_FILE "utf.bin" 4043d2a30fa80166243498fc6b8c841828ce52fcc1Kalle Valo 411a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo/* includes also the null byte */ 421a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo#define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 431a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo 44384914b2e5566dfce25f3f38d992708a9ef6f51bBen Greear#define REG_DUMP_COUNT_QCA988X 60 45384914b2e5566dfce25f3f38d992708a9ef6f51bBen Greear 461a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valostruct ath10k_fw_ie { 471a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo __le32 id; 481a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo __le32 len; 491a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo u8 data[0]; 501a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo}; 511a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo 521a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valoenum ath10k_fw_ie_type { 531a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo ATH10K_FW_IE_FW_VERSION = 0, 541a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo ATH10K_FW_IE_TIMESTAMP = 1, 551a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo ATH10K_FW_IE_FEATURES = 2, 561a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo ATH10K_FW_IE_FW_IMAGE = 3, 571a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo ATH10K_FW_IE_OTP_IMAGE = 4, 581a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo}; 591a222435a1b0ed2f87f4752abdf03065b574dfacKalle Valo 605e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* Known pecularities: 615e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - current FW doesn't support raw rx mode (last tested v599) 625e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - current FW dumps upon raw tx mode (last tested v599) 635e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 645e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - raw have FCS, nwifi doesn't 655e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 665e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * param, llc/snap) are aligned to 4byte boundaries each */ 675e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valoenum ath10k_hw_txrx_mode { 685e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_HW_TXRX_RAW = 0, 695e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_HW_TXRX_NATIVE_WIFI = 1, 705e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_HW_TXRX_ETHERNET = 2, 71961d4c38961a0f61e43edbb1fb579f28475a88bdMichal Kazior 72961d4c38961a0f61e43edbb1fb579f28475a88bdMichal Kazior /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 73961d4c38961a0f61e43edbb1fb579f28475a88bdMichal Kazior ATH10K_HW_TXRX_MGMT = 3, 745e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo}; 755e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 765e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valoenum ath10k_mcast2ucast_mode { 775e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_MCAST2UCAST_DISABLED = 0, 785e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_MCAST2UCAST_ENABLED = 1, 795e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo}; 805e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 81ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski/* Target specific defines for MAIN firmware */ 825e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_VDEVS 8 835e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_PEER_AST 2 845e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_WDS_ENTRIES 32 855e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_DMA_BURST_SIZE 0 865e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_MAC_AGGR_DELIM 0 875e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_AST_SKID_LIMIT 16 885e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_PEERS 16 895e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_OFFLOAD_PEERS 0 905e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 915e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_PEER_KEYS 2 925e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS))) 935e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 945e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 955e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_TIMEOUT_LO_PRI 100 965e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_TIMEOUT_HI_PRI 40 974d316c79a5dcc13dea8110f0fcf295a17b4b625bMichal Kazior 984d316c79a5dcc13dea8110f0fcf295a17b4b625bMichal Kazior/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and 994d316c79a5dcc13dea8110f0fcf295a17b4b625bMichal Kazior * avoid a very expensive re-alignment in mac80211. */ 1004d316c79a5dcc13dea8110f0fcf295a17b4b625bMichal Kazior#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 1014d316c79a5dcc13dea8110f0fcf295a17b4b625bMichal Kazior 1025e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_SCAN_MAX_PENDING_REQS 4 1035e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 1045e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 1055e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 1065e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_GTK_OFFLOAD_MAX_VDEV 3 1075e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_MCAST_GROUPS 0 1085e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_MCAST_TABLE_ELEMS 0 1095e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 1105e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_TX_DBG_LOG_SIZE 1024 1115e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 1125e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_VOW_CONFIG 0 1135e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_MSDU_DESC (1024 + 400) 1145e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_MAX_FRAG_ENTRIES 0 1155e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 116ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski/* Target specific defines for 10.X firmware */ 117ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_VDEVS 16 118ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_PEER_AST 2 119ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_WDS_ENTRIES 32 120ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_DMA_BURST_SIZE 0 121ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_MAC_AGGR_DELIM 0 122ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_AST_SKID_LIMIT 16 123ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_PEERS (128 + (TARGET_10X_NUM_VDEVS)) 1240e759f363e9f2f1b1a7a640b15ca613e5e27dfc0Bartosz Markowski#define TARGET_10X_NUM_PEERS_MAX 128 125ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_OFFLOAD_PEERS 0 126ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 127ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_PEER_KEYS 2 128ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_TIDS 256 129ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 130ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 131ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_RX_TIMEOUT_LO_PRI 100 132ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_RX_TIMEOUT_HI_PRI 40 1330d1a28f241e917d199ad72644edd0d6bb6726577Michal Kazior#define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 134ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_SCAN_MAX_PENDING_REQS 4 135ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 136ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 137ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 138ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 139ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_MCAST_GROUPS 0 140ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 141ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 142ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_TX_DBG_LOG_SIZE 1024 143ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 144ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_VOW_CONFIG 0 145ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 146ec6a73f00eba1cfca99599bf337ee3c66f89d735Bartosz Markowski#define TARGET_10X_MAX_FRAG_ENTRIES 0 1475e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1485e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* Number of Copy Engines supported */ 1495e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE_COUNT 8 1505e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1515e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* 1525e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Total number of PCIe MSI interrupts requested for all interrupt sources. 1535e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * PCIe standard forces this to be a power of 2. 1545e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Some Host OS's limit MSI requests that can be granted to 8 1555e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * so for now we abide by this limit and avoid requesting more 1565e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * than that. 1575e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo */ 1585e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_NUM_REQUEST_LOG2 3 1595e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) 1605e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1615e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* 1625e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Granted MSIs are assigned as follows: 1635e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Firmware uses the first 1645e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Remaining MSIs, if any, are used by Copy Engines 1655e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * This mapping is known to both Target firmware and Host software. 1665e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * It may be changed as long as Host and Target are kept in sync. 1675e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo */ 1685e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* MSI for firmware (errors, etc.) */ 1695e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_ASSIGN_FW 0 1705e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1715e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* MSIs for Copy Engines */ 1725e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_ASSIGN_CE_INITIAL 1 1735e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_ASSIGN_CE_MAX 7 1745e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1755e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* as of IP3.7.1 */ 1765e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_ON 3 1775e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1785e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_COLD_RESET_MASK 0x00000400 1795e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_LSB 0 1805e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_MASK 0x00000007 1815e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_ADDRESS 0x0000 1825e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_SOC_WAKE_V_MASK 0x00000001 1835e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_SOC_WAKE_ADDRESS 0x0004 1845e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_SOC_WAKE_RESET 0x00000000 1855e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_GLOBAL_RESET_ADDRESS 0x0008 1865e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1875e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_SOC_BASE_ADDRESS 0x00004000 1885e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_WMAC_BASE_ADDRESS 0x00005000 1895e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MAC_COEX_BASE_ADDRESS 0x00006000 1905e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define BT_COEX_BASE_ADDRESS 0x00007000 1915e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_PCIE_BASE_ADDRESS 0x00008000 1925e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CORE_BASE_ADDRESS 0x00009000 1935e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_UART_BASE_ADDRESS 0x0000c000 1945e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SI_BASE_ADDRESS 0x00010000 1955e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_BASE_ADDRESS 0x00014000 1965e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 1975e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_MAC_BASE_ADDRESS 0x00020000 1985e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define EFUSE_BASE_ADDRESS 0x00030000 1995e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FPGA_REG_BASE_ADDRESS 0x00039000 2005e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_UART2_BASE_ADDRESS 0x00054c00 2015e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE_WRAPPER_BASE_ADDRESS 0x00057000 2025e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE0_BASE_ADDRESS 0x00057400 2035e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE1_BASE_ADDRESS 0x00057800 2045e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE2_BASE_ADDRESS 0x00057c00 2055e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE3_BASE_ADDRESS 0x00058000 2065e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE4_BASE_ADDRESS 0x00058400 2075e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE5_BASE_ADDRESS 0x00058800 2085e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE6_BASE_ADDRESS 0x00058c00 2095e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE7_BASE_ADDRESS 0x00059000 2105e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define DBI_BASE_ADDRESS 0x00060000 2115e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 2125e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_LOCAL_BASE_ADDRESS 0x00080000 2135e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 214fc36e3ffcdd0ef214008d459bf8d8bff159ce16fMichal Kazior#define SOC_RESET_CONTROL_ADDRESS 0x00000000 2155e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_RESET_CONTROL_OFFSET 0x00000000 2165e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 217fc36e3ffcdd0ef214008d459bf8d8bff159ce16fMichal Kazior#define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 218fc36e3ffcdd0ef214008d459bf8d8bff159ce16fMichal Kazior#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 2195e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CPU_CLOCK_OFFSET 0x00000020 2205e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CPU_CLOCK_STANDARD_LSB 0 2215e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 2225e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CLOCK_CONTROL_OFFSET 0x00000028 2235e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 2245e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 2255e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_LPO_CAL_OFFSET 0x000000e0 2265e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_LPO_CAL_ENABLE_LSB 20 2275e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_LPO_CAL_ENABLE_MASK 0x00100000 228fc36e3ffcdd0ef214008d459bf8d8bff159ce16fMichal Kazior#define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 229fc36e3ffcdd0ef214008d459bf8d8bff159ce16fMichal Kazior#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 2305e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 231e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo#define SOC_CHIP_ID_ADDRESS 0x000000ec 232e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo#define SOC_CHIP_ID_REV_LSB 8 233e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo#define SOC_CHIP_ID_REV_MASK 0x00000f00 234e01ae68c5d8889588db6b7fcf3e3d7821a3365fbKalle Valo 2355e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 2365e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 2375e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 2385e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 2395e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2405e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 2415e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 2425e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 2435e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 2445e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 2455e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 2465e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 2475e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 2485e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2495e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_GPIO_OFFSET 0xffffffff 2505e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 2515e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 2525e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2535e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_OFFSET 0x00000000 2545e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 2555e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 2565e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_I2C_LSB 16 2575e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_I2C_MASK 0x00010000 2585e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_POS_SAMPLE_LSB 7 2595e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 2605e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_DATA_LSB 5 2615e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 2625e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_CLK_LSB 4 2635e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 2645e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_DIVIDER_LSB 0 2655e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_DIVIDER_MASK 0x0000000f 2665e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_OFFSET 0x00000004 2675e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_DONE_ERR_MASK 0x00000400 2685e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_DONE_INT_MASK 0x00000200 2695e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_START_LSB 8 2705e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_START_MASK 0x00000100 2715e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_RX_CNT_LSB 4 2725e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_RX_CNT_MASK 0x000000f0 2735e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_TX_CNT_LSB 0 2745e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_TX_CNT_MASK 0x0000000f 2755e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2765e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_TX_DATA0_OFFSET 0x00000008 2775e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_TX_DATA1_OFFSET 0x0000000c 2785e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_RX_DATA0_OFFSET 0x00000010 2795e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_RX_DATA1_OFFSET 0x00000014 2805e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2815e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CORE_CTRL_CPU_INTR_MASK 0x00002000 2825e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CORE_CTRL_ADDRESS 0x0000 2835e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_ENABLE_ADDRESS 0x0008 284e539887b1521ed4aefce7387bc3f33814b11442dMichal Kazior#define PCIE_INTR_CAUSE_ADDRESS 0x000c 2855e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_CLR_ADDRESS 0x0014 2865e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SCRATCH_3_ADDRESS 0x0030 287fc36e3ffcdd0ef214008d459bf8d8bff159ce16fMichal Kazior#define CPU_INTR_ADDRESS 0x0010 2885e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2895e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* Firmware indications to the Host via SCRATCH_3 register. */ 2905e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) 2915e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FW_IND_EVENT_PENDING 1 2925e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FW_IND_INITIALIZED 2 2935e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2945e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* HOST_REG interrupt from firmware */ 2955e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_FIRMWARE_MASK 0x00000400 2965e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_CE_MASK_ALL 0x0007f800 2975e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2985e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define DRAM_BASE_ADDRESS 0x00400000 2995e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 3005e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MISSING 0 3015e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 3025e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 3035e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 3045e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 3055e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 3065e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 3075e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RESET_CONTROL_MBOX_RST_MASK MISSING 3085e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 3095e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 3105e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 3115e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 3125e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 3135e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 3145e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 3155e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 3165e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LOCAL_SCRATCH_OFFSET 0x18 3175e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 3185e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 3195e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 3205e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 3215e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 3225e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 3235e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 3245e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 3255e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 3265e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 3275e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 3285e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MBOX_BASE_ADDRESS MISSING 3295e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_ERROR_LSB MISSING 3305e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_ERROR_MASK MISSING 3315e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_CPU_LSB MISSING 3325e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_CPU_MASK MISSING 3335e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_COUNTER_LSB MISSING 3345e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_COUNTER_MASK MISSING 3355e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 3365e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 3375e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 3385e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 3395e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 3405e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 3415e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 3425e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 3435e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_ADDRESS MISSING 3445e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 3455e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 3465e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_ADDRESS MISSING 3475e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_INT_STATUS_ADDRESS MISSING 3485e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_ADDRESS MISSING 3495e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_WAKEUP_MASK MISSING 3505e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_WAKEUP_LSB MISSING 3515e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 3525e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 3535e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 3545e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 3555e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define COUNT_DEC_ADDRESS MISSING 3565e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_CPU_MASK MISSING 3575e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_CPU_LSB MISSING 3585e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_ERROR_MASK MISSING 3595e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_ERROR_LSB MISSING 3605e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_COUNTER_MASK MISSING 3615e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_COUNTER_LSB MISSING 3625e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RX_LOOKAHEAD_VALID_ADDRESS MISSING 3635e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WINDOW_DATA_ADDRESS MISSING 3645e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WINDOW_READ_ADDR_ADDRESS MISSING 3655e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WINDOW_WRITE_ADDR_ADDRESS MISSING 3665e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 3675e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 3685e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 3695e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#endif /* _HW_H_ */ 370