hw.h revision 5e3dd157d7e70f0e3cea3f2573ed69fb156a19d5
15e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* 25e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Copyright (c) 2005-2011 Atheros Communications Inc. 35e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 45e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * 55e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Permission to use, copy, modify, and/or distribute this software for any 65e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * purpose with or without fee is hereby granted, provided that the above 75e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * copyright notice and this permission notice appear in all copies. 85e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * 95e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 105e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 115e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 125e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 135e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 145e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 155e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 165e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo */ 175e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 185e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#ifndef _HW_H_ 195e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define _HW_H_ 205e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 215e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#include "targaddrs.h" 225e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 235e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* Supported FW version */ 245e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SUPPORTED_FW_MAJOR 1 255e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SUPPORTED_FW_MINOR 0 265e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SUPPORTED_FW_RELEASE 0 275e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SUPPORTED_FW_BUILD 629 285e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 295e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* QCA988X 1.0 definitions */ 305e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_1_0_VERSION 0x4000002c 315e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_1_0_FW_DIR "ath10k/QCA988X/hw1.0" 325e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_1_0_FW_FILE "firmware.bin" 335e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_1_0_OTP_FILE "otp.bin" 345e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_1_0_BOARD_DATA_FILE "board.bin" 355e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_1_0_PATCH_LOAD_ADDR 0x1234 365e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 375e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* QCA988X 2.0 definitions */ 385e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_VERSION 0x4100016c 395e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0" 405e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_FW_FILE "firmware.bin" 415e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_OTP_FILE "otp.bin" 425e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 435e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 445e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 455e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* Known pecularities: 465e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - current FW doesn't support raw rx mode (last tested v599) 475e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - current FW dumps upon raw tx mode (last tested v599) 485e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 495e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - raw have FCS, nwifi doesn't 505e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 515e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * param, llc/snap) are aligned to 4byte boundaries each */ 525e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valoenum ath10k_hw_txrx_mode { 535e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_HW_TXRX_RAW = 0, 545e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_HW_TXRX_NATIVE_WIFI = 1, 555e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_HW_TXRX_ETHERNET = 2, 565e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo}; 575e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 585e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valoenum ath10k_mcast2ucast_mode { 595e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_MCAST2UCAST_DISABLED = 0, 605e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo ATH10K_MCAST2UCAST_ENABLED = 1, 615e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo}; 625e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 635e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_VDEVS 8 645e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_PEER_AST 2 655e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_WDS_ENTRIES 32 665e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_DMA_BURST_SIZE 0 675e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_MAC_AGGR_DELIM 0 685e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_AST_SKID_LIMIT 16 695e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_PEERS 16 705e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_OFFLOAD_PEERS 0 715e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 725e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_PEER_KEYS 2 735e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS))) 745e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 755e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 765e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_TIMEOUT_LO_PRI 100 775e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_TIMEOUT_HI_PRI 40 785e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_ETHERNET 795e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_SCAN_MAX_PENDING_REQS 4 805e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 815e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 825e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 835e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_GTK_OFFLOAD_MAX_VDEV 3 845e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_MCAST_GROUPS 0 855e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_MCAST_TABLE_ELEMS 0 865e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 875e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_TX_DBG_LOG_SIZE 1024 885e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 895e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_VOW_CONFIG 0 905e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_NUM_MSDU_DESC (1024 + 400) 915e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define TARGET_MAX_FRAG_ENTRIES 0 925e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 935e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 945e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* Number of Copy Engines supported */ 955e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE_COUNT 8 965e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 975e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* 985e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Total number of PCIe MSI interrupts requested for all interrupt sources. 995e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * PCIe standard forces this to be a power of 2. 1005e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Some Host OS's limit MSI requests that can be granted to 8 1015e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * so for now we abide by this limit and avoid requesting more 1025e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * than that. 1035e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo */ 1045e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_NUM_REQUEST_LOG2 3 1055e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) 1065e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1075e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* 1085e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Granted MSIs are assigned as follows: 1095e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Firmware uses the first 1105e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * Remaining MSIs, if any, are used by Copy Engines 1115e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * This mapping is known to both Target firmware and Host software. 1125e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo * It may be changed as long as Host and Target are kept in sync. 1135e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo */ 1145e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* MSI for firmware (errors, etc.) */ 1155e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_ASSIGN_FW 0 1165e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1175e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* MSIs for Copy Engines */ 1185e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_ASSIGN_CE_INITIAL 1 1195e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MSI_ASSIGN_CE_MAX 7 1205e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1215e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* as of IP3.7.1 */ 1225e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_ON 3 1235e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1245e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_COLD_RESET_MASK 0x00000400 1255e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_LSB 0 1265e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_MASK 0x00000007 1275e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_ADDRESS 0x0000 1285e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_SOC_WAKE_V_MASK 0x00000001 1295e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_SOC_WAKE_ADDRESS 0x0004 1305e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_SOC_WAKE_RESET 0x00000000 1315e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_GLOBAL_RESET_ADDRESS 0x0008 1325e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1335e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_SOC_BASE_ADDRESS 0x00004000 1345e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_WMAC_BASE_ADDRESS 0x00005000 1355e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MAC_COEX_BASE_ADDRESS 0x00006000 1365e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define BT_COEX_BASE_ADDRESS 0x00007000 1375e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_PCIE_BASE_ADDRESS 0x00008000 1385e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CORE_BASE_ADDRESS 0x00009000 1395e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_UART_BASE_ADDRESS 0x0000c000 1405e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SI_BASE_ADDRESS 0x00010000 1415e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_BASE_ADDRESS 0x00014000 1425e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 1435e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_MAC_BASE_ADDRESS 0x00020000 1445e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define EFUSE_BASE_ADDRESS 0x00030000 1455e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FPGA_REG_BASE_ADDRESS 0x00039000 1465e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_UART2_BASE_ADDRESS 0x00054c00 1475e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE_WRAPPER_BASE_ADDRESS 0x00057000 1485e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE0_BASE_ADDRESS 0x00057400 1495e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE1_BASE_ADDRESS 0x00057800 1505e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE2_BASE_ADDRESS 0x00057c00 1515e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE3_BASE_ADDRESS 0x00058000 1525e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE4_BASE_ADDRESS 0x00058400 1535e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE5_BASE_ADDRESS 0x00058800 1545e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE6_BASE_ADDRESS 0x00058c00 1555e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CE7_BASE_ADDRESS 0x00059000 1565e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define DBI_BASE_ADDRESS 0x00060000 1575e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 1585e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_LOCAL_BASE_ADDRESS 0x00080000 1595e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1605e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_RESET_CONTROL_OFFSET 0x00000000 1615e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 1625e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CPU_CLOCK_OFFSET 0x00000020 1635e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CPU_CLOCK_STANDARD_LSB 0 1645e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 1655e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CLOCK_CONTROL_OFFSET 0x00000028 1665e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 1675e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 1685e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_LPO_CAL_OFFSET 0x000000e0 1695e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_LPO_CAL_ENABLE_LSB 20 1705e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SOC_LPO_CAL_ENABLE_MASK 0x00100000 1715e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1725e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 1735e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 1745e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 1755e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 1765e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1775e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 1785e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 1795e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 1805e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 1815e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 1825e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 1835e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 1845e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 1855e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1865e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_GPIO_OFFSET 0xffffffff 1875e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 1885e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 1895e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 1905e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_OFFSET 0x00000000 1915e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 1925e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 1935e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_I2C_LSB 16 1945e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_I2C_MASK 0x00010000 1955e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_POS_SAMPLE_LSB 7 1965e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 1975e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_DATA_LSB 5 1985e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 1995e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_CLK_LSB 4 2005e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 2015e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_DIVIDER_LSB 0 2025e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CONFIG_DIVIDER_MASK 0x0000000f 2035e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_OFFSET 0x00000004 2045e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_DONE_ERR_MASK 0x00000400 2055e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_DONE_INT_MASK 0x00000200 2065e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_START_LSB 8 2075e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_START_MASK 0x00000100 2085e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_RX_CNT_LSB 4 2095e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_RX_CNT_MASK 0x000000f0 2105e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_TX_CNT_LSB 0 2115e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_CS_TX_CNT_MASK 0x0000000f 2125e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2135e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_TX_DATA0_OFFSET 0x00000008 2145e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_TX_DATA1_OFFSET 0x0000000c 2155e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_RX_DATA0_OFFSET 0x00000010 2165e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_RX_DATA1_OFFSET 0x00000014 2175e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2185e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CORE_CTRL_CPU_INTR_MASK 0x00002000 2195e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CORE_CTRL_ADDRESS 0x0000 2205e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_ENABLE_ADDRESS 0x0008 2215e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_CLR_ADDRESS 0x0014 2225e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SCRATCH_3_ADDRESS 0x0030 2235e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2245e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* Firmware indications to the Host via SCRATCH_3 register. */ 2255e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) 2265e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FW_IND_EVENT_PENDING 1 2275e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define FW_IND_INITIALIZED 2 2285e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2295e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo/* HOST_REG interrupt from firmware */ 2305e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_FIRMWARE_MASK 0x00000400 2315e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define PCIE_INTR_CE_MASK_ALL 0x0007f800 2325e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2335e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define DRAM_BASE_ADDRESS 0x00400000 2345e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2355e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MISSING 0 2365e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 2375e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 2385e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 2395e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 2405e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 2415e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 2425e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RESET_CONTROL_MBOX_RST_MASK MISSING 2435e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 2445e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 2455e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 2465e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 2475e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 2485e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 2495e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 2505e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 2515e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LOCAL_SCRATCH_OFFSET 0x18 2525e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 2535e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 2545e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 2555e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 2565e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 2575e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 2585e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 2595e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 2605e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 2615e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 2625e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 2635e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define MBOX_BASE_ADDRESS MISSING 2645e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_ERROR_LSB MISSING 2655e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_ERROR_MASK MISSING 2665e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_CPU_LSB MISSING 2675e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_CPU_MASK MISSING 2685e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_COUNTER_LSB MISSING 2695e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_COUNTER_MASK MISSING 2705e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 2715e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 2725e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 2735e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 2745e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 2755e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 2765e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 2775e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 2785e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define INT_STATUS_ENABLE_ADDRESS MISSING 2795e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 2805e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 2815e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_ADDRESS MISSING 2825e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define CPU_INT_STATUS_ADDRESS MISSING 2835e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_ADDRESS MISSING 2845e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_WAKEUP_MASK MISSING 2855e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_WAKEUP_LSB MISSING 2865e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 2875e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 2885e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 2895e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 2905e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define COUNT_DEC_ADDRESS MISSING 2915e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_CPU_MASK MISSING 2925e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_CPU_LSB MISSING 2935e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_ERROR_MASK MISSING 2945e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_ERROR_LSB MISSING 2955e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_COUNTER_MASK MISSING 2965e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define HOST_INT_STATUS_COUNTER_LSB MISSING 2975e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RX_LOOKAHEAD_VALID_ADDRESS MISSING 2985e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WINDOW_DATA_ADDRESS MISSING 2995e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WINDOW_READ_ADDR_ADDRESS MISSING 3005e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define WINDOW_WRITE_ADDR_ADDRESS MISSING 3015e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 3025e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 3035e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo 3045e3dd157d7e70f0e3cea3f2573ed69fb156a19d5Kalle Valo#endif /* _HW_H_ */ 305