1/*
2 * Firmware I/O code for mac80211 ST-Ericsson CW1200 drivers
3 *
4 * Copyright (c) 2010, ST-Ericsson
5 * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
6 *
7 * Based on:
8 * ST-Ericsson UMAC CW1200 driver which is
9 * Copyright (c) 2010, ST-Ericsson
10 * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/vmalloc.h>
18#include <linux/sched.h>
19#include <linux/firmware.h>
20
21#include "cw1200.h"
22#include "fwio.h"
23#include "hwio.h"
24#include "hwbus.h"
25#include "bh.h"
26
27static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision)
28{
29	int hw_type = -1;
30	u32 silicon_type = (config_reg_val >> 24) & 0x7;
31	u32 silicon_vers = (config_reg_val >> 31) & 0x1;
32
33	switch (silicon_type) {
34	case 0x00:
35		*major_revision = 1;
36		hw_type = HIF_9000_SILICON_VERSATILE;
37		break;
38	case 0x01:
39	case 0x02: /* CW1x00 */
40	case 0x04: /* CW1x60 */
41		*major_revision = silicon_type;
42		if (silicon_vers)
43			hw_type = HIF_8601_VERSATILE;
44		else
45			hw_type = HIF_8601_SILICON;
46		break;
47	default:
48		break;
49	}
50
51	return hw_type;
52}
53
54static int cw1200_load_firmware_cw1200(struct cw1200_common *priv)
55{
56	int ret, block, num_blocks;
57	unsigned i;
58	u32 val32;
59	u32 put = 0, get = 0;
60	u8 *buf = NULL;
61	const char *fw_path;
62	const struct firmware *firmware = NULL;
63
64	/* Macroses are local. */
65#define APB_WRITE(reg, val) \
66	do { \
67		ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
68		if (ret < 0) \
69			goto error; \
70	} while (0)
71#define APB_READ(reg, val) \
72	do { \
73		ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \
74		if (ret < 0) \
75			goto error; \
76	} while (0)
77#define REG_WRITE(reg, val) \
78	do { \
79		ret = cw1200_reg_write_32(priv, (reg), (val)); \
80		if (ret < 0) \
81			goto error; \
82	} while (0)
83#define REG_READ(reg, val) \
84	do { \
85		ret = cw1200_reg_read_32(priv, (reg), &(val)); \
86		if (ret < 0) \
87			goto error; \
88	} while (0)
89
90	switch (priv->hw_revision) {
91	case CW1200_HW_REV_CUT10:
92		fw_path = FIRMWARE_CUT10;
93		if (!priv->sdd_path)
94			priv->sdd_path = SDD_FILE_10;
95		break;
96	case CW1200_HW_REV_CUT11:
97		fw_path = FIRMWARE_CUT11;
98		if (!priv->sdd_path)
99			priv->sdd_path = SDD_FILE_11;
100		break;
101	case CW1200_HW_REV_CUT20:
102		fw_path = FIRMWARE_CUT20;
103		if (!priv->sdd_path)
104			priv->sdd_path = SDD_FILE_20;
105		break;
106	case CW1200_HW_REV_CUT22:
107		fw_path = FIRMWARE_CUT22;
108		if (!priv->sdd_path)
109			priv->sdd_path = SDD_FILE_22;
110		break;
111	case CW1X60_HW_REV:
112		fw_path = FIRMWARE_CW1X60;
113		if (!priv->sdd_path)
114			priv->sdd_path = SDD_FILE_CW1X60;
115		break;
116	default:
117		pr_err("Invalid silicon revision %d.\n", priv->hw_revision);
118		return -EINVAL;
119	}
120
121	/* Initialize common registers */
122	APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
123	APB_WRITE(DOWNLOAD_PUT_REG, 0);
124	APB_WRITE(DOWNLOAD_GET_REG, 0);
125	APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
126	APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
127
128	/* Write the NOP Instruction */
129	REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
130	REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
131
132	/* Release CPU from RESET */
133	REG_READ(ST90TDS_CONFIG_REG_ID, val32);
134	val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT;
135	REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
136
137	/* Enable Clock */
138	val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT;
139	REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
140
141	/* Load a firmware file */
142	ret = request_firmware(&firmware, fw_path, priv->pdev);
143	if (ret) {
144		pr_err("Can't load firmware file %s.\n", fw_path);
145		goto error;
146	}
147
148	buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA);
149	if (!buf) {
150		pr_err("Can't allocate firmware load buffer.\n");
151		ret = -ENOMEM;
152		goto error;
153	}
154
155	/* Check if the bootloader is ready */
156	for (i = 0; i < 100; i += 1 + i / 2) {
157		APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
158		if (val32 == DOWNLOAD_I_AM_HERE)
159			break;
160		mdelay(i);
161	} /* End of for loop */
162
163	if (val32 != DOWNLOAD_I_AM_HERE) {
164		pr_err("Bootloader is not ready.\n");
165		ret = -ETIMEDOUT;
166		goto error;
167	}
168
169	/* Calculcate number of download blocks */
170	num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
171
172	/* Updating the length in Download Ctrl Area */
173	val32 = firmware->size; /* Explicit cast from size_t to u32 */
174	APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, val32);
175
176	/* Firmware downloading loop */
177	for (block = 0; block < num_blocks; block++) {
178		size_t tx_size;
179		size_t block_size;
180
181		/* check the download status */
182		APB_READ(DOWNLOAD_STATUS_REG, val32);
183		if (val32 != DOWNLOAD_PENDING) {
184			pr_err("Bootloader reported error %d.\n", val32);
185			ret = -EIO;
186			goto error;
187		}
188
189		/* loop until put - get <= 24K */
190		for (i = 0; i < 100; i++) {
191			APB_READ(DOWNLOAD_GET_REG, get);
192			if ((put - get) <=
193			    (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
194				break;
195			mdelay(i);
196		}
197
198		if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
199			pr_err("Timeout waiting for FIFO.\n");
200			ret = -ETIMEDOUT;
201			goto error;
202		}
203
204		/* calculate the block size */
205		tx_size = block_size = min_t(size_t, firmware->size - put,
206					DOWNLOAD_BLOCK_SIZE);
207
208		memcpy(buf, &firmware->data[put], block_size);
209		if (block_size < DOWNLOAD_BLOCK_SIZE) {
210			memset(&buf[block_size], 0,
211			       DOWNLOAD_BLOCK_SIZE - block_size);
212			tx_size = DOWNLOAD_BLOCK_SIZE;
213		}
214
215		/* send the block to sram */
216		ret = cw1200_apb_write(priv,
217			CW1200_APB(DOWNLOAD_FIFO_OFFSET +
218				   (put & (DOWNLOAD_FIFO_SIZE - 1))),
219			buf, tx_size);
220		if (ret < 0) {
221			pr_err("Can't write firmware block @ %d!\n",
222			       put & (DOWNLOAD_FIFO_SIZE - 1));
223			goto error;
224		}
225
226		/* update the put register */
227		put += block_size;
228		APB_WRITE(DOWNLOAD_PUT_REG, put);
229	} /* End of firmware download loop */
230
231	/* Wait for the download completion */
232	for (i = 0; i < 300; i += 1 + i / 2) {
233		APB_READ(DOWNLOAD_STATUS_REG, val32);
234		if (val32 != DOWNLOAD_PENDING)
235			break;
236		mdelay(i);
237	}
238	if (val32 != DOWNLOAD_SUCCESS) {
239		pr_err("Wait for download completion failed: 0x%.8X\n", val32);
240		ret = -ETIMEDOUT;
241		goto error;
242	} else {
243		pr_info("Firmware download completed.\n");
244		ret = 0;
245	}
246
247error:
248	kfree(buf);
249	if (firmware)
250		release_firmware(firmware);
251	return ret;
252
253#undef APB_WRITE
254#undef APB_READ
255#undef REG_WRITE
256#undef REG_READ
257}
258
259
260static int config_reg_read(struct cw1200_common *priv, u32 *val)
261{
262	switch (priv->hw_type) {
263	case HIF_9000_SILICON_VERSATILE: {
264		u16 val16;
265		int ret = cw1200_reg_read_16(priv,
266					     ST90TDS_CONFIG_REG_ID,
267					     &val16);
268		if (ret < 0)
269			return ret;
270		*val = val16;
271		return 0;
272	}
273	case HIF_8601_VERSATILE:
274	case HIF_8601_SILICON:
275	default:
276		cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val);
277		break;
278	}
279	return 0;
280}
281
282static int config_reg_write(struct cw1200_common *priv, u32 val)
283{
284	switch (priv->hw_type) {
285	case HIF_9000_SILICON_VERSATILE:
286		return cw1200_reg_write_16(priv,
287					   ST90TDS_CONFIG_REG_ID,
288					   (u16)val);
289	case HIF_8601_VERSATILE:
290	case HIF_8601_SILICON:
291	default:
292		return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val);
293	}
294	return 0;
295}
296
297int cw1200_load_firmware(struct cw1200_common *priv)
298{
299	int ret;
300	int i;
301	u32 val32;
302	u16 val16;
303	int major_revision = -1;
304
305	/* Read CONFIG Register */
306	ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
307	if (ret < 0) {
308		pr_err("Can't read config register.\n");
309		goto out;
310	}
311
312	if (val32 == 0 || val32 == 0xffffffff) {
313		pr_err("Bad config register value (0x%08x)\n", val32);
314		ret = -EIO;
315		goto out;
316	}
317
318	priv->hw_type = cw1200_get_hw_type(val32, &major_revision);
319	if (priv->hw_type < 0) {
320		pr_err("Can't deduce hardware type.\n");
321		ret = -ENOTSUPP;
322		goto out;
323	}
324
325	/* Set DPLL Reg value, and read back to confirm writes work */
326	ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
327				  cw1200_dpll_from_clk(priv->hw_refclk));
328	if (ret < 0) {
329		pr_err("Can't write DPLL register.\n");
330		goto out;
331	}
332
333	msleep(20);
334
335	ret = cw1200_reg_read_32(priv,
336		ST90TDS_TSET_GEN_R_W_REG_ID, &val32);
337	if (ret < 0) {
338		pr_err("Can't read DPLL register.\n");
339		goto out;
340	}
341
342	if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) {
343		pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n",
344		       cw1200_dpll_from_clk(priv->hw_refclk), val32);
345		ret = -EIO;
346		goto out;
347	}
348
349	/* Set wakeup bit in device */
350	ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16);
351	if (ret < 0) {
352		pr_err("set_wakeup: can't read control register.\n");
353		goto out;
354	}
355
356	ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
357		val16 | ST90TDS_CONT_WUP_BIT);
358	if (ret < 0) {
359		pr_err("set_wakeup: can't write control register.\n");
360		goto out;
361	}
362
363	/* Wait for wakeup */
364	for (i = 0; i < 300; i += (1 + i / 2)) {
365		ret = cw1200_reg_read_16(priv,
366			ST90TDS_CONTROL_REG_ID, &val16);
367		if (ret < 0) {
368			pr_err("wait_for_wakeup: can't read control register.\n");
369			goto out;
370		}
371
372		if (val16 & ST90TDS_CONT_RDY_BIT)
373			break;
374
375		msleep(i);
376	}
377
378	if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) {
379		pr_err("wait_for_wakeup: device is not responding.\n");
380		ret = -ETIMEDOUT;
381		goto out;
382	}
383
384	switch (major_revision) {
385	case 1:
386		/* CW1200 Hardware detection logic : Check for CUT1.1 */
387		ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32);
388		if (ret) {
389			pr_err("HW detection: can't read CUT ID.\n");
390			goto out;
391		}
392
393		switch (val32) {
394		case CW1200_CUT_11_ID_STR:
395			pr_info("CW1x00 Cut 1.1 silicon detected.\n");
396			priv->hw_revision = CW1200_HW_REV_CUT11;
397			break;
398		default:
399			pr_info("CW1x00 Cut 1.0 silicon detected.\n");
400			priv->hw_revision = CW1200_HW_REV_CUT10;
401			break;
402		}
403
404		/* According to ST-E, CUT<2.0 has busted BA TID0-3.
405		   Just disable it entirely...
406		*/
407		priv->ba_rx_tid_mask = 0;
408		priv->ba_tx_tid_mask = 0;
409		break;
410	case 2: {
411		u32 ar1, ar2, ar3;
412		ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1);
413		if (ret) {
414			pr_err("(1) HW detection: can't read CUT ID\n");
415			goto out;
416		}
417		ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2);
418		if (ret) {
419			pr_err("(2) HW detection: can't read CUT ID.\n");
420			goto out;
421		}
422
423		ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3);
424		if (ret) {
425			pr_err("(3) HW detection: can't read CUT ID.\n");
426			goto out;
427		}
428
429		if (ar1 == CW1200_CUT_22_ID_STR1 &&
430		    ar2 == CW1200_CUT_22_ID_STR2 &&
431		    ar3 == CW1200_CUT_22_ID_STR3) {
432			pr_info("CW1x00 Cut 2.2 silicon detected.\n");
433			priv->hw_revision = CW1200_HW_REV_CUT22;
434		} else {
435			pr_info("CW1x00 Cut 2.0 silicon detected.\n");
436			priv->hw_revision = CW1200_HW_REV_CUT20;
437		}
438		break;
439	}
440	case 4:
441		pr_info("CW1x60 silicon detected.\n");
442		priv->hw_revision = CW1X60_HW_REV;
443		break;
444	default:
445		pr_err("Unsupported silicon major revision %d.\n",
446		       major_revision);
447		ret = -ENOTSUPP;
448		goto out;
449	}
450
451	/* Checking for access mode */
452	ret = config_reg_read(priv, &val32);
453	if (ret < 0) {
454		pr_err("Can't read config register.\n");
455		goto out;
456	}
457
458	if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) {
459		pr_err("Device is already in QUEUE mode!\n");
460			ret = -EINVAL;
461			goto out;
462	}
463
464	switch (priv->hw_type)  {
465	case HIF_8601_SILICON:
466		if (priv->hw_revision == CW1X60_HW_REV) {
467			pr_err("Can't handle CW1160/1260 firmware load yet.\n");
468			ret = -ENOTSUPP;
469			goto out;
470		}
471		ret = cw1200_load_firmware_cw1200(priv);
472		break;
473	default:
474		pr_err("Can't perform firmware load for hw type %d.\n",
475		       priv->hw_type);
476		ret = -ENOTSUPP;
477		goto out;
478	}
479	if (ret < 0) {
480		pr_err("Firmware load error.\n");
481		goto out;
482	}
483
484	/* Enable interrupt signalling */
485	priv->hwbus_ops->lock(priv->hwbus_priv);
486	ret = __cw1200_irq_enable(priv, 1);
487	priv->hwbus_ops->unlock(priv->hwbus_priv);
488	if (ret < 0)
489		goto unsubscribe;
490
491	/* Configure device for MESSSAGE MODE */
492	ret = config_reg_read(priv, &val32);
493	if (ret < 0) {
494		pr_err("Can't read config register.\n");
495		goto unsubscribe;
496	}
497	ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT);
498	if (ret < 0) {
499		pr_err("Can't write config register.\n");
500		goto unsubscribe;
501	}
502
503	/* Unless we read the CONFIG Register we are
504	 * not able to get an interrupt
505	 */
506	mdelay(10);
507	config_reg_read(priv, &val32);
508
509out:
510	return ret;
511
512unsubscribe:
513	/* Disable interrupt signalling */
514	priv->hwbus_ops->lock(priv->hwbus_priv);
515	ret = __cw1200_irq_enable(priv, 0);
516	priv->hwbus_ops->unlock(priv->hwbus_priv);
517	return ret;
518}
519