1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2013 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL88E_DM_H__ 31#define __RTL88E_DM_H__ 32 33#define MAIN_ANT 0 34#define AUX_ANT 1 35#define MAIN_ANT_CG_TRX 1 36#define AUX_ANT_CG_TRX 0 37#define MAIN_ANT_CGCS_RX 0 38#define AUX_ANT_CGCS_RX 1 39 40/*RF REG LIST*/ 41#define DM_REG_RF_MODE_11N 0x00 42#define DM_REG_RF_0B_11N 0x0B 43#define DM_REG_CHNBW_11N 0x18 44#define DM_REG_T_METER_11N 0x24 45#define DM_REG_RF_25_11N 0x25 46#define DM_REG_RF_26_11N 0x26 47#define DM_REG_RF_27_11N 0x27 48#define DM_REG_RF_2B_11N 0x2B 49#define DM_REG_RF_2C_11N 0x2C 50#define DM_REG_RXRF_A3_11N 0x3C 51#define DM_REG_T_METER_92D_11N 0x42 52#define DM_REG_T_METER_88E_11N 0x42 53 54/*BB REG LIST*/ 55/*PAGE 8 */ 56#define DM_REG_BB_CTRL_11N 0x800 57#define DM_REG_RF_PIN_11N 0x804 58#define DM_REG_PSD_CTRL_11N 0x808 59#define DM_REG_TX_ANT_CTRL_11N 0x80C 60#define DM_REG_BB_PWR_SAV5_11N 0x818 61#define DM_REG_CCK_RPT_FORMAT_11N 0x824 62#define DM_REG_RX_DEFAULT_A_11N 0x858 63#define DM_REG_RX_DEFAULT_B_11N 0x85A 64#define DM_REG_BB_PWR_SAV3_11N 0x85C 65#define DM_REG_ANTSEL_CTRL_11N 0x860 66#define DM_REG_RX_ANT_CTRL_11N 0x864 67#define DM_REG_PIN_CTRL_11N 0x870 68#define DM_REG_BB_PWR_SAV1_11N 0x874 69#define DM_REG_ANTSEL_PATH_11N 0x878 70#define DM_REG_BB_3WIRE_11N 0x88C 71#define DM_REG_SC_CNT_11N 0x8C4 72#define DM_REG_PSD_DATA_11N 0x8B4 73/*PAGE 9*/ 74#define DM_REG_ANT_MAPPING1_11N 0x914 75#define DM_REG_ANT_MAPPING2_11N 0x918 76/*PAGE A*/ 77#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00 78#define DM_REG_CCK_CCA_11N 0xA0A 79#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C 80#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10 81#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14 82#define DM_REG_CCK_FILTER_PARA1_11N 0xA22 83#define DM_REG_CCK_FILTER_PARA2_11N 0xA23 84#define DM_REG_CCK_FILTER_PARA3_11N 0xA24 85#define DM_REG_CCK_FILTER_PARA4_11N 0xA25 86#define DM_REG_CCK_FILTER_PARA5_11N 0xA26 87#define DM_REG_CCK_FILTER_PARA6_11N 0xA27 88#define DM_REG_CCK_FILTER_PARA7_11N 0xA28 89#define DM_REG_CCK_FILTER_PARA8_11N 0xA29 90#define DM_REG_CCK_FA_RST_11N 0xA2C 91#define DM_REG_CCK_FA_MSB_11N 0xA58 92#define DM_REG_CCK_FA_LSB_11N 0xA5C 93#define DM_REG_CCK_CCA_CNT_11N 0xA60 94#define DM_REG_BB_PWR_SAV4_11N 0xA74 95/*PAGE B */ 96#define DM_REG_LNA_SWITCH_11N 0xB2C 97#define DM_REG_PATH_SWITCH_11N 0xB30 98#define DM_REG_RSSI_CTRL_11N 0xB38 99#define DM_REG_CONFIG_ANTA_11N 0xB68 100#define DM_REG_RSSI_BT_11N 0xB9C 101/*PAGE C */ 102#define DM_REG_OFDM_FA_HOLDC_11N 0xC00 103#define DM_REG_RX_PATH_11N 0xC04 104#define DM_REG_TRMUX_11N 0xC08 105#define DM_REG_OFDM_FA_RSTC_11N 0xC0C 106#define DM_REG_RXIQI_MATRIX_11N 0xC14 107#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C 108#define DM_REG_IGI_A_11N 0xC50 109#define DM_REG_ANTDIV_PARA2_11N 0xC54 110#define DM_REG_IGI_B_11N 0xC58 111#define DM_REG_ANTDIV_PARA3_11N 0xC5C 112#define DM_REG_BB_PWR_SAV2_11N 0xC70 113#define DM_REG_RX_OFF_11N 0xC7C 114#define DM_REG_TXIQK_MATRIXA_11N 0xC80 115#define DM_REG_TXIQK_MATRIXB_11N 0xC88 116#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 117#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C 118#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 119#define DM_REG_ANTDIV_PARA1_11N 0xCA4 120#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0 121/*PAGE D */ 122#define DM_REG_OFDM_FA_RSTD_11N 0xD00 123#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0 124#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4 125#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8 126/*PAGE E */ 127#define DM_REG_TXAGC_A_6_18_11N 0xE00 128#define DM_REG_TXAGC_A_24_54_11N 0xE04 129#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08 130#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10 131#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14 132#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18 133#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C 134#define DM_REG_FPGA0_IQK_11N 0xE28 135#define DM_REG_TXIQK_TONE_A_11N 0xE30 136#define DM_REG_RXIQK_TONE_A_11N 0xE34 137#define DM_REG_TXIQK_PI_A_11N 0xE38 138#define DM_REG_RXIQK_PI_A_11N 0xE3C 139#define DM_REG_TXIQK_11N 0xE40 140#define DM_REG_RXIQK_11N 0xE44 141#define DM_REG_IQK_AGC_PTS_11N 0xE48 142#define DM_REG_IQK_AGC_RSP_11N 0xE4C 143#define DM_REG_BLUETOOTH_11N 0xE6C 144#define DM_REG_RX_WAIT_CCA_11N 0xE70 145#define DM_REG_TX_CCK_RFON_11N 0xE74 146#define DM_REG_TX_CCK_BBON_11N 0xE78 147#define DM_REG_OFDM_RFON_11N 0xE7C 148#define DM_REG_OFDM_BBON_11N 0xE80 149#define DM_REG_TX2RX_11N 0xE84 150#define DM_REG_TX2TX_11N 0xE88 151#define DM_REG_RX_CCK_11N 0xE8C 152#define DM_REG_RX_OFDM_11N 0xED0 153#define DM_REG_RX_WAIT_RIFS_11N 0xED4 154#define DM_REG_RX2RX_11N 0xED8 155#define DM_REG_STANDBY_11N 0xEDC 156#define DM_REG_SLEEP_11N 0xEE0 157#define DM_REG_PMPD_ANAEN_11N 0xEEC 158 159/*MAC REG LIST*/ 160#define DM_REG_BB_RST_11N 0x02 161#define DM_REG_ANTSEL_PIN_11N 0x4C 162#define DM_REG_EARLY_MODE_11N 0x4D0 163#define DM_REG_RSSI_MONITOR_11N 0x4FE 164#define DM_REG_EDCA_VO_11N 0x500 165#define DM_REG_EDCA_VI_11N 0x504 166#define DM_REG_EDCA_BE_11N 0x508 167#define DM_REG_EDCA_BK_11N 0x50C 168#define DM_REG_TXPAUSE_11N 0x522 169#define DM_REG_RESP_TX_11N 0x6D8 170#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0 171#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4 172 173 174/*DIG Related*/ 175#define DM_BIT_IGI_11N 0x0000007F 176 177#define HAL_DM_DIG_DISABLE BIT(0) 178#define HAL_DM_HIPWR_DISABLE BIT(1) 179 180#define OFDM_TABLE_LENGTH 43 181#define CCK_TABLE_LENGTH 33 182 183#define OFDM_TABLE_SIZE 43 184#define CCK_TABLE_SIZE 33 185 186#define BW_AUTO_SWITCH_HIGH_LOW 25 187#define BW_AUTO_SWITCH_LOW_HIGH 30 188 189#define DM_DIG_THRESH_HIGH 40 190#define DM_DIG_THRESH_LOW 35 191 192#define DM_FALSEALARM_THRESH_LOW 400 193#define DM_FALSEALARM_THRESH_HIGH 1000 194 195#define DM_DIG_MAX 0x3e 196#define DM_DIG_MIN 0x1e 197 198#define DM_DIG_MAX_AP 0x32 199#define DM_DIG_MIN_AP 0x20 200 201#define DM_DIG_FA_UPPER 0x3e 202#define DM_DIG_FA_LOWER 0x1e 203#define DM_DIG_FA_TH0 0x200 204#define DM_DIG_FA_TH1 0x300 205#define DM_DIG_FA_TH2 0x400 206 207#define DM_DIG_BACKOFF_MAX 12 208#define DM_DIG_BACKOFF_MIN -4 209#define DM_DIG_BACKOFF_DEFAULT 10 210 211#define RXPATHSELECTION_SS_TH_W 30 212#define RXPATHSELECTION_DIFF_TH 18 213 214#define DM_RATR_STA_INIT 0 215#define DM_RATR_STA_HIGH 1 216#define DM_RATR_STA_MIDDLE 2 217#define DM_RATR_STA_LOW 3 218 219#define CTS2SELF_THVAL 30 220#define REGC38_TH 20 221 222#define WAIOTTHVAL 25 223 224#define TXHIGHPWRLEVEL_NORMAL 0 225#define TXHIGHPWRLEVEL_LEVEL1 1 226#define TXHIGHPWRLEVEL_LEVEL2 2 227#define TXHIGHPWRLEVEL_BT1 3 228#define TXHIGHPWRLEVEL_BT2 4 229 230#define DM_TYPE_BYFW 0 231#define DM_TYPE_BYDRIVER 1 232 233#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 234#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 235#define TXPWRTRACK_MAX_IDX 6 236 237struct swat_t { 238 u8 failure_cnt; 239 u8 try_flag; 240 u8 stop_trying; 241 242 long pre_rssi; 243 long trying_threshold; 244 u8 cur_antenna; 245 u8 pre_antenna; 246 247}; 248 249enum FAT_STATE { 250 FAT_NORMAL_STATE = 0, 251 FAT_TRAINING_STATE = 1, 252}; 253 254enum tag_dynamic_init_gain_operation_type_definition { 255 DIG_TYPE_THRESH_HIGH = 0, 256 DIG_TYPE_THRESH_LOW = 1, 257 DIG_TYPE_BACKOFF = 2, 258 DIG_TYPE_RX_GAIN_MIN = 3, 259 DIG_TYPE_RX_GAIN_MAX = 4, 260 DIG_TYPE_ENABLE = 5, 261 DIG_TYPE_DISABLE = 6, 262 DIG_OP_TYPE_MAX 263}; 264 265enum tag_cck_packet_detection_threshold_type_definition { 266 CCK_PD_STAGE_LOWRSSI = 0, 267 CCK_PD_STAGE_HIGHRSSI = 1, 268 CCK_FA_STAGE_LOW = 2, 269 CCK_FA_STAGE_HIGH = 3, 270 CCK_PD_STAGE_MAX = 4, 271}; 272 273enum dm_1r_cca_e { 274 CCA_1R = 0, 275 CCA_2R = 1, 276 CCA_MAX = 2, 277}; 278 279enum dm_rf_e { 280 RF_SAVE = 0, 281 RF_NORMAL = 1, 282 RF_MAX = 2, 283}; 284 285enum dm_sw_ant_switch_e { 286 ANS_ANTENNA_B = 1, 287 ANS_ANTENNA_A = 2, 288 ANS_ANTENNA_MAX = 3, 289}; 290 291enum dm_dig_ext_port_alg_e { 292 DIG_EXT_PORT_STAGE_0 = 0, 293 DIG_EXT_PORT_STAGE_1 = 1, 294 DIG_EXT_PORT_STAGE_2 = 2, 295 DIG_EXT_PORT_STAGE_3 = 3, 296 DIG_EXT_PORT_STAGE_MAX = 4, 297}; 298 299enum dm_dig_connect_e { 300 DIG_STA_DISCONNECT = 0, 301 DIG_STA_CONNECT = 1, 302 DIG_STA_BEFORE_CONNECT = 2, 303 DIG_MULTISTA_DISCONNECT = 3, 304 DIG_MULTISTA_CONNECT = 4, 305 DIG_CONNECT_MAX 306}; 307 308enum pwr_track_control_method { 309 BBSWING, 310 TXAGC 311}; 312 313void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, 314 u8 *pdesc, u32 mac_id); 315void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw, 316 u8 antsel_tr_mux, u32 mac_id, 317 u32 rx_pwdb_all); 318void rtl88e_dm_fast_antenna_training_callback(unsigned long data); 319void rtl88e_dm_init(struct ieee80211_hw *hw); 320void rtl88e_dm_watchdog(struct ieee80211_hw *hw); 321void rtl88e_dm_write_dig(struct ieee80211_hw *hw); 322void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw); 323void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw); 324void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 325void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw, 326 u8 type, u8 *pdirection, u32 *poutwrite_val); 327#endif 328