1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#include "../wifi.h" 31#include "../core.h" 32#include "../base.h" 33#include "../pci.h" 34#include "reg.h" 35#include "def.h" 36#include "phy.h" 37#include "dm.h" 38#include "fw.h" 39#include "hw.h" 40#include "sw.h" 41#include "trx.h" 42#include "led.h" 43 44#include <linux/module.h> 45 46static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw) 47{ 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 50 /*close ASPM for AMD defaultly */ 51 rtlpci->const_amdpci_aspm = 0; 52 53 /* ASPM PS mode. 54 * 0 - Disable ASPM, 55 * 1 - Enable ASPM without Clock Req, 56 * 2 - Enable ASPM with Clock Req, 57 * 3 - Alwyas Enable ASPM with Clock Req, 58 * 4 - Always Enable ASPM without Clock Req. 59 * set defult to RTL8192CE:3 RTL8192E:2 60 * */ 61 rtlpci->const_pci_aspm = 2; 62 63 /*Setting for PCI-E device */ 64 rtlpci->const_devicepci_aspm_setting = 0x03; 65 66 /*Setting for PCI-E bridge */ 67 rtlpci->const_hostpci_aspm_setting = 0x02; 68 69 /* In Hw/Sw Radio Off situation. 70 * 0 - Default, 71 * 1 - From ASPM setting without low Mac Pwr, 72 * 2 - From ASPM setting with low Mac Pwr, 73 * 3 - Bus D3 74 * set default to RTL8192CE:0 RTL8192SE:2 75 */ 76 rtlpci->const_hwsw_rfoff_d3 = 2; 77 78 /* This setting works for those device with 79 * backdoor ASPM setting such as EPHY setting. 80 * 0 - Not support ASPM, 81 * 1 - Support ASPM, 82 * 2 - According to chipset. 83 */ 84 rtlpci->const_support_pciaspm = 2; 85} 86 87static void rtl92se_fw_cb(const struct firmware *firmware, void *context) 88{ 89 struct ieee80211_hw *hw = context; 90 struct rtl_priv *rtlpriv = rtl_priv(hw); 91 struct rt_firmware *pfirmware = NULL; 92 93 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 94 "Firmware callback routine entered!\n"); 95 complete(&rtlpriv->firmware_loading_complete); 96 if (!firmware) { 97 pr_err("Firmware %s not available\n", rtlpriv->cfg->fw_name); 98 rtlpriv->max_fw_size = 0; 99 return; 100 } 101 if (firmware->size > rtlpriv->max_fw_size) { 102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 103 "Firmware is too big!\n"); 104 rtlpriv->max_fw_size = 0; 105 release_firmware(firmware); 106 return; 107 } 108 pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware; 109 memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size); 110 pfirmware->sz_fw_tmpbufferlen = firmware->size; 111 release_firmware(firmware); 112} 113 114static int rtl92s_init_sw_vars(struct ieee80211_hw *hw) 115{ 116 struct rtl_priv *rtlpriv = rtl_priv(hw); 117 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 118 int err = 0; 119 u16 earlyrxthreshold = 7; 120 121 rtlpriv->dm.dm_initialgain_enable = true; 122 rtlpriv->dm.dm_flag = 0; 123 rtlpriv->dm.disable_framebursting = false; 124 rtlpriv->dm.thermalvalue = 0; 125 rtlpriv->dm.useramask = true; 126 127 /* compatible 5G band 91se just 2.4G band & smsp */ 128 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 129 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 130 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 131 132 rtlpci->transmit_config = 0; 133 134 rtlpci->receive_config = 135 RCR_APPFCS | 136 RCR_APWRMGT | 137 /*RCR_ADD3 |*/ 138 RCR_AMF | 139 RCR_ADF | 140 RCR_APP_MIC | 141 RCR_APP_ICV | 142 RCR_AICV | 143 /* Accept ICV error, CRC32 Error */ 144 RCR_ACRC32 | 145 RCR_AB | 146 /* Accept Broadcast, Multicast */ 147 RCR_AM | 148 /* Accept Physical match */ 149 RCR_APM | 150 /* Accept Destination Address packets */ 151 /*RCR_AAP |*/ 152 RCR_APP_PHYST_STAFF | 153 /* Accept PHY status */ 154 RCR_APP_PHYST_RXFF | 155 (earlyrxthreshold << RCR_FIFO_OFFSET); 156 157 rtlpci->irq_mask[0] = (u32) 158 (IMR_ROK | 159 IMR_VODOK | 160 IMR_VIDOK | 161 IMR_BEDOK | 162 IMR_BKDOK | 163 IMR_HCCADOK | 164 IMR_MGNTDOK | 165 IMR_COMDOK | 166 IMR_HIGHDOK | 167 IMR_BDOK | 168 IMR_RXCMDOK | 169 /*IMR_TIMEOUT0 |*/ 170 IMR_RDU | 171 IMR_RXFOVW | 172 IMR_BCNINT 173 /*| IMR_TXFOVW*/ 174 /*| IMR_TBDOK | 175 IMR_TBDER*/); 176 177 rtlpci->irq_mask[1] = (u32) 0; 178 179 rtlpci->shortretry_limit = 0x30; 180 rtlpci->longretry_limit = 0x30; 181 182 rtlpci->first_init = true; 183 184 /* for debug level */ 185 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 186 /* for LPS & IPS */ 187 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 188 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 189 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 190 if (!rtlpriv->psc.inactiveps) 191 pr_info("Power Save off (module option)\n"); 192 if (!rtlpriv->psc.fwctrl_lps) 193 pr_info("FW Power Save off (module option)\n"); 194 rtlpriv->psc.reg_fwctrl_lps = 3; 195 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 196 /* for ASPM, you can close aspm through 197 * set const_support_pciaspm = 0 */ 198 rtl92s_init_aspm_vars(hw); 199 200 if (rtlpriv->psc.reg_fwctrl_lps == 1) 201 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 202 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 203 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 204 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 205 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 206 207 /* for firmware buf */ 208 rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware)); 209 if (!rtlpriv->rtlhal.pfirmware) 210 return 1; 211 212 rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 + 213 sizeof(struct fw_hdr); 214 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n" 215 "Loading firmware %s\n", rtlpriv->cfg->fw_name); 216 /* request fw */ 217 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, 218 rtlpriv->io.dev, GFP_KERNEL, hw, 219 rtl92se_fw_cb); 220 if (err) { 221 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 222 "Failed to request firmware!\n"); 223 return 1; 224 } 225 226 return err; 227} 228 229static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw) 230{ 231 struct rtl_priv *rtlpriv = rtl_priv(hw); 232 233 if (rtlpriv->rtlhal.pfirmware) { 234 vfree(rtlpriv->rtlhal.pfirmware); 235 rtlpriv->rtlhal.pfirmware = NULL; 236 } 237} 238 239static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, 240 u16 index) 241{ 242 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 243 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 244 u8 *entry = (u8 *)(&ring->desc[ring->idx]); 245 u8 own = (u8)rtl92se_get_desc(entry, true, HW_DESC_OWN); 246 247 if (own) 248 return false; 249 return true; 250} 251 252static struct rtl_hal_ops rtl8192se_hal_ops = { 253 .init_sw_vars = rtl92s_init_sw_vars, 254 .deinit_sw_vars = rtl92s_deinit_sw_vars, 255 .read_eeprom_info = rtl92se_read_eeprom_info, 256 .interrupt_recognized = rtl92se_interrupt_recognized, 257 .hw_init = rtl92se_hw_init, 258 .hw_disable = rtl92se_card_disable, 259 .hw_suspend = rtl92se_suspend, 260 .hw_resume = rtl92se_resume, 261 .enable_interrupt = rtl92se_enable_interrupt, 262 .disable_interrupt = rtl92se_disable_interrupt, 263 .set_network_type = rtl92se_set_network_type, 264 .set_chk_bssid = rtl92se_set_check_bssid, 265 .set_qos = rtl92se_set_qos, 266 .set_bcn_reg = rtl92se_set_beacon_related_registers, 267 .set_bcn_intv = rtl92se_set_beacon_interval, 268 .update_interrupt_mask = rtl92se_update_interrupt_mask, 269 .get_hw_reg = rtl92se_get_hw_reg, 270 .set_hw_reg = rtl92se_set_hw_reg, 271 .update_rate_tbl = rtl92se_update_hal_rate_tbl, 272 .fill_tx_desc = rtl92se_tx_fill_desc, 273 .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc, 274 .query_rx_desc = rtl92se_rx_query_desc, 275 .set_channel_access = rtl92se_update_channel_access_setting, 276 .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking, 277 .set_bw_mode = rtl92s_phy_set_bw_mode, 278 .switch_channel = rtl92s_phy_sw_chnl, 279 .dm_watchdog = rtl92s_dm_watchdog, 280 .scan_operation_backup = rtl92s_phy_scan_operation_backup, 281 .set_rf_power_state = rtl92s_phy_set_rf_power_state, 282 .led_control = rtl92se_led_control, 283 .set_desc = rtl92se_set_desc, 284 .get_desc = rtl92se_get_desc, 285 .is_tx_desc_closed = rtl92se_is_tx_desc_closed, 286 .tx_polling = rtl92se_tx_polling, 287 .enable_hw_sec = rtl92se_enable_hw_security_config, 288 .set_key = rtl92se_set_key, 289 .init_sw_leds = rtl92se_init_sw_leds, 290 .get_bbreg = rtl92s_phy_query_bb_reg, 291 .set_bbreg = rtl92s_phy_set_bb_reg, 292 .get_rfreg = rtl92s_phy_query_rf_reg, 293 .set_rfreg = rtl92s_phy_set_rf_reg, 294 .get_btc_status = rtl_btc_status_false, 295}; 296 297static struct rtl_mod_params rtl92se_mod_params = { 298 .sw_crypto = false, 299 .inactiveps = true, 300 .swctrl_lps = true, 301 .fwctrl_lps = false, 302 .debug = DBG_EMERG, 303}; 304 305/* Because memory R/W bursting will cause system hang/crash 306 * for 92se, so we don't read back after every write action */ 307static struct rtl_hal_cfg rtl92se_hal_cfg = { 308 .bar_id = 1, 309 .write_readback = false, 310 .name = "rtl92s_pci", 311 .fw_name = "rtlwifi/rtl8192sefw.bin", 312 .ops = &rtl8192se_hal_ops, 313 .mod_params = &rtl92se_mod_params, 314 315 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 316 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 317 .maps[SYS_CLK] = SYS_CLKR, 318 .maps[MAC_RCR_AM] = RCR_AM, 319 .maps[MAC_RCR_AB] = RCR_AB, 320 .maps[MAC_RCR_ACRC32] = RCR_ACRC32, 321 .maps[MAC_RCR_ACF] = RCR_ACF, 322 .maps[MAC_RCR_AAP] = RCR_AAP, 323 .maps[MAC_HIMR] = INTA_MASK, 324 .maps[MAC_HIMRE] = INTA_MASK + 4, 325 326 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 327 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 328 .maps[EFUSE_CLK] = REG_EFUSE_CLK, 329 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 330 .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */ 331 .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */ 332 .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */ 333 .maps[EFUSE_ANA8M] = EFUSE_ANA8M, 334 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S, 335 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 336 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 337 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, 338 339 .maps[RWCAM] = REG_RWCAM, 340 .maps[WCAMI] = REG_WCAMI, 341 .maps[RCAMO] = REG_RCAMO, 342 .maps[CAMDBG] = REG_CAMDBG, 343 .maps[SECR] = REG_SECR, 344 .maps[SEC_CAM_NONE] = CAM_NONE, 345 .maps[SEC_CAM_WEP40] = CAM_WEP40, 346 .maps[SEC_CAM_TKIP] = CAM_TKIP, 347 .maps[SEC_CAM_AES] = CAM_AES, 348 .maps[SEC_CAM_WEP104] = CAM_WEP104, 349 350 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 351 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 352 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 353 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 354 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 355 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 356 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 357 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 358 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 359 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 360 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 361 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 362 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 363 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 364 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 365 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 366 367 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 368 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 369 .maps[RTL_IMR_BCNINT] = IMR_BCNINT, 370 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 371 .maps[RTL_IMR_RDU] = IMR_RDU, 372 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 373 .maps[RTL_IMR_BDOK] = IMR_BDOK, 374 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 375 .maps[RTL_IMR_TBDER] = IMR_TBDER, 376 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 377 .maps[RTL_IMR_COMDOK] = IMR_COMDOK, 378 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 379 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 380 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 381 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 382 .maps[RTL_IMR_VODOK] = IMR_VODOK, 383 .maps[RTL_IMR_ROK] = IMR_ROK, 384 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), 385 386 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M, 387 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M, 388 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M, 389 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M, 390 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M, 391 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M, 392 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M, 393 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M, 394 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M, 395 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M, 396 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M, 397 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M, 398 399 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7, 400 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15, 401}; 402 403static struct pci_device_id rtl92se_pci_ids[] = { 404 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)}, 405 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)}, 406 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)}, 407 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)}, 408 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)}, 409 {}, 410}; 411 412MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids); 413 414MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 415MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 416MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 417MODULE_LICENSE("GPL"); 418MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless"); 419MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin"); 420 421module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444); 422module_param_named(debug, rtl92se_mod_params.debug, int, 0444); 423module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444); 424module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444); 425module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444); 426MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 427MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 428MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 429MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 430MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 431 432static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 433 434static struct pci_driver rtl92se_driver = { 435 .name = KBUILD_MODNAME, 436 .id_table = rtl92se_pci_ids, 437 .probe = rtl_pci_probe, 438 .remove = rtl_pci_disconnect, 439 .driver.pm = &rtlwifi_pm_ops, 440}; 441 442module_pci_driver(rtl92se_driver); 443