1/* 2 * Synopsys Designware PCIe host controller driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Author: Jingoo Han <jg1.han@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/irq.h> 15#include <linux/irqdomain.h> 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/msi.h> 19#include <linux/of_address.h> 20#include <linux/of_pci.h> 21#include <linux/pci.h> 22#include <linux/pci_regs.h> 23#include <linux/platform_device.h> 24#include <linux/types.h> 25 26#include "pcie-designware.h" 27 28/* Synopsis specific PCIE configuration registers */ 29#define PCIE_PORT_LINK_CONTROL 0x710 30#define PORT_LINK_MODE_MASK (0x3f << 16) 31#define PORT_LINK_MODE_1_LANES (0x1 << 16) 32#define PORT_LINK_MODE_2_LANES (0x3 << 16) 33#define PORT_LINK_MODE_4_LANES (0x7 << 16) 34 35#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 36#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 37#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) 38#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 39#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 40#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 41 42#define PCIE_MSI_ADDR_LO 0x820 43#define PCIE_MSI_ADDR_HI 0x824 44#define PCIE_MSI_INTR0_ENABLE 0x828 45#define PCIE_MSI_INTR0_MASK 0x82C 46#define PCIE_MSI_INTR0_STATUS 0x830 47 48#define PCIE_ATU_VIEWPORT 0x900 49#define PCIE_ATU_REGION_INBOUND (0x1 << 31) 50#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 51#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 52#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 53#define PCIE_ATU_CR1 0x904 54#define PCIE_ATU_TYPE_MEM (0x0 << 0) 55#define PCIE_ATU_TYPE_IO (0x2 << 0) 56#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 57#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 58#define PCIE_ATU_CR2 0x908 59#define PCIE_ATU_ENABLE (0x1 << 31) 60#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 61#define PCIE_ATU_LOWER_BASE 0x90C 62#define PCIE_ATU_UPPER_BASE 0x910 63#define PCIE_ATU_LIMIT 0x914 64#define PCIE_ATU_LOWER_TARGET 0x918 65#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 66#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 67#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 68#define PCIE_ATU_UPPER_TARGET 0x91C 69 70static struct hw_pci dw_pci; 71 72static unsigned long global_io_offset; 73 74static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) 75{ 76 BUG_ON(!sys->private_data); 77 78 return sys->private_data; 79} 80 81int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) 82{ 83 *val = readl(addr); 84 85 if (size == 1) 86 *val = (*val >> (8 * (where & 3))) & 0xff; 87 else if (size == 2) 88 *val = (*val >> (8 * (where & 3))) & 0xffff; 89 else if (size != 4) 90 return PCIBIOS_BAD_REGISTER_NUMBER; 91 92 return PCIBIOS_SUCCESSFUL; 93} 94 95int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) 96{ 97 if (size == 4) 98 writel(val, addr); 99 else if (size == 2) 100 writew(val, addr + (where & 2)); 101 else if (size == 1) 102 writeb(val, addr + (where & 3)); 103 else 104 return PCIBIOS_BAD_REGISTER_NUMBER; 105 106 return PCIBIOS_SUCCESSFUL; 107} 108 109static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) 110{ 111 if (pp->ops->readl_rc) 112 pp->ops->readl_rc(pp, pp->dbi_base + reg, val); 113 else 114 *val = readl(pp->dbi_base + reg); 115} 116 117static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) 118{ 119 if (pp->ops->writel_rc) 120 pp->ops->writel_rc(pp, val, pp->dbi_base + reg); 121 else 122 writel(val, pp->dbi_base + reg); 123} 124 125static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 126 u32 *val) 127{ 128 int ret; 129 130 if (pp->ops->rd_own_conf) 131 ret = pp->ops->rd_own_conf(pp, where, size, val); 132 else 133 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 134 size, val); 135 136 return ret; 137} 138 139static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 140 u32 val) 141{ 142 int ret; 143 144 if (pp->ops->wr_own_conf) 145 ret = pp->ops->wr_own_conf(pp, where, size, val); 146 else 147 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, 148 size, val); 149 150 return ret; 151} 152 153static struct irq_chip dw_msi_irq_chip = { 154 .name = "PCI-MSI", 155 .irq_enable = unmask_msi_irq, 156 .irq_disable = mask_msi_irq, 157 .irq_mask = mask_msi_irq, 158 .irq_unmask = unmask_msi_irq, 159}; 160 161/* MSI int handler */ 162irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 163{ 164 unsigned long val; 165 int i, pos, irq; 166 irqreturn_t ret = IRQ_NONE; 167 168 for (i = 0; i < MAX_MSI_CTRLS; i++) { 169 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, 170 (u32 *)&val); 171 if (val) { 172 ret = IRQ_HANDLED; 173 pos = 0; 174 while ((pos = find_next_bit(&val, 32, pos)) != 32) { 175 irq = irq_find_mapping(pp->irq_domain, 176 i * 32 + pos); 177 dw_pcie_wr_own_conf(pp, 178 PCIE_MSI_INTR0_STATUS + i * 12, 179 4, 1 << pos); 180 generic_handle_irq(irq); 181 pos++; 182 } 183 } 184 } 185 186 return ret; 187} 188 189void dw_pcie_msi_init(struct pcie_port *pp) 190{ 191 pp->msi_data = __get_free_pages(GFP_KERNEL, 0); 192 193 /* program the msi_data */ 194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, 195 virt_to_phys((void *)pp->msi_data)); 196 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); 197} 198 199static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) 200{ 201 unsigned int res, bit, val; 202 203 res = (irq / 32) * 12; 204 bit = irq % 32; 205 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); 206 val &= ~(1 << bit); 207 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); 208} 209 210static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, 211 unsigned int nvec, unsigned int pos) 212{ 213 unsigned int i; 214 215 for (i = 0; i < nvec; i++) { 216 irq_set_msi_desc_off(irq_base, i, NULL); 217 /* Disable corresponding interrupt on MSI controller */ 218 if (pp->ops->msi_clear_irq) 219 pp->ops->msi_clear_irq(pp, pos + i); 220 else 221 dw_pcie_msi_clear_irq(pp, pos + i); 222 } 223 224 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); 225} 226 227static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) 228{ 229 unsigned int res, bit, val; 230 231 res = (irq / 32) * 12; 232 bit = irq % 32; 233 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); 234 val |= 1 << bit; 235 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); 236} 237 238static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) 239{ 240 int irq, pos0, i; 241 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); 242 243 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, 244 order_base_2(no_irqs)); 245 if (pos0 < 0) 246 goto no_valid_irq; 247 248 irq = irq_find_mapping(pp->irq_domain, pos0); 249 if (!irq) 250 goto no_valid_irq; 251 252 /* 253 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates 254 * descs so there is no need to allocate descs here. We can therefore 255 * assume that if irq_find_mapping above returns non-zero, then the 256 * descs are also successfully allocated. 257 */ 258 259 for (i = 0; i < no_irqs; i++) { 260 if (irq_set_msi_desc_off(irq, i, desc) != 0) { 261 clear_irq_range(pp, irq, i, pos0); 262 goto no_valid_irq; 263 } 264 /*Enable corresponding interrupt in MSI interrupt controller */ 265 if (pp->ops->msi_set_irq) 266 pp->ops->msi_set_irq(pp, pos0 + i); 267 else 268 dw_pcie_msi_set_irq(pp, pos0 + i); 269 } 270 271 *pos = pos0; 272 return irq; 273 274no_valid_irq: 275 *pos = pos0; 276 return -ENOSPC; 277} 278 279static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, 280 struct msi_desc *desc) 281{ 282 int irq, pos; 283 struct msi_msg msg; 284 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); 285 286 irq = assign_irq(1, desc, &pos); 287 if (irq < 0) 288 return irq; 289 290 if (pp->ops->get_msi_addr) 291 msg.address_lo = pp->ops->get_msi_addr(pp); 292 else 293 msg.address_lo = virt_to_phys((void *)pp->msi_data); 294 msg.address_hi = 0x0; 295 296 if (pp->ops->get_msi_data) 297 msg.data = pp->ops->get_msi_data(pp, pos); 298 else 299 msg.data = pos; 300 301 write_msi_msg(irq, &msg); 302 303 return 0; 304} 305 306static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq) 307{ 308 struct irq_data *data = irq_get_irq_data(irq); 309 struct msi_desc *msi = irq_data_get_msi(data); 310 struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); 311 312 clear_irq_range(pp, irq, 1, data->hwirq); 313} 314 315static struct msi_chip dw_pcie_msi_chip = { 316 .setup_irq = dw_msi_setup_irq, 317 .teardown_irq = dw_msi_teardown_irq, 318}; 319 320int dw_pcie_link_up(struct pcie_port *pp) 321{ 322 if (pp->ops->link_up) 323 return pp->ops->link_up(pp); 324 else 325 return 0; 326} 327 328static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, 329 irq_hw_number_t hwirq) 330{ 331 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); 332 irq_set_chip_data(irq, domain->host_data); 333 set_irq_flags(irq, IRQF_VALID); 334 335 return 0; 336} 337 338static const struct irq_domain_ops msi_domain_ops = { 339 .map = dw_pcie_msi_map, 340}; 341 342int __init dw_pcie_host_init(struct pcie_port *pp) 343{ 344 struct device_node *np = pp->dev->of_node; 345 struct platform_device *pdev = to_platform_device(pp->dev); 346 struct of_pci_range range; 347 struct of_pci_range_parser parser; 348 struct resource *cfg_res; 349 u32 val, na, ns; 350 const __be32 *addrp; 351 int i, index, ret; 352 353 /* Find the address cell size and the number of cells in order to get 354 * the untranslated address. 355 */ 356 of_property_read_u32(np, "#address-cells", &na); 357 ns = of_n_size_cells(np); 358 359 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 360 if (cfg_res) { 361 pp->cfg0_size = resource_size(cfg_res)/2; 362 pp->cfg1_size = resource_size(cfg_res)/2; 363 pp->cfg0_base = cfg_res->start; 364 pp->cfg1_base = cfg_res->start + pp->cfg0_size; 365 366 /* Find the untranslated configuration space address */ 367 index = of_property_match_string(np, "reg-names", "config"); 368 addrp = of_get_address(np, index, NULL, NULL); 369 pp->cfg0_mod_base = of_read_number(addrp, ns); 370 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; 371 } else { 372 dev_err(pp->dev, "missing *config* reg space\n"); 373 } 374 375 if (of_pci_range_parser_init(&parser, np)) { 376 dev_err(pp->dev, "missing ranges property\n"); 377 return -EINVAL; 378 } 379 380 /* Get the I/O and memory ranges from DT */ 381 for_each_of_pci_range(&parser, &range) { 382 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; 383 if (restype == IORESOURCE_IO) { 384 of_pci_range_to_resource(&range, np, &pp->io); 385 pp->io.name = "I/O"; 386 pp->io.start = max_t(resource_size_t, 387 PCIBIOS_MIN_IO, 388 range.pci_addr + global_io_offset); 389 pp->io.end = min_t(resource_size_t, 390 IO_SPACE_LIMIT, 391 range.pci_addr + range.size 392 + global_io_offset - 1); 393 pp->io_size = resource_size(&pp->io); 394 pp->io_bus_addr = range.pci_addr; 395 pp->io_base = range.cpu_addr; 396 397 /* Find the untranslated IO space address */ 398 pp->io_mod_base = of_read_number(parser.range - 399 parser.np + na, ns); 400 } 401 if (restype == IORESOURCE_MEM) { 402 of_pci_range_to_resource(&range, np, &pp->mem); 403 pp->mem.name = "MEM"; 404 pp->mem_size = resource_size(&pp->mem); 405 pp->mem_bus_addr = range.pci_addr; 406 407 /* Find the untranslated MEM space address */ 408 pp->mem_mod_base = of_read_number(parser.range - 409 parser.np + na, ns); 410 } 411 if (restype == 0) { 412 of_pci_range_to_resource(&range, np, &pp->cfg); 413 pp->cfg0_size = resource_size(&pp->cfg)/2; 414 pp->cfg1_size = resource_size(&pp->cfg)/2; 415 pp->cfg0_base = pp->cfg.start; 416 pp->cfg1_base = pp->cfg.start + pp->cfg0_size; 417 418 /* Find the untranslated configuration space address */ 419 pp->cfg0_mod_base = of_read_number(parser.range - 420 parser.np + na, ns); 421 pp->cfg1_mod_base = pp->cfg0_mod_base + 422 pp->cfg0_size; 423 } 424 } 425 426 ret = of_pci_parse_bus_range(np, &pp->busn); 427 if (ret < 0) { 428 pp->busn.name = np->name; 429 pp->busn.start = 0; 430 pp->busn.end = 0xff; 431 pp->busn.flags = IORESOURCE_BUS; 432 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n", 433 ret, &pp->busn); 434 } 435 436 if (!pp->dbi_base) { 437 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, 438 resource_size(&pp->cfg)); 439 if (!pp->dbi_base) { 440 dev_err(pp->dev, "error with ioremap\n"); 441 return -ENOMEM; 442 } 443 } 444 445 pp->mem_base = pp->mem.start; 446 447 if (!pp->va_cfg0_base) { 448 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, 449 pp->cfg0_size); 450 if (!pp->va_cfg0_base) { 451 dev_err(pp->dev, "error with ioremap in function\n"); 452 return -ENOMEM; 453 } 454 } 455 456 if (!pp->va_cfg1_base) { 457 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, 458 pp->cfg1_size); 459 if (!pp->va_cfg1_base) { 460 dev_err(pp->dev, "error with ioremap\n"); 461 return -ENOMEM; 462 } 463 } 464 465 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { 466 dev_err(pp->dev, "Failed to parse the number of lanes\n"); 467 return -EINVAL; 468 } 469 470 if (IS_ENABLED(CONFIG_PCI_MSI)) { 471 if (!pp->ops->msi_host_init) { 472 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, 473 MAX_MSI_IRQS, &msi_domain_ops, 474 &dw_pcie_msi_chip); 475 if (!pp->irq_domain) { 476 dev_err(pp->dev, "irq domain init failed\n"); 477 return -ENXIO; 478 } 479 480 for (i = 0; i < MAX_MSI_IRQS; i++) 481 irq_create_mapping(pp->irq_domain, i); 482 } else { 483 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); 484 if (ret < 0) 485 return ret; 486 } 487 } 488 489 if (pp->ops->host_init) 490 pp->ops->host_init(pp); 491 492 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); 493 494 /* program correct class for RC */ 495 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); 496 497 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); 498 val |= PORT_LOGIC_SPEED_CHANGE; 499 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); 500 501 dw_pci.nr_controllers = 1; 502 dw_pci.private_data = (void **)&pp; 503 504 pci_common_init_dev(pp->dev, &dw_pci); 505#ifdef CONFIG_PCI_DOMAINS 506 dw_pci.domain++; 507#endif 508 509 return 0; 510} 511 512static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) 513{ 514 /* Program viewport 0 : OUTBOUND : CFG0 */ 515 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 516 PCIE_ATU_VIEWPORT); 517 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE); 518 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE); 519 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1, 520 PCIE_ATU_LIMIT); 521 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); 522 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); 523 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1); 524 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 525} 526 527static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) 528{ 529 /* Program viewport 1 : OUTBOUND : CFG1 */ 530 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 531 PCIE_ATU_VIEWPORT); 532 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); 533 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE); 534 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE); 535 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1, 536 PCIE_ATU_LIMIT); 537 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); 538 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); 539 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 540} 541 542static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) 543{ 544 /* Program viewport 0 : OUTBOUND : MEM */ 545 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 546 PCIE_ATU_VIEWPORT); 547 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); 548 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE); 549 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE); 550 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1, 551 PCIE_ATU_LIMIT); 552 dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET); 553 dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr), 554 PCIE_ATU_UPPER_TARGET); 555 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 556} 557 558static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) 559{ 560 /* Program viewport 1 : OUTBOUND : IO */ 561 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 562 PCIE_ATU_VIEWPORT); 563 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); 564 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE); 565 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE); 566 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1, 567 PCIE_ATU_LIMIT); 568 dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET); 569 dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr), 570 PCIE_ATU_UPPER_TARGET); 571 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 572} 573 574static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 575 u32 devfn, int where, int size, u32 *val) 576{ 577 int ret = PCIBIOS_SUCCESSFUL; 578 u32 address, busdev; 579 580 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 581 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 582 address = where & ~0x3; 583 584 if (bus->parent->number == pp->root_bus_nr) { 585 dw_pcie_prog_viewport_cfg0(pp, busdev); 586 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, 587 val); 588 dw_pcie_prog_viewport_mem_outbound(pp); 589 } else { 590 dw_pcie_prog_viewport_cfg1(pp, busdev); 591 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, 592 val); 593 dw_pcie_prog_viewport_io_outbound(pp); 594 } 595 596 return ret; 597} 598 599static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 600 u32 devfn, int where, int size, u32 val) 601{ 602 int ret = PCIBIOS_SUCCESSFUL; 603 u32 address, busdev; 604 605 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 606 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 607 address = where & ~0x3; 608 609 if (bus->parent->number == pp->root_bus_nr) { 610 dw_pcie_prog_viewport_cfg0(pp, busdev); 611 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, 612 val); 613 dw_pcie_prog_viewport_mem_outbound(pp); 614 } else { 615 dw_pcie_prog_viewport_cfg1(pp, busdev); 616 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, 617 val); 618 dw_pcie_prog_viewport_io_outbound(pp); 619 } 620 621 return ret; 622} 623 624static int dw_pcie_valid_config(struct pcie_port *pp, 625 struct pci_bus *bus, int dev) 626{ 627 /* If there is no link, then there is no device */ 628 if (bus->number != pp->root_bus_nr) { 629 if (!dw_pcie_link_up(pp)) 630 return 0; 631 } 632 633 /* access only one slot on each root port */ 634 if (bus->number == pp->root_bus_nr && dev > 0) 635 return 0; 636 637 /* 638 * do not read more than one device on the bus directly attached 639 * to RC's (Virtual Bridge's) DS side. 640 */ 641 if (bus->primary == pp->root_bus_nr && dev > 0) 642 return 0; 643 644 return 1; 645} 646 647static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 648 int size, u32 *val) 649{ 650 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 651 int ret; 652 653 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { 654 *val = 0xffffffff; 655 return PCIBIOS_DEVICE_NOT_FOUND; 656 } 657 658 if (bus->number != pp->root_bus_nr) 659 if (pp->ops->rd_other_conf) 660 ret = pp->ops->rd_other_conf(pp, bus, devfn, 661 where, size, val); 662 else 663 ret = dw_pcie_rd_other_conf(pp, bus, devfn, 664 where, size, val); 665 else 666 ret = dw_pcie_rd_own_conf(pp, where, size, val); 667 668 return ret; 669} 670 671static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 672 int where, int size, u32 val) 673{ 674 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 675 int ret; 676 677 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) 678 return PCIBIOS_DEVICE_NOT_FOUND; 679 680 if (bus->number != pp->root_bus_nr) 681 if (pp->ops->wr_other_conf) 682 ret = pp->ops->wr_other_conf(pp, bus, devfn, 683 where, size, val); 684 else 685 ret = dw_pcie_wr_other_conf(pp, bus, devfn, 686 where, size, val); 687 else 688 ret = dw_pcie_wr_own_conf(pp, where, size, val); 689 690 return ret; 691} 692 693static struct pci_ops dw_pcie_ops = { 694 .read = dw_pcie_rd_conf, 695 .write = dw_pcie_wr_conf, 696}; 697 698static int dw_pcie_setup(int nr, struct pci_sys_data *sys) 699{ 700 struct pcie_port *pp; 701 702 pp = sys_to_pcie(sys); 703 704 if (global_io_offset < SZ_1M && pp->io_size > 0) { 705 sys->io_offset = global_io_offset - pp->io_bus_addr; 706 pci_ioremap_io(global_io_offset, pp->io_base); 707 global_io_offset += SZ_64K; 708 pci_add_resource_offset(&sys->resources, &pp->io, 709 sys->io_offset); 710 } 711 712 sys->mem_offset = pp->mem.start - pp->mem_bus_addr; 713 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); 714 pci_add_resource(&sys->resources, &pp->busn); 715 716 return 1; 717} 718 719static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) 720{ 721 struct pci_bus *bus; 722 struct pcie_port *pp = sys_to_pcie(sys); 723 724 pp->root_bus_nr = sys->busnr; 725 bus = pci_create_root_bus(pp->dev, sys->busnr, 726 &dw_pcie_ops, sys, &sys->resources); 727 if (!bus) 728 return NULL; 729 730 pci_scan_child_bus(bus); 731 732 if (bus && pp->ops->scan_bus) 733 pp->ops->scan_bus(pp); 734 735 return bus; 736} 737 738static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 739{ 740 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); 741 int irq; 742 743 irq = of_irq_parse_and_map_pci(dev, slot, pin); 744 if (!irq) 745 irq = pp->irq; 746 747 return irq; 748} 749 750static void dw_pcie_add_bus(struct pci_bus *bus) 751{ 752 if (IS_ENABLED(CONFIG_PCI_MSI)) { 753 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 754 755 dw_pcie_msi_chip.dev = pp->dev; 756 bus->msi = &dw_pcie_msi_chip; 757 } 758} 759 760static struct hw_pci dw_pci = { 761 .setup = dw_pcie_setup, 762 .scan = dw_pcie_scan_bus, 763 .map_irq = dw_pcie_map_irq, 764 .add_bus = dw_pcie_add_bus, 765}; 766 767void dw_pcie_setup_rc(struct pcie_port *pp) 768{ 769 u32 val; 770 u32 membase; 771 u32 memlimit; 772 773 /* set the number of lanes */ 774 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); 775 val &= ~PORT_LINK_MODE_MASK; 776 switch (pp->lanes) { 777 case 1: 778 val |= PORT_LINK_MODE_1_LANES; 779 break; 780 case 2: 781 val |= PORT_LINK_MODE_2_LANES; 782 break; 783 case 4: 784 val |= PORT_LINK_MODE_4_LANES; 785 break; 786 } 787 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); 788 789 /* set link width speed control register */ 790 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); 791 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 792 switch (pp->lanes) { 793 case 1: 794 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 795 break; 796 case 2: 797 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 798 break; 799 case 4: 800 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 801 break; 802 } 803 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); 804 805 /* setup RC BARs */ 806 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); 807 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); 808 809 /* setup interrupt pins */ 810 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); 811 val &= 0xffff00ff; 812 val |= 0x00000100; 813 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); 814 815 /* setup bus numbers */ 816 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); 817 val &= 0xff000000; 818 val |= 0x00010100; 819 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); 820 821 /* setup memory base, memory limit */ 822 membase = ((u32)pp->mem_base & 0xfff00000) >> 16; 823 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000; 824 val = memlimit | membase; 825 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); 826 827 /* setup command register */ 828 dw_pcie_readl_rc(pp, PCI_COMMAND, &val); 829 val &= 0xffff0000; 830 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 831 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 832 dw_pcie_writel_rc(pp, val, PCI_COMMAND); 833} 834 835MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 836MODULE_DESCRIPTION("Designware PCIe host controller driver"); 837MODULE_LICENSE("GPL v2"); 838