pcie-designware.c revision 66c5c34bf80c28d370eb9bcf30153ea0304a288a
1/* 2 * Synopsys Designware PCIe host controller driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Author: Jingoo Han <jg1.han@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/irq.h> 15#include <linux/irqdomain.h> 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/msi.h> 19#include <linux/of_address.h> 20#include <linux/pci.h> 21#include <linux/pci_regs.h> 22#include <linux/types.h> 23 24#include "pcie-designware.h" 25 26/* Synopsis specific PCIE configuration registers */ 27#define PCIE_PORT_LINK_CONTROL 0x710 28#define PORT_LINK_MODE_MASK (0x3f << 16) 29#define PORT_LINK_MODE_1_LANES (0x1 << 16) 30#define PORT_LINK_MODE_2_LANES (0x3 << 16) 31#define PORT_LINK_MODE_4_LANES (0x7 << 16) 32 33#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 34#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 35#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) 36#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 37#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 38#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 39 40#define PCIE_MSI_ADDR_LO 0x820 41#define PCIE_MSI_ADDR_HI 0x824 42#define PCIE_MSI_INTR0_ENABLE 0x828 43#define PCIE_MSI_INTR0_MASK 0x82C 44#define PCIE_MSI_INTR0_STATUS 0x830 45 46#define PCIE_ATU_VIEWPORT 0x900 47#define PCIE_ATU_REGION_INBOUND (0x1 << 31) 48#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 49#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 50#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 51#define PCIE_ATU_CR1 0x904 52#define PCIE_ATU_TYPE_MEM (0x0 << 0) 53#define PCIE_ATU_TYPE_IO (0x2 << 0) 54#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 55#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 56#define PCIE_ATU_CR2 0x908 57#define PCIE_ATU_ENABLE (0x1 << 31) 58#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 59#define PCIE_ATU_LOWER_BASE 0x90C 60#define PCIE_ATU_UPPER_BASE 0x910 61#define PCIE_ATU_LIMIT 0x914 62#define PCIE_ATU_LOWER_TARGET 0x918 63#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 64#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 65#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 66#define PCIE_ATU_UPPER_TARGET 0x91C 67 68static struct hw_pci dw_pci; 69 70static unsigned long global_io_offset; 71 72static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) 73{ 74 return sys->private_data; 75} 76 77int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) 78{ 79 *val = readl(addr); 80 81 if (size == 1) 82 *val = (*val >> (8 * (where & 3))) & 0xff; 83 else if (size == 2) 84 *val = (*val >> (8 * (where & 3))) & 0xffff; 85 else if (size != 4) 86 return PCIBIOS_BAD_REGISTER_NUMBER; 87 88 return PCIBIOS_SUCCESSFUL; 89} 90 91int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) 92{ 93 if (size == 4) 94 writel(val, addr); 95 else if (size == 2) 96 writew(val, addr + (where & 2)); 97 else if (size == 1) 98 writeb(val, addr + (where & 3)); 99 else 100 return PCIBIOS_BAD_REGISTER_NUMBER; 101 102 return PCIBIOS_SUCCESSFUL; 103} 104 105static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) 106{ 107 if (pp->ops->readl_rc) 108 pp->ops->readl_rc(pp, pp->dbi_base + reg, val); 109 else 110 *val = readl(pp->dbi_base + reg); 111} 112 113static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) 114{ 115 if (pp->ops->writel_rc) 116 pp->ops->writel_rc(pp, val, pp->dbi_base + reg); 117 else 118 writel(val, pp->dbi_base + reg); 119} 120 121static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 122 u32 *val) 123{ 124 int ret; 125 126 if (pp->ops->rd_own_conf) 127 ret = pp->ops->rd_own_conf(pp, where, size, val); 128 else 129 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 130 size, val); 131 132 return ret; 133} 134 135static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 136 u32 val) 137{ 138 int ret; 139 140 if (pp->ops->wr_own_conf) 141 ret = pp->ops->wr_own_conf(pp, where, size, val); 142 else 143 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, 144 size, val); 145 146 return ret; 147} 148 149static struct irq_chip dw_msi_irq_chip = { 150 .name = "PCI-MSI", 151 .irq_enable = unmask_msi_irq, 152 .irq_disable = mask_msi_irq, 153 .irq_mask = mask_msi_irq, 154 .irq_unmask = unmask_msi_irq, 155}; 156 157/* MSI int handler */ 158void dw_handle_msi_irq(struct pcie_port *pp) 159{ 160 unsigned long val; 161 int i, pos, irq; 162 163 for (i = 0; i < MAX_MSI_CTRLS; i++) { 164 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, 165 (u32 *)&val); 166 if (val) { 167 pos = 0; 168 while ((pos = find_next_bit(&val, 32, pos)) != 32) { 169 irq = irq_find_mapping(pp->irq_domain, 170 i * 32 + pos); 171 dw_pcie_wr_own_conf(pp, 172 PCIE_MSI_INTR0_STATUS + i * 12, 173 4, 1 << pos); 174 generic_handle_irq(irq); 175 pos++; 176 } 177 } 178 } 179} 180 181void dw_pcie_msi_init(struct pcie_port *pp) 182{ 183 pp->msi_data = __get_free_pages(GFP_KERNEL, 0); 184 185 /* program the msi_data */ 186 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, 187 virt_to_phys((void *)pp->msi_data)); 188 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); 189} 190 191static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) 192{ 193 int flag = 1; 194 195 do { 196 pos = find_next_zero_bit(pp->msi_irq_in_use, 197 MAX_MSI_IRQS, pos); 198 /*if you have reached to the end then get out from here.*/ 199 if (pos == MAX_MSI_IRQS) 200 return -ENOSPC; 201 /* 202 * Check if this position is at correct offset.nvec is always a 203 * power of two. pos0 must be nvec bit aligned. 204 */ 205 if (pos % msgvec) 206 pos += msgvec - (pos % msgvec); 207 else 208 flag = 0; 209 } while (flag); 210 211 *pos0 = pos; 212 return 0; 213} 214 215static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, 216 unsigned int nvec, unsigned int pos) 217{ 218 unsigned int i, res, bit, val; 219 220 for (i = 0; i < nvec; i++) { 221 irq_set_msi_desc_off(irq_base, i, NULL); 222 clear_bit(pos + i, pp->msi_irq_in_use); 223 /* Disable corresponding interrupt on MSI controller */ 224 res = ((pos + i) / 32) * 12; 225 bit = (pos + i) % 32; 226 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); 227 val &= ~(1 << bit); 228 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); 229 } 230} 231 232static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) 233{ 234 int res, bit, irq, pos0, pos1, i; 235 u32 val; 236 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); 237 238 if (!pp) { 239 BUG(); 240 return -EINVAL; 241 } 242 243 pos0 = find_first_zero_bit(pp->msi_irq_in_use, 244 MAX_MSI_IRQS); 245 if (pos0 % no_irqs) { 246 if (find_valid_pos0(pp, no_irqs, pos0, &pos0)) 247 goto no_valid_irq; 248 } 249 if (no_irqs > 1) { 250 pos1 = find_next_bit(pp->msi_irq_in_use, 251 MAX_MSI_IRQS, pos0); 252 /* there must be nvec number of consecutive free bits */ 253 while ((pos1 - pos0) < no_irqs) { 254 if (find_valid_pos0(pp, no_irqs, pos1, &pos0)) 255 goto no_valid_irq; 256 pos1 = find_next_bit(pp->msi_irq_in_use, 257 MAX_MSI_IRQS, pos0); 258 } 259 } 260 261 irq = irq_find_mapping(pp->irq_domain, pos0); 262 if (!irq) 263 goto no_valid_irq; 264 265 /* 266 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates 267 * descs so there is no need to allocate descs here. We can therefore 268 * assume that if irq_find_mapping above returns non-zero, then the 269 * descs are also successfully allocated. 270 */ 271 272 for (i = 0; i < no_irqs; i++) { 273 if (irq_set_msi_desc_off(irq, i, desc) != 0) { 274 clear_irq_range(pp, irq, i, pos0); 275 goto no_valid_irq; 276 } 277 set_bit(pos0 + i, pp->msi_irq_in_use); 278 /*Enable corresponding interrupt in MSI interrupt controller */ 279 res = ((pos0 + i) / 32) * 12; 280 bit = (pos0 + i) % 32; 281 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); 282 val |= 1 << bit; 283 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); 284 } 285 286 *pos = pos0; 287 return irq; 288 289no_valid_irq: 290 *pos = pos0; 291 return -ENOSPC; 292} 293 294static void clear_irq(unsigned int irq) 295{ 296 unsigned int pos, nvec; 297 struct msi_desc *msi; 298 struct pcie_port *pp; 299 struct irq_data *data = irq_get_irq_data(irq); 300 301 /* get the port structure */ 302 msi = irq_data_get_msi(data); 303 pp = sys_to_pcie(msi->dev->bus->sysdata); 304 if (!pp) { 305 BUG(); 306 return; 307 } 308 309 /* undo what was done in assign_irq */ 310 pos = data->hwirq; 311 nvec = 1 << msi->msi_attrib.multiple; 312 313 clear_irq_range(pp, irq, nvec, pos); 314 315 /* all irqs cleared; reset attributes */ 316 msi->irq = 0; 317 msi->msi_attrib.multiple = 0; 318} 319 320static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, 321 struct msi_desc *desc) 322{ 323 int irq, pos, msgvec; 324 u16 msg_ctr; 325 struct msi_msg msg; 326 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); 327 328 if (!pp) { 329 BUG(); 330 return -EINVAL; 331 } 332 333 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS, 334 &msg_ctr); 335 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4; 336 if (msgvec == 0) 337 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1; 338 if (msgvec > 5) 339 msgvec = 0; 340 341 irq = assign_irq((1 << msgvec), desc, &pos); 342 if (irq < 0) 343 return irq; 344 345 /* 346 * write_msi_msg() will update PCI_MSI_FLAGS so there is 347 * no need to explicitly call pci_write_config_word(). 348 */ 349 desc->msi_attrib.multiple = msgvec; 350 351 msg.address_lo = virt_to_phys((void *)pp->msi_data); 352 msg.address_hi = 0x0; 353 msg.data = pos; 354 write_msi_msg(irq, &msg); 355 356 return 0; 357} 358 359static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq) 360{ 361 clear_irq(irq); 362} 363 364static struct msi_chip dw_pcie_msi_chip = { 365 .setup_irq = dw_msi_setup_irq, 366 .teardown_irq = dw_msi_teardown_irq, 367}; 368 369int dw_pcie_link_up(struct pcie_port *pp) 370{ 371 if (pp->ops->link_up) 372 return pp->ops->link_up(pp); 373 else 374 return 0; 375} 376 377static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, 378 irq_hw_number_t hwirq) 379{ 380 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); 381 irq_set_chip_data(irq, domain->host_data); 382 set_irq_flags(irq, IRQF_VALID); 383 384 return 0; 385} 386 387static const struct irq_domain_ops msi_domain_ops = { 388 .map = dw_pcie_msi_map, 389}; 390 391int __init dw_pcie_host_init(struct pcie_port *pp) 392{ 393 struct device_node *np = pp->dev->of_node; 394 struct of_pci_range range; 395 struct of_pci_range_parser parser; 396 u32 val; 397 int i; 398 399 if (of_pci_range_parser_init(&parser, np)) { 400 dev_err(pp->dev, "missing ranges property\n"); 401 return -EINVAL; 402 } 403 404 /* Get the I/O and memory ranges from DT */ 405 for_each_of_pci_range(&parser, &range) { 406 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; 407 if (restype == IORESOURCE_IO) { 408 of_pci_range_to_resource(&range, np, &pp->io); 409 pp->io.name = "I/O"; 410 pp->io.start = max_t(resource_size_t, 411 PCIBIOS_MIN_IO, 412 range.pci_addr + global_io_offset); 413 pp->io.end = min_t(resource_size_t, 414 IO_SPACE_LIMIT, 415 range.pci_addr + range.size 416 + global_io_offset); 417 pp->config.io_size = resource_size(&pp->io); 418 pp->config.io_bus_addr = range.pci_addr; 419 pp->io_base = range.cpu_addr; 420 } 421 if (restype == IORESOURCE_MEM) { 422 of_pci_range_to_resource(&range, np, &pp->mem); 423 pp->mem.name = "MEM"; 424 pp->config.mem_size = resource_size(&pp->mem); 425 pp->config.mem_bus_addr = range.pci_addr; 426 } 427 if (restype == 0) { 428 of_pci_range_to_resource(&range, np, &pp->cfg); 429 pp->config.cfg0_size = resource_size(&pp->cfg)/2; 430 pp->config.cfg1_size = resource_size(&pp->cfg)/2; 431 } 432 } 433 434 if (!pp->dbi_base) { 435 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, 436 resource_size(&pp->cfg)); 437 if (!pp->dbi_base) { 438 dev_err(pp->dev, "error with ioremap\n"); 439 return -ENOMEM; 440 } 441 } 442 443 pp->cfg0_base = pp->cfg.start; 444 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; 445 pp->mem_base = pp->mem.start; 446 447 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, 448 pp->config.cfg0_size); 449 if (!pp->va_cfg0_base) { 450 dev_err(pp->dev, "error with ioremap in function\n"); 451 return -ENOMEM; 452 } 453 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, 454 pp->config.cfg1_size); 455 if (!pp->va_cfg1_base) { 456 dev_err(pp->dev, "error with ioremap\n"); 457 return -ENOMEM; 458 } 459 460 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { 461 dev_err(pp->dev, "Failed to parse the number of lanes\n"); 462 return -EINVAL; 463 } 464 465 if (IS_ENABLED(CONFIG_PCI_MSI)) { 466 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, 467 MAX_MSI_IRQS, &msi_domain_ops, 468 &dw_pcie_msi_chip); 469 if (!pp->irq_domain) { 470 dev_err(pp->dev, "irq domain init failed\n"); 471 return -ENXIO; 472 } 473 474 for (i = 0; i < MAX_MSI_IRQS; i++) 475 irq_create_mapping(pp->irq_domain, i); 476 } 477 478 if (pp->ops->host_init) 479 pp->ops->host_init(pp); 480 481 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); 482 483 /* program correct class for RC */ 484 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); 485 486 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); 487 val |= PORT_LOGIC_SPEED_CHANGE; 488 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); 489 490 dw_pci.nr_controllers = 1; 491 dw_pci.private_data = (void **)&pp; 492 493 pci_common_init(&dw_pci); 494 pci_assign_unassigned_resources(); 495#ifdef CONFIG_PCI_DOMAINS 496 dw_pci.domain++; 497#endif 498 499 return 0; 500} 501 502static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) 503{ 504 /* Program viewport 0 : OUTBOUND : CFG0 */ 505 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 506 PCIE_ATU_VIEWPORT); 507 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE); 508 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE); 509 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1, 510 PCIE_ATU_LIMIT); 511 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); 512 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); 513 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1); 514 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 515} 516 517static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) 518{ 519 /* Program viewport 1 : OUTBOUND : CFG1 */ 520 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 521 PCIE_ATU_VIEWPORT); 522 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); 523 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 524 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE); 525 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE); 526 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1, 527 PCIE_ATU_LIMIT); 528 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); 529 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); 530} 531 532static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) 533{ 534 /* Program viewport 0 : OUTBOUND : MEM */ 535 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 536 PCIE_ATU_VIEWPORT); 537 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); 538 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 539 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE); 540 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE); 541 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, 542 PCIE_ATU_LIMIT); 543 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); 544 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), 545 PCIE_ATU_UPPER_TARGET); 546} 547 548static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) 549{ 550 /* Program viewport 1 : OUTBOUND : IO */ 551 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 552 PCIE_ATU_VIEWPORT); 553 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); 554 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 555 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE); 556 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE); 557 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, 558 PCIE_ATU_LIMIT); 559 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); 560 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), 561 PCIE_ATU_UPPER_TARGET); 562} 563 564static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 565 u32 devfn, int where, int size, u32 *val) 566{ 567 int ret = PCIBIOS_SUCCESSFUL; 568 u32 address, busdev; 569 570 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 571 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 572 address = where & ~0x3; 573 574 if (bus->parent->number == pp->root_bus_nr) { 575 dw_pcie_prog_viewport_cfg0(pp, busdev); 576 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, 577 val); 578 dw_pcie_prog_viewport_mem_outbound(pp); 579 } else { 580 dw_pcie_prog_viewport_cfg1(pp, busdev); 581 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, 582 val); 583 dw_pcie_prog_viewport_io_outbound(pp); 584 } 585 586 return ret; 587} 588 589static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 590 u32 devfn, int where, int size, u32 val) 591{ 592 int ret = PCIBIOS_SUCCESSFUL; 593 u32 address, busdev; 594 595 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 596 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 597 address = where & ~0x3; 598 599 if (bus->parent->number == pp->root_bus_nr) { 600 dw_pcie_prog_viewport_cfg0(pp, busdev); 601 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, 602 val); 603 dw_pcie_prog_viewport_mem_outbound(pp); 604 } else { 605 dw_pcie_prog_viewport_cfg1(pp, busdev); 606 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, 607 val); 608 dw_pcie_prog_viewport_io_outbound(pp); 609 } 610 611 return ret; 612} 613 614static int dw_pcie_valid_config(struct pcie_port *pp, 615 struct pci_bus *bus, int dev) 616{ 617 /* If there is no link, then there is no device */ 618 if (bus->number != pp->root_bus_nr) { 619 if (!dw_pcie_link_up(pp)) 620 return 0; 621 } 622 623 /* access only one slot on each root port */ 624 if (bus->number == pp->root_bus_nr && dev > 0) 625 return 0; 626 627 /* 628 * do not read more than one device on the bus directly attached 629 * to RC's (Virtual Bridge's) DS side. 630 */ 631 if (bus->primary == pp->root_bus_nr && dev > 0) 632 return 0; 633 634 return 1; 635} 636 637static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 638 int size, u32 *val) 639{ 640 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 641 unsigned long flags; 642 int ret; 643 644 if (!pp) { 645 BUG(); 646 return -EINVAL; 647 } 648 649 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { 650 *val = 0xffffffff; 651 return PCIBIOS_DEVICE_NOT_FOUND; 652 } 653 654 spin_lock_irqsave(&pp->conf_lock, flags); 655 if (bus->number != pp->root_bus_nr) 656 ret = dw_pcie_rd_other_conf(pp, bus, devfn, 657 where, size, val); 658 else 659 ret = dw_pcie_rd_own_conf(pp, where, size, val); 660 spin_unlock_irqrestore(&pp->conf_lock, flags); 661 662 return ret; 663} 664 665static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 666 int where, int size, u32 val) 667{ 668 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 669 unsigned long flags; 670 int ret; 671 672 if (!pp) { 673 BUG(); 674 return -EINVAL; 675 } 676 677 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) 678 return PCIBIOS_DEVICE_NOT_FOUND; 679 680 spin_lock_irqsave(&pp->conf_lock, flags); 681 if (bus->number != pp->root_bus_nr) 682 ret = dw_pcie_wr_other_conf(pp, bus, devfn, 683 where, size, val); 684 else 685 ret = dw_pcie_wr_own_conf(pp, where, size, val); 686 spin_unlock_irqrestore(&pp->conf_lock, flags); 687 688 return ret; 689} 690 691static struct pci_ops dw_pcie_ops = { 692 .read = dw_pcie_rd_conf, 693 .write = dw_pcie_wr_conf, 694}; 695 696static int dw_pcie_setup(int nr, struct pci_sys_data *sys) 697{ 698 struct pcie_port *pp; 699 700 pp = sys_to_pcie(sys); 701 702 if (!pp) 703 return 0; 704 705 if (global_io_offset < SZ_1M && pp->config.io_size > 0) { 706 sys->io_offset = global_io_offset - pp->config.io_bus_addr; 707 pci_ioremap_io(global_io_offset, pp->io_base); 708 global_io_offset += SZ_64K; 709 pci_add_resource_offset(&sys->resources, &pp->io, 710 sys->io_offset); 711 } 712 713 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr; 714 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); 715 716 return 1; 717} 718 719static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) 720{ 721 struct pci_bus *bus; 722 struct pcie_port *pp = sys_to_pcie(sys); 723 724 if (pp) { 725 pp->root_bus_nr = sys->busnr; 726 bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops, 727 sys, &sys->resources); 728 } else { 729 bus = NULL; 730 BUG(); 731 } 732 733 return bus; 734} 735 736static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 737{ 738 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); 739 740 return pp->irq; 741} 742 743static void dw_pcie_add_bus(struct pci_bus *bus) 744{ 745 if (IS_ENABLED(CONFIG_PCI_MSI)) { 746 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 747 748 dw_pcie_msi_chip.dev = pp->dev; 749 bus->msi = &dw_pcie_msi_chip; 750 } 751} 752 753static struct hw_pci dw_pci = { 754 .setup = dw_pcie_setup, 755 .scan = dw_pcie_scan_bus, 756 .map_irq = dw_pcie_map_irq, 757 .add_bus = dw_pcie_add_bus, 758}; 759 760void dw_pcie_setup_rc(struct pcie_port *pp) 761{ 762 struct pcie_port_info *config = &pp->config; 763 u32 val; 764 u32 membase; 765 u32 memlimit; 766 767 /* set the number of lanes */ 768 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); 769 val &= ~PORT_LINK_MODE_MASK; 770 switch (pp->lanes) { 771 case 1: 772 val |= PORT_LINK_MODE_1_LANES; 773 break; 774 case 2: 775 val |= PORT_LINK_MODE_2_LANES; 776 break; 777 case 4: 778 val |= PORT_LINK_MODE_4_LANES; 779 break; 780 } 781 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); 782 783 /* set link width speed control register */ 784 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); 785 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 786 switch (pp->lanes) { 787 case 1: 788 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 789 break; 790 case 2: 791 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 792 break; 793 case 4: 794 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 795 break; 796 } 797 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); 798 799 /* setup RC BARs */ 800 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); 801 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); 802 803 /* setup interrupt pins */ 804 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); 805 val &= 0xffff00ff; 806 val |= 0x00000100; 807 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); 808 809 /* setup bus numbers */ 810 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); 811 val &= 0xff000000; 812 val |= 0x00010100; 813 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); 814 815 /* setup memory base, memory limit */ 816 membase = ((u32)pp->mem_base & 0xfff00000) >> 16; 817 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000; 818 val = memlimit | membase; 819 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); 820 821 /* setup command register */ 822 dw_pcie_readl_rc(pp, PCI_COMMAND, &val); 823 val &= 0xffff0000; 824 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 825 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 826 dw_pcie_writel_rc(pp, val, PCI_COMMAND); 827} 828 829MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 830MODULE_DESCRIPTION("Designware PCIe host controller driver"); 831MODULE_LICENSE("GPL v2"); 832