gpio.c revision a373ed0aa229f06e7d699797669b664ef39d97c1 
1/*
2 * SuperH Pin Function Controller GPIO driver.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License.  See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
13
14#include <linux/device.h>
15#include <linux/gpio.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21
22#include "core.h"
23
24struct sh_pfc_chip {
25	struct sh_pfc		*pfc;
26	struct gpio_chip	gpio_chip;
27};
28
29static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
30{
31	return container_of(gc, struct sh_pfc_chip, gpio_chip);
32}
33
34static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
35{
36	return gpio_to_pfc_chip(gc)->pfc;
37}
38
39static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
40{
41	struct sh_pfc *pfc = gpio_to_pfc(gc);
42	unsigned long flags;
43	int ret = -EINVAL;
44
45	if (offset < pfc->info->nr_pins)
46		return pinctrl_request_gpio(offset);
47
48	pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
49
50	spin_lock_irqsave(&pfc->lock, flags);
51
52	if (!sh_pfc_gpio_is_function(pfc, offset))
53		goto done;
54
55	if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION,
56			       GPIO_CFG_DRYRUN))
57		goto done;
58
59	if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION,
60			       GPIO_CFG_REQ))
61		goto done;
62
63	ret = 0;
64
65done:
66	spin_unlock_irqrestore(&pfc->lock, flags);
67	return ret;
68}
69
70static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
71{
72	struct sh_pfc *pfc = gpio_to_pfc(gc);
73	unsigned long flags;
74
75	if (offset < pfc->info->nr_pins)
76		return pinctrl_free_gpio(offset);
77
78	spin_lock_irqsave(&pfc->lock, flags);
79
80	sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
81
82	spin_unlock_irqrestore(&pfc->lock, flags);
83}
84
85static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
86{
87	struct pinmux_data_reg *dr = NULL;
88	int bit = 0;
89
90	if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
91		BUG();
92	else
93		sh_pfc_write_bit(dr, bit, value);
94}
95
96static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
97{
98	struct pinmux_data_reg *dr = NULL;
99	int bit = 0;
100
101	if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
102		return -EINVAL;
103
104	return sh_pfc_read_bit(dr, bit);
105}
106
107static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
108{
109	struct sh_pfc *pfc = gpio_to_pfc(gc);
110
111	if (offset >= pfc->info->nr_pins) {
112		/* Function GPIOs can only be requested, never configured. */
113		return -EINVAL;
114	}
115
116	return pinctrl_gpio_direction_input(offset);
117}
118
119static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
120				    int value)
121{
122	struct sh_pfc *pfc = gpio_to_pfc(gc);
123
124	if (offset >= pfc->info->nr_pins) {
125		/* Function GPIOs can only be requested, never configured. */
126		return -EINVAL;
127	}
128
129	sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
130
131	return pinctrl_gpio_direction_output(offset);
132}
133
134static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
135{
136	return sh_gpio_get_value(gpio_to_pfc(gc), offset);
137}
138
139static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
140{
141	sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
142}
143
144static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
145{
146	struct sh_pfc *pfc = gpio_to_pfc(gc);
147	pinmux_enum_t enum_id;
148	pinmux_enum_t *enum_ids;
149	int i, k, pos;
150
151	pos = 0;
152	enum_id = 0;
153	while (1) {
154		pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
155		if (pos <= 0 || !enum_id)
156			break;
157
158		for (i = 0; i < pfc->info->gpio_irq_size; i++) {
159			enum_ids = pfc->info->gpio_irq[i].enum_ids;
160			for (k = 0; enum_ids[k]; k++) {
161				if (enum_ids[k] == enum_id)
162					return pfc->info->gpio_irq[i].irq;
163			}
164		}
165	}
166
167	return -ENOSYS;
168}
169
170static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
171{
172	struct sh_pfc *pfc = chip->pfc;
173	struct gpio_chip *gc = &chip->gpio_chip;
174
175	gc->request = sh_gpio_request;
176	gc->free = sh_gpio_free;
177	gc->direction_input = sh_gpio_direction_input;
178	gc->get = sh_gpio_get;
179	gc->direction_output = sh_gpio_direction_output;
180	gc->set = sh_gpio_set;
181	gc->to_irq = sh_gpio_to_irq;
182
183	gc->label = pfc->info->name;
184	gc->owner = THIS_MODULE;
185	gc->base = 0;
186	gc->ngpio = pfc->info->nr_pins + pfc->info->nr_func_gpios;
187}
188
189int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
190{
191	struct sh_pfc_chip *chip;
192	int ret;
193
194	chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
195	if (unlikely(!chip))
196		return -ENOMEM;
197
198	chip->pfc = pfc;
199
200	sh_pfc_gpio_setup(chip);
201
202	ret = gpiochip_add(&chip->gpio_chip);
203	if (unlikely(ret < 0))
204		return ret;
205
206	pfc->gpio = chip;
207
208	pr_info("%s handling gpio 0 -> %u\n",
209		pfc->info->name,
210		pfc->info->nr_pins + pfc->info->nr_func_gpios - 1);
211
212	return 0;
213}
214
215int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
216{
217	struct sh_pfc_chip *chip = pfc->gpio;
218	int ret;
219
220	ret = gpiochip_remove(&chip->gpio_chip);
221	if (unlikely(ret < 0))
222		return ret;
223
224	pfc->gpio = NULL;
225	return 0;
226}
227