b4e7c55dabf611cf5cccd1554fec06f72e1c9faf |
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12-Jul-2014 |
abdoulaye berthe <berthe.ab@gmail.com> |
pinctrl: remove all usage of gpio_remove ret val in driver/pinctl Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6d5bddd5258c11f58cc6a6d17cd97ce5ad39a270 |
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16-Dec-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
pinctrl: sh-pfc: Constify IRQ GPIOs arrays The arrays are never modified, make them const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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70c8f01a357ac74d223a632659787396fef1e649 |
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11-Dec-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Support GPIO to IRQ mapping specified IRQ resources On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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5b46ac3a7723636082ec6234289517ca5b9c65af |
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11-Dec-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Rename sh_pfc window field to windows There's more than one window, name the field windows. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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316b2550015dc8d26fb1395826533e9ef3434da9 |
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11-Dec-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Terminate gpios array by -1 0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ lists. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8d72a7fc8dd74d41ec5f37b70797679e910007e0 |
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11-Dec-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Turn unsigned indices into unsigned int Some indices take positive values only, make them unsigned. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4f82e3ee724f1712f9e84b8802e24ea096a6089f |
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15-Jul-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Support pins not associated with a GPIO port Pins with selectable functions but without a GPIO port can't be named PORT_# or GP_#_#. Add a SH_PFC_PIN_NAMED macro to declare such pins in the pinmux pins array, naming them with the PIN_ prefix followed by the pin physical position. In order to make sure not to register those pins as GPIOs, add a SH_PFC_PIN_CFG_NO_GPIO pin flag to denote pins without a GPIO port. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
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acac8ed5e2aa2c0d364d06f364fd9ed0dc27d28a |
|
15-Jul-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Compute pin ranges automatically Remove the manually specified ranges from PFC SoC data and compute the ranges automatically. This prevents ranges from being out-of-sync with pins definitions. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
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28818fa5dadfd458fa7e17c8be26b2d7edffa8bf |
|
15-Jul-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Rename struct sh_pfc nr_pins field to nr_gpio_pins The field contains the number of pins with an associated GPIO port. This is currently equal to the total number of pins but will be modified when adding support for pins without a GPIO port. Rename the field accordingly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
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757b055a65c5e0f84185012ef45cc2e15a337b63 |
|
15-Jul-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Rename gpio arguments to be consistent with the rest of the code The gpio_get_data_reg() and gpio_setup_data_reg() functions both take an argument named gpio. The argument contains a GPIO offset for the first function and a pin index for the second one. Rename them to offset and idx respectively to match the rest of the code. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
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a1a3580cb322f71cc5aa7e9180ffb6df609b530d |
|
15-Jul-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Don't overallocate memory for the GPIO chip pins array The GPIO driver uses an array of sh_pfc_gpio_pin structures to store per-GPIO pin data. The array size is miscomputed at allocation time by using the number of the last pin instead of the number of pins. When the pin space contains holes this leads to memory overallocation. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
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ceef91dcc0bca0a39c54d2f0071848b6d5c66b88 |
|
10-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Skip gpiochip registration when no GPIO resource is found Boards/platforms that register dedicated GPIO devices will not supply a memory resource for GPIOs. Try to locate the GPIO memory resource at initialization time, and skip registration of the gpiochip if the resource can't be found. This is a temporary modification to ease the transition to separate GPIO drivers. It should be reverted when all boards and platforms will have been moved. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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1a4fd58f76cf331c93daaa1667daa25db297d0d4 |
|
10-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Make GPIO support optional When implemented as a separate IP block, GPIOs should be handled by a separate driver. To make this possible GPIO support needs to be optional in the sh-pfc driver. If no GPIO data registers are supplied in the SoC information structure skip registration of the gpiochip. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
542a564d2ddbd2c37536b4dff8e45fa0fc239bcc |
|
07-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Make function GPIOs support optional The target is to get rid of function GPIOs completely. To reach this, make function GPIOs support optional by skipping the function GPIO chip registration if no function GPIOS are defined in SoC data. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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9a643c9a11259955ec6961f9a2509604c6df1cd9 |
|
10-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Convert message printing from pr_* to dev_* Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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b705c054255ae3264aa02d46347e9cfbcf26523a |
|
10-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Use proper error codes Return proper error codes instead of -1, and propagate the error codes. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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cd3c1beecfeb757b16904386ea474d3c272de4ee |
|
16-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Constify all SoC data None of the SoC data need to be modified. Constify it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
|
861601de101215494e2cc7918e8633d63da490ef |
|
10-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Remove configuration dry-run and free The purpose of the dry-run is to ensure that a pin about to be configured isn't in use. However, the current implementation is a no-op. This proves that the dry-run isn't essential. Remove it. Freeing configuration then becomes a no-op as well. Remove it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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1a0039dce269317a843d4fc85c4a3430b484bc2d |
|
08-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Don't modify sh_pfc_pin SoC data The sh_pfc_pin structure supplied in SoC data contains information about pin configuration and name. It's abused to store GPIO data registers information and pin config type. Move those fields out of the pinmux_data_reg structure into the new sh_pfc_gpio_pin and sh_pfc_pin_config structures. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
|
51cb226b359bc48fed4a92b9bbd9af34640b1be8 |
|
16-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Don't modify pinmux_data_reg SoC data The pinmux_data_reg structure supplied in SoC data contains information about data registers. It's abused to store per-device mapped iomem and shadow values. Move those fields out of the pinmux_data_reg structure into the per-device sh_pfc_chip structure. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
|
e51d5343ffc4b81172178e51e6ca2ee00da67045 |
|
17-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Don't map data registers individually All data registers are located in the same memory resource. Locate the mapped resource at initializat time and use it directly instead of computing a mapped address for each register. This gets rid of the mapped_reg field of the pinmux_data_reg structure. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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41f1219fae987f97787677d3a91c2f33ca9bab98 |
|
15-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Move GPIO registers access functions to gpio.c Move the sh_pfc_setup_data_regs(), sh_pfc_setup_data_reg(), sh_pfc_get_data_reg(), sh_pfc_read_bit() and sh_pfc_write_bit() function to gpio.c as they belong to the GPIO implementation. Inline sh_pfc_read_bit() and sh_pfc_write_bit() in their only call location. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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63d573835f835aab4c44d0e0342cf5976fb14b35 |
|
15-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Add support for sparse pin numbers The PFC driver assumes that the value of the GPIO_PORTxxx enumeration names are equal to the port number. This isn't true when the port number space is sparse, as with the SH73A0. Fix the issue by adding support for pin numbers ranges specified through SoC data. When no range is specified the driver considers that the PFC implements a single contiguous range for all pins. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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247127f90ba1fcc234008e00e937537a89eef9ca |
|
08-Mar-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Replace pinctrl_add_gpio_range() with gpiochip_add_pin_range() Adding a GPIO range to a pinctrl device logically belongs to the GPIO driver. Switch to the right API. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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934cb02bab9003bf65afe73e9146a1ea63b26c40 |
|
14-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Add function to retrieve a pin instance from its pin number This prepares support for sparse pin numbering. The function currently just performs and indexed lookup in the pins array. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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0b73ee5d534cc6dcb96efb9eac4cf96b40910911 |
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14-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Simplify the sh_pfc_gpio_is_pin() logic The function is guaranteed to be called with a gpio number smaller than nr_pins. The condition can the be simplified, and the function inlined. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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a68fdca9b0447a0e7a85ee378510509be8b70d90 |
|
14-Feb-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Use pinmux identifiers in the pin muxing API The PFC core exposes a sh_pfc_config_gpio() function that configures pinmuxing for a given GPIO (either a real GPIO or a function GPIO). Handling of real and function GPIOs belong to the GPIO layer, move the GPIO number to mark translation to the caller and rename the function to sh_pfc_config_mux(). Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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c07f54f604b3b458f10452b60fe21c549218bf02 |
|
03-Jan-2013 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Look up IRQ table entries by GPIO number Instead of converting the GPIO number to an enum_id and looking up IRQ table entries by enum_id, replace the pinmux_irq enum_ids field with a gpios field and lookup entries using the GPIO number. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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16883814eca229506cd2a4e447b2b5a2338fa35e |
|
06-Dec-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Split pins and functions into separate gpio_chip instances Register two GPIO chips, one for the real GPIOs and one for the function GPIOs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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a373ed0aa229f06e7d699797669b664ef39d97c1 |
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29-Nov-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Split pins and functions definition tables Split the GPIOs table into a pins table for real GPIOs and a functions table for function GPIOs. Only register pins with the pinctrl core. The function GPIOs remain accessible as GPIOs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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24d6b36e91b0503cd1c88b34fa793c0c65fa767d |
|
29-Nov-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Don't needlessly check GPIO type in sh_gpio_free() The GPIO type is always PINMUX_TYPE_FUNCTION when freeing a function GPIO. Hardcode the type value. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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2119f7c9afaf4c5fe88e9ffec1f34c5bc6b02f78 |
|
29-Nov-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Shrink the pinctrl GPIO range to include real GPIOs only As a step towards GPIO function removal, shorten the GPIO range registered with the pinctrl core. Function GPIOs are now handled in the GPIO handlers directly instead of going through the pinctrl API. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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d7a7ca5781fa2ac40319acc7125c487db5b26d91 |
|
28-Nov-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Replace first_gpio and last_gpio with nr_gpios The SoC information first_gpio field is always equal to 0, and the last_gpio field is the index of the last entry in the pinmux_gpios array. Replace the first_gpio and last_gpio fields by a nr_gpios field, and initialize it to ARRAY_SIZE(pinmux_gpios). Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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c3323806a67c0c656e27956b7340e37ba6c6968b |
|
15-Dec-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Move sh_pfc.h from include/linux/ to driver directory The header file isn't used by arch code anymore. Make it private to the driver. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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19bb7fe36950ff74ce322cc29f6f4e025999f1f0 |
|
15-Dec-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Support pinmux info in driver data instead of platform data Pinmux information should be provided by the pinmux driver, not arch code. Make it possible to do so by supporting pinmux information passed through the driver_data field in the platform ID table. Platform data will remain supported until all arch code has been converted. Rename the sh_pfc_platform_data structure to sh_pfc_soc_info to reflect this. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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6e54d8d252ed09ae148af6565971974af9a96e10 |
|
15-Dec-2012 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/ Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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