1/* 2 * simple driver for PWM (Pulse Width Modulator) controller 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> 9 */ 10 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/platform_device.h> 14#include <linux/slab.h> 15#include <linux/err.h> 16#include <linux/clk.h> 17#include <linux/delay.h> 18#include <linux/io.h> 19#include <linux/pwm.h> 20#include <linux/of.h> 21#include <linux/of_device.h> 22 23/* i.MX1 and i.MX21 share the same PWM function block: */ 24 25#define MX1_PWMC 0x00 /* PWM Control Register */ 26#define MX1_PWMS 0x04 /* PWM Sample Register */ 27#define MX1_PWMP 0x08 /* PWM Period Register */ 28 29#define MX1_PWMC_EN (1 << 4) 30 31/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */ 32 33#define MX3_PWMCR 0x00 /* PWM Control Register */ 34#define MX3_PWMSR 0x04 /* PWM Status Register */ 35#define MX3_PWMSAR 0x0C /* PWM Sample Register */ 36#define MX3_PWMPR 0x10 /* PWM Period Register */ 37#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4) 38#define MX3_PWMCR_DOZEEN (1 << 24) 39#define MX3_PWMCR_WAITEN (1 << 23) 40#define MX3_PWMCR_DBGEN (1 << 22) 41#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) 42#define MX3_PWMCR_CLKSRC_IPG (1 << 16) 43#define MX3_PWMCR_SWR (1 << 3) 44#define MX3_PWMCR_EN (1 << 0) 45#define MX3_PWMSR_FIFOAV_4WORDS 0x4 46#define MX3_PWMSR_FIFOAV_MASK 0x7 47 48#define MX3_PWM_SWR_LOOP 5 49 50struct imx_chip { 51 struct clk *clk_per; 52 struct clk *clk_ipg; 53 54 void __iomem *mmio_base; 55 56 struct pwm_chip chip; 57 58 int (*config)(struct pwm_chip *chip, 59 struct pwm_device *pwm, int duty_ns, int period_ns); 60 void (*set_enable)(struct pwm_chip *chip, bool enable); 61}; 62 63#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip) 64 65static int imx_pwm_config_v1(struct pwm_chip *chip, 66 struct pwm_device *pwm, int duty_ns, int period_ns) 67{ 68 struct imx_chip *imx = to_imx_chip(chip); 69 70 /* 71 * The PWM subsystem allows for exact frequencies. However, 72 * I cannot connect a scope on my device to the PWM line and 73 * thus cannot provide the program the PWM controller 74 * exactly. Instead, I'm relying on the fact that the 75 * Bootloader (u-boot or WinCE+haret) has programmed the PWM 76 * function group already. So I'll just modify the PWM sample 77 * register to follow the ratio of duty_ns vs. period_ns 78 * accordingly. 79 * 80 * This is good enough for programming the brightness of 81 * the LCD backlight. 82 * 83 * The real implementation would divide PERCLK[0] first by 84 * both the prescaler (/1 .. /128) and then by CLKSEL 85 * (/2 .. /16). 86 */ 87 u32 max = readl(imx->mmio_base + MX1_PWMP); 88 u32 p = max * duty_ns / period_ns; 89 writel(max - p, imx->mmio_base + MX1_PWMS); 90 91 return 0; 92} 93 94static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable) 95{ 96 struct imx_chip *imx = to_imx_chip(chip); 97 u32 val; 98 99 val = readl(imx->mmio_base + MX1_PWMC); 100 101 if (enable) 102 val |= MX1_PWMC_EN; 103 else 104 val &= ~MX1_PWMC_EN; 105 106 writel(val, imx->mmio_base + MX1_PWMC); 107} 108 109static int imx_pwm_config_v2(struct pwm_chip *chip, 110 struct pwm_device *pwm, int duty_ns, int period_ns) 111{ 112 struct imx_chip *imx = to_imx_chip(chip); 113 struct device *dev = chip->dev; 114 unsigned long long c; 115 unsigned long period_cycles, duty_cycles, prescale; 116 unsigned int period_ms; 117 bool enable = test_bit(PWMF_ENABLED, &pwm->flags); 118 int wait_count = 0, fifoav; 119 u32 cr, sr; 120 121 /* 122 * i.MX PWMv2 has a 4-word sample FIFO. 123 * In order to avoid FIFO overflow issue, we do software reset 124 * to clear all sample FIFO if the controller is disabled or 125 * wait for a full PWM cycle to get a relinquished FIFO slot 126 * when the controller is enabled and the FIFO is fully loaded. 127 */ 128 if (enable) { 129 sr = readl(imx->mmio_base + MX3_PWMSR); 130 fifoav = sr & MX3_PWMSR_FIFOAV_MASK; 131 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { 132 period_ms = DIV_ROUND_UP(pwm->period, NSEC_PER_MSEC); 133 msleep(period_ms); 134 135 sr = readl(imx->mmio_base + MX3_PWMSR); 136 if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK)) 137 dev_warn(dev, "there is no free FIFO slot\n"); 138 } 139 } else { 140 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); 141 do { 142 usleep_range(200, 1000); 143 cr = readl(imx->mmio_base + MX3_PWMCR); 144 } while ((cr & MX3_PWMCR_SWR) && 145 (wait_count++ < MX3_PWM_SWR_LOOP)); 146 147 if (cr & MX3_PWMCR_SWR) 148 dev_warn(dev, "software reset timeout\n"); 149 } 150 151 c = clk_get_rate(imx->clk_per); 152 c = c * period_ns; 153 do_div(c, 1000000000); 154 period_cycles = c; 155 156 prescale = period_cycles / 0x10000 + 1; 157 158 period_cycles /= prescale; 159 c = (unsigned long long)period_cycles * duty_ns; 160 do_div(c, period_ns); 161 duty_cycles = c; 162 163 /* 164 * according to imx pwm RM, the real period value should be 165 * PERIOD value in PWMPR plus 2. 166 */ 167 if (period_cycles > 2) 168 period_cycles -= 2; 169 else 170 period_cycles = 0; 171 172 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); 173 writel(period_cycles, imx->mmio_base + MX3_PWMPR); 174 175 cr = MX3_PWMCR_PRESCALER(prescale) | 176 MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | 177 MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH; 178 179 if (enable) 180 cr |= MX3_PWMCR_EN; 181 182 writel(cr, imx->mmio_base + MX3_PWMCR); 183 184 return 0; 185} 186 187static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable) 188{ 189 struct imx_chip *imx = to_imx_chip(chip); 190 u32 val; 191 192 val = readl(imx->mmio_base + MX3_PWMCR); 193 194 if (enable) 195 val |= MX3_PWMCR_EN; 196 else 197 val &= ~MX3_PWMCR_EN; 198 199 writel(val, imx->mmio_base + MX3_PWMCR); 200} 201 202static int imx_pwm_config(struct pwm_chip *chip, 203 struct pwm_device *pwm, int duty_ns, int period_ns) 204{ 205 struct imx_chip *imx = to_imx_chip(chip); 206 int ret; 207 208 ret = clk_prepare_enable(imx->clk_ipg); 209 if (ret) 210 return ret; 211 212 ret = imx->config(chip, pwm, duty_ns, period_ns); 213 214 clk_disable_unprepare(imx->clk_ipg); 215 216 return ret; 217} 218 219static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 220{ 221 struct imx_chip *imx = to_imx_chip(chip); 222 int ret; 223 224 ret = clk_prepare_enable(imx->clk_per); 225 if (ret) 226 return ret; 227 228 imx->set_enable(chip, true); 229 230 return 0; 231} 232 233static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 234{ 235 struct imx_chip *imx = to_imx_chip(chip); 236 237 imx->set_enable(chip, false); 238 239 clk_disable_unprepare(imx->clk_per); 240} 241 242static struct pwm_ops imx_pwm_ops = { 243 .enable = imx_pwm_enable, 244 .disable = imx_pwm_disable, 245 .config = imx_pwm_config, 246 .owner = THIS_MODULE, 247}; 248 249struct imx_pwm_data { 250 int (*config)(struct pwm_chip *chip, 251 struct pwm_device *pwm, int duty_ns, int period_ns); 252 void (*set_enable)(struct pwm_chip *chip, bool enable); 253}; 254 255static struct imx_pwm_data imx_pwm_data_v1 = { 256 .config = imx_pwm_config_v1, 257 .set_enable = imx_pwm_set_enable_v1, 258}; 259 260static struct imx_pwm_data imx_pwm_data_v2 = { 261 .config = imx_pwm_config_v2, 262 .set_enable = imx_pwm_set_enable_v2, 263}; 264 265static const struct of_device_id imx_pwm_dt_ids[] = { 266 { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, }, 267 { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, }, 268 { /* sentinel */ } 269}; 270MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids); 271 272static int imx_pwm_probe(struct platform_device *pdev) 273{ 274 const struct of_device_id *of_id = 275 of_match_device(imx_pwm_dt_ids, &pdev->dev); 276 const struct imx_pwm_data *data; 277 struct imx_chip *imx; 278 struct resource *r; 279 int ret = 0; 280 281 if (!of_id) 282 return -ENODEV; 283 284 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); 285 if (imx == NULL) 286 return -ENOMEM; 287 288 imx->clk_per = devm_clk_get(&pdev->dev, "per"); 289 if (IS_ERR(imx->clk_per)) { 290 dev_err(&pdev->dev, "getting per clock failed with %ld\n", 291 PTR_ERR(imx->clk_per)); 292 return PTR_ERR(imx->clk_per); 293 } 294 295 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 296 if (IS_ERR(imx->clk_ipg)) { 297 dev_err(&pdev->dev, "getting ipg clock failed with %ld\n", 298 PTR_ERR(imx->clk_ipg)); 299 return PTR_ERR(imx->clk_ipg); 300 } 301 302 imx->chip.ops = &imx_pwm_ops; 303 imx->chip.dev = &pdev->dev; 304 imx->chip.base = -1; 305 imx->chip.npwm = 1; 306 imx->chip.can_sleep = true; 307 308 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 309 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); 310 if (IS_ERR(imx->mmio_base)) 311 return PTR_ERR(imx->mmio_base); 312 313 data = of_id->data; 314 imx->config = data->config; 315 imx->set_enable = data->set_enable; 316 317 ret = pwmchip_add(&imx->chip); 318 if (ret < 0) 319 return ret; 320 321 platform_set_drvdata(pdev, imx); 322 return 0; 323} 324 325static int imx_pwm_remove(struct platform_device *pdev) 326{ 327 struct imx_chip *imx; 328 329 imx = platform_get_drvdata(pdev); 330 if (imx == NULL) 331 return -ENODEV; 332 333 return pwmchip_remove(&imx->chip); 334} 335 336static struct platform_driver imx_pwm_driver = { 337 .driver = { 338 .name = "imx-pwm", 339 .owner = THIS_MODULE, 340 .of_match_table = imx_pwm_dt_ids, 341 }, 342 .probe = imx_pwm_probe, 343 .remove = imx_pwm_remove, 344}; 345 346module_platform_driver(imx_pwm_driver); 347 348MODULE_LICENSE("GPL v2"); 349MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 350