1/**
2 * Copyright (C) 2005 - 2014 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.  The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18#ifndef BEISCSI_H
19#define BEISCSI_H
20
21#include <linux/pci.h>
22#include <linux/if_vlan.h>
23#include <linux/blk-iopoll.h>
24#define FW_VER_LEN	32
25#define MCC_Q_LEN	128
26#define MCC_CQ_LEN	256
27#define MAX_MCC_CMD	16
28/* BladeEngine Generation numbers */
29#define BE_GEN2 2
30#define BE_GEN3 3
31#define BE_GEN4	4
32struct be_dma_mem {
33	void *va;
34	dma_addr_t dma;
35	u32 size;
36};
37
38struct be_queue_info {
39	struct be_dma_mem dma_mem;
40	u16 len;
41	u16 entry_size;		/* Size of an element in the queue */
42	u16 id;
43	u16 tail, head;
44	bool created;
45	atomic_t used;		/* Number of valid elements in the queue */
46};
47
48static inline u32 MODULO(u16 val, u16 limit)
49{
50	WARN_ON(limit & (limit - 1));
51	return val & (limit - 1);
52}
53
54static inline void index_inc(u16 *index, u16 limit)
55{
56	*index = MODULO((*index + 1), limit);
57}
58
59static inline void *queue_head_node(struct be_queue_info *q)
60{
61	return q->dma_mem.va + q->head * q->entry_size;
62}
63
64static inline void *queue_get_wrb(struct be_queue_info *q, unsigned int wrb_num)
65{
66	return q->dma_mem.va + wrb_num * q->entry_size;
67}
68
69static inline void *queue_tail_node(struct be_queue_info *q)
70{
71	return q->dma_mem.va + q->tail * q->entry_size;
72}
73
74static inline void queue_head_inc(struct be_queue_info *q)
75{
76	index_inc(&q->head, q->len);
77}
78
79static inline void queue_tail_inc(struct be_queue_info *q)
80{
81	index_inc(&q->tail, q->len);
82}
83
84/*ISCSI */
85
86struct be_aic_obj {		/* Adaptive interrupt coalescing (AIC) info */
87	bool enable;
88	u32 min_eqd;		/* in usecs */
89	u32 max_eqd;		/* in usecs */
90	u32 prev_eqd;		/* in usecs */
91	u32 et_eqd;		/* configured val when aic is off */
92	ulong jiffs;
93	u64 eq_prev;		/* Used to calculate eqe */
94};
95
96struct be_eq_obj {
97	bool todo_mcc_cq;
98	bool todo_cq;
99	u32 cq_count;
100	struct be_queue_info q;
101	struct beiscsi_hba *phba;
102	struct be_queue_info *cq;
103	struct work_struct work_cqs; /* Work Item */
104	struct blk_iopoll	iopoll;
105};
106
107struct be_mcc_obj {
108	struct be_queue_info q;
109	struct be_queue_info cq;
110};
111
112struct beiscsi_mcc_tag_state {
113#define MCC_TAG_STATE_COMPLETED 0x00
114#define MCC_TAG_STATE_RUNNING   0x01
115#define MCC_TAG_STATE_TIMEOUT   0x02
116	uint8_t tag_state;
117	struct be_dma_mem tag_mem_state;
118};
119
120struct be_ctrl_info {
121	u8 __iomem *csr;
122	u8 __iomem *db;		/* Door Bell */
123	u8 __iomem *pcicfg;	/* PCI config space */
124	struct pci_dev *pdev;
125
126	/* Mbox used for cmd request/response */
127	spinlock_t mbox_lock;	/* For serializing mbox cmds to BE card */
128	struct be_dma_mem mbox_mem;
129	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
130	 * is stored for freeing purpose */
131	struct be_dma_mem mbox_mem_alloced;
132
133	/* MCC Rings */
134	struct be_mcc_obj mcc_obj;
135	spinlock_t mcc_lock;	/* For serializing mcc cmds to BE card */
136	spinlock_t mcc_cq_lock;
137
138	wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1];
139	unsigned int mcc_tag[MAX_MCC_CMD];
140	unsigned int mcc_numtag[MAX_MCC_CMD + 1];
141	unsigned short mcc_alloc_index;
142	unsigned short mcc_free_index;
143	unsigned int mcc_tag_available;
144
145	struct beiscsi_mcc_tag_state ptag_state[MAX_MCC_CMD + 1];
146};
147
148#include "be_cmds.h"
149
150#define PAGE_SHIFT_4K 12
151#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
152#define mcc_timeout		120000 /* 12s timeout */
153#define BEISCSI_LOGOUT_SYNC_DELAY	250
154
155/* Returns number of pages spanned by the data starting at the given addr */
156#define PAGES_4K_SPANNED(_address, size)				\
157		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +	\
158			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
159
160/* Returns bit offset within a DWORD of a bitfield */
161#define AMAP_BIT_OFFSET(_struct, field)					\
162		(((size_t)&(((_struct *)0)->field))%32)
163
164/* Returns the bit mask of the field that is NOT shifted into location. */
165static inline u32 amap_mask(u32 bitsize)
166{
167	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
168}
169
170static inline void amap_set(void *ptr, u32 dw_offset, u32 mask,
171					u32 offset, u32 value)
172{
173	u32 *dw = (u32 *) ptr + dw_offset;
174	*dw &= ~(mask << offset);
175	*dw |= (mask & value) << offset;
176}
177
178#define AMAP_SET_BITS(_struct, field, ptr, val)				\
179		amap_set(ptr,						\
180			offsetof(_struct, field)/32,			\
181			amap_mask(sizeof(((_struct *)0)->field)),	\
182			AMAP_BIT_OFFSET(_struct, field),		\
183			val)
184
185static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
186{
187	u32 *dw = ptr;
188	return mask & (*(dw + dw_offset) >> offset);
189}
190
191#define AMAP_GET_BITS(_struct, field, ptr)				\
192		amap_get(ptr,						\
193			offsetof(_struct, field)/32,			\
194			amap_mask(sizeof(((_struct *)0)->field)),	\
195			AMAP_BIT_OFFSET(_struct, field))
196
197#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
198#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
199static inline void swap_dws(void *wrb, int len)
200{
201#ifdef __BIG_ENDIAN
202	u32 *dw = wrb;
203	WARN_ON(len % 4);
204	do {
205		*dw = cpu_to_le32(*dw);
206		dw++;
207		len -= 4;
208	} while (len);
209#endif /* __BIG_ENDIAN */
210}
211#endif /* BEISCSI_H */
212