1/* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20#include <linux/kernel.h> 21#include <linux/clk.h> 22#include <linux/clk/tegra.h> 23#include <linux/debugfs.h> 24#include <linux/delay.h> 25#include <linux/err.h> 26#include <linux/export.h> 27#include <linux/init.h> 28#include <linux/io.h> 29#include <linux/of.h> 30#include <linux/of_address.h> 31#include <linux/platform_device.h> 32#include <linux/reboot.h> 33#include <linux/reset.h> 34#include <linux/seq_file.h> 35#include <linux/spinlock.h> 36 37#include <soc/tegra/common.h> 38#include <soc/tegra/fuse.h> 39#include <soc/tegra/pmc.h> 40 41#define PMC_CNTRL 0x0 42#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ 43#define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */ 44#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ 45#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ 46#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ 47#define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */ 48 49#define DPD_SAMPLE 0x020 50#define DPD_SAMPLE_ENABLE (1 << 0) 51#define DPD_SAMPLE_DISABLE (0 << 0) 52 53#define PWRGATE_TOGGLE 0x30 54#define PWRGATE_TOGGLE_START (1 << 8) 55 56#define REMOVE_CLAMPING 0x34 57 58#define PWRGATE_STATUS 0x38 59 60#define PMC_SCRATCH0 0x50 61#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) 62#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) 63#define PMC_SCRATCH0_MODE_RCM (1 << 1) 64#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 65 PMC_SCRATCH0_MODE_BOOTLOADER | \ 66 PMC_SCRATCH0_MODE_RCM) 67 68#define PMC_CPUPWRGOOD_TIMER 0xc8 69#define PMC_CPUPWROFF_TIMER 0xcc 70 71#define PMC_SCRATCH41 0x140 72 73#define IO_DPD_REQ 0x1b8 74#define IO_DPD_REQ_CODE_IDLE (0 << 30) 75#define IO_DPD_REQ_CODE_OFF (1 << 30) 76#define IO_DPD_REQ_CODE_ON (2 << 30) 77#define IO_DPD_REQ_CODE_MASK (3 << 30) 78 79#define IO_DPD_STATUS 0x1bc 80#define IO_DPD2_REQ 0x1c0 81#define IO_DPD2_STATUS 0x1c4 82#define SEL_DPD_TIM 0x1c8 83 84#define GPU_RG_CNTRL 0x2d4 85 86struct tegra_pmc_soc { 87 unsigned int num_powergates; 88 const char *const *powergates; 89 unsigned int num_cpu_powergates; 90 const u8 *cpu_powergates; 91}; 92 93/** 94 * struct tegra_pmc - NVIDIA Tegra PMC 95 * @base: pointer to I/O remapped register region 96 * @clk: pointer to pclk clock 97 * @rate: currently configured rate of pclk 98 * @suspend_mode: lowest suspend mode available 99 * @cpu_good_time: CPU power good time (in microseconds) 100 * @cpu_off_time: CPU power off time (in microsecends) 101 * @core_osc_time: core power good OSC time (in microseconds) 102 * @core_pmu_time: core power good PMU time (in microseconds) 103 * @core_off_time: core power off time (in microseconds) 104 * @corereq_high: core power request is active-high 105 * @sysclkreq_high: system clock request is active-high 106 * @combined_req: combined power request for CPU & core 107 * @cpu_pwr_good_en: CPU power good signal is enabled 108 * @lp0_vec_phys: physical base address of the LP0 warm boot code 109 * @lp0_vec_size: size of the LP0 warm boot code 110 * @powergates_lock: mutex for power gate register access 111 */ 112struct tegra_pmc { 113 void __iomem *base; 114 struct clk *clk; 115 116 const struct tegra_pmc_soc *soc; 117 118 unsigned long rate; 119 120 enum tegra_suspend_mode suspend_mode; 121 u32 cpu_good_time; 122 u32 cpu_off_time; 123 u32 core_osc_time; 124 u32 core_pmu_time; 125 u32 core_off_time; 126 bool corereq_high; 127 bool sysclkreq_high; 128 bool combined_req; 129 bool cpu_pwr_good_en; 130 u32 lp0_vec_phys; 131 u32 lp0_vec_size; 132 133 struct mutex powergates_lock; 134}; 135 136static struct tegra_pmc *pmc = &(struct tegra_pmc) { 137 .base = NULL, 138 .suspend_mode = TEGRA_SUSPEND_NONE, 139}; 140 141static u32 tegra_pmc_readl(unsigned long offset) 142{ 143 return readl(pmc->base + offset); 144} 145 146static void tegra_pmc_writel(u32 value, unsigned long offset) 147{ 148 writel(value, pmc->base + offset); 149} 150 151/** 152 * tegra_powergate_set() - set the state of a partition 153 * @id: partition ID 154 * @new_state: new state of the partition 155 */ 156static int tegra_powergate_set(int id, bool new_state) 157{ 158 bool status; 159 160 mutex_lock(&pmc->powergates_lock); 161 162 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); 163 164 if (status == new_state) { 165 mutex_unlock(&pmc->powergates_lock); 166 return 0; 167 } 168 169 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 170 171 mutex_unlock(&pmc->powergates_lock); 172 173 return 0; 174} 175 176/** 177 * tegra_powergate_power_on() - power on partition 178 * @id: partition ID 179 */ 180int tegra_powergate_power_on(int id) 181{ 182 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 183 return -EINVAL; 184 185 return tegra_powergate_set(id, true); 186} 187 188/** 189 * tegra_powergate_power_off() - power off partition 190 * @id: partition ID 191 */ 192int tegra_powergate_power_off(int id) 193{ 194 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 195 return -EINVAL; 196 197 return tegra_powergate_set(id, false); 198} 199EXPORT_SYMBOL(tegra_powergate_power_off); 200 201/** 202 * tegra_powergate_is_powered() - check if partition is powered 203 * @id: partition ID 204 */ 205int tegra_powergate_is_powered(int id) 206{ 207 u32 status; 208 209 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 210 return -EINVAL; 211 212 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); 213 return !!status; 214} 215 216/** 217 * tegra_powergate_remove_clamping() - remove power clamps for partition 218 * @id: partition ID 219 */ 220int tegra_powergate_remove_clamping(int id) 221{ 222 u32 mask; 223 224 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 225 return -EINVAL; 226 227 /* 228 * The Tegra124 GPU has a separate register (with different semantics) 229 * to remove clamps. 230 */ 231 if (tegra_get_chip_id() == TEGRA124) { 232 if (id == TEGRA_POWERGATE_3D) { 233 tegra_pmc_writel(0, GPU_RG_CNTRL); 234 return 0; 235 } 236 } 237 238 /* 239 * Tegra 2 has a bug where PCIE and VDE clamping masks are 240 * swapped relatively to the partition ids 241 */ 242 if (id == TEGRA_POWERGATE_VDEC) 243 mask = (1 << TEGRA_POWERGATE_PCIE); 244 else if (id == TEGRA_POWERGATE_PCIE) 245 mask = (1 << TEGRA_POWERGATE_VDEC); 246 else 247 mask = (1 << id); 248 249 tegra_pmc_writel(mask, REMOVE_CLAMPING); 250 251 return 0; 252} 253EXPORT_SYMBOL(tegra_powergate_remove_clamping); 254 255/** 256 * tegra_powergate_sequence_power_up() - power up partition 257 * @id: partition ID 258 * @clk: clock for partition 259 * @rst: reset for partition 260 * 261 * Must be called with clk disabled, and returns with clk enabled. 262 */ 263int tegra_powergate_sequence_power_up(int id, struct clk *clk, 264 struct reset_control *rst) 265{ 266 int ret; 267 268 reset_control_assert(rst); 269 270 ret = tegra_powergate_power_on(id); 271 if (ret) 272 goto err_power; 273 274 ret = clk_prepare_enable(clk); 275 if (ret) 276 goto err_clk; 277 278 usleep_range(10, 20); 279 280 ret = tegra_powergate_remove_clamping(id); 281 if (ret) 282 goto err_clamp; 283 284 usleep_range(10, 20); 285 reset_control_deassert(rst); 286 287 return 0; 288 289err_clamp: 290 clk_disable_unprepare(clk); 291err_clk: 292 tegra_powergate_power_off(id); 293err_power: 294 return ret; 295} 296EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 297 298#ifdef CONFIG_SMP 299/** 300 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 301 * @cpuid: CPU partition ID 302 * 303 * Returns the partition ID corresponding to the CPU partition ID or a 304 * negative error code on failure. 305 */ 306static int tegra_get_cpu_powergate_id(int cpuid) 307{ 308 if (pmc->soc && cpuid > 0 && cpuid < pmc->soc->num_cpu_powergates) 309 return pmc->soc->cpu_powergates[cpuid]; 310 311 return -EINVAL; 312} 313 314/** 315 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 316 * @cpuid: CPU partition ID 317 */ 318bool tegra_pmc_cpu_is_powered(int cpuid) 319{ 320 int id; 321 322 id = tegra_get_cpu_powergate_id(cpuid); 323 if (id < 0) 324 return false; 325 326 return tegra_powergate_is_powered(id); 327} 328 329/** 330 * tegra_pmc_cpu_power_on() - power on CPU partition 331 * @cpuid: CPU partition ID 332 */ 333int tegra_pmc_cpu_power_on(int cpuid) 334{ 335 int id; 336 337 id = tegra_get_cpu_powergate_id(cpuid); 338 if (id < 0) 339 return id; 340 341 return tegra_powergate_set(id, true); 342} 343 344/** 345 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 346 * @cpuid: CPU partition ID 347 */ 348int tegra_pmc_cpu_remove_clamping(int cpuid) 349{ 350 int id; 351 352 id = tegra_get_cpu_powergate_id(cpuid); 353 if (id < 0) 354 return id; 355 356 return tegra_powergate_remove_clamping(id); 357} 358#endif /* CONFIG_SMP */ 359 360/** 361 * tegra_pmc_restart() - reboot the system 362 * @mode: which mode to reboot in 363 * @cmd: reboot command 364 */ 365void tegra_pmc_restart(enum reboot_mode mode, const char *cmd) 366{ 367 u32 value; 368 369 value = tegra_pmc_readl(PMC_SCRATCH0); 370 value &= ~PMC_SCRATCH0_MODE_MASK; 371 372 if (cmd) { 373 if (strcmp(cmd, "recovery") == 0) 374 value |= PMC_SCRATCH0_MODE_RECOVERY; 375 376 if (strcmp(cmd, "bootloader") == 0) 377 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 378 379 if (strcmp(cmd, "forced-recovery") == 0) 380 value |= PMC_SCRATCH0_MODE_RCM; 381 } 382 383 tegra_pmc_writel(value, PMC_SCRATCH0); 384 385 value = tegra_pmc_readl(0); 386 value |= 0x10; 387 tegra_pmc_writel(value, 0); 388} 389 390static int powergate_show(struct seq_file *s, void *data) 391{ 392 unsigned int i; 393 394 seq_printf(s, " powergate powered\n"); 395 seq_printf(s, "------------------\n"); 396 397 for (i = 0; i < pmc->soc->num_powergates; i++) { 398 if (!pmc->soc->powergates[i]) 399 continue; 400 401 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 402 tegra_powergate_is_powered(i) ? "yes" : "no"); 403 } 404 405 return 0; 406} 407 408static int powergate_open(struct inode *inode, struct file *file) 409{ 410 return single_open(file, powergate_show, inode->i_private); 411} 412 413static const struct file_operations powergate_fops = { 414 .open = powergate_open, 415 .read = seq_read, 416 .llseek = seq_lseek, 417 .release = single_release, 418}; 419 420static int tegra_powergate_debugfs_init(void) 421{ 422 struct dentry *d; 423 424 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 425 &powergate_fops); 426 if (!d) 427 return -ENOMEM; 428 429 return 0; 430} 431 432static int tegra_io_rail_prepare(int id, unsigned long *request, 433 unsigned long *status, unsigned int *bit) 434{ 435 unsigned long rate, value; 436 struct clk *clk; 437 438 *bit = id % 32; 439 440 /* 441 * There are two sets of 30 bits to select IO rails, but bits 30 and 442 * 31 are control bits rather than IO rail selection bits. 443 */ 444 if (id > 63 || *bit == 30 || *bit == 31) 445 return -EINVAL; 446 447 if (id < 32) { 448 *status = IO_DPD_STATUS; 449 *request = IO_DPD_REQ; 450 } else { 451 *status = IO_DPD2_STATUS; 452 *request = IO_DPD2_REQ; 453 } 454 455 clk = clk_get_sys(NULL, "pclk"); 456 if (IS_ERR(clk)) 457 return PTR_ERR(clk); 458 459 rate = clk_get_rate(clk); 460 clk_put(clk); 461 462 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 463 464 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 465 value = DIV_ROUND_UP(1000000000, rate); 466 value = DIV_ROUND_UP(200, value); 467 tegra_pmc_writel(value, SEL_DPD_TIM); 468 469 return 0; 470} 471 472static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, 473 unsigned long val, unsigned long timeout) 474{ 475 unsigned long value; 476 477 timeout = jiffies + msecs_to_jiffies(timeout); 478 479 while (time_after(timeout, jiffies)) { 480 value = tegra_pmc_readl(offset); 481 if ((value & mask) == val) 482 return 0; 483 484 usleep_range(250, 1000); 485 } 486 487 return -ETIMEDOUT; 488} 489 490static void tegra_io_rail_unprepare(void) 491{ 492 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 493} 494 495int tegra_io_rail_power_on(int id) 496{ 497 unsigned long request, status, value; 498 unsigned int bit, mask; 499 int err; 500 501 err = tegra_io_rail_prepare(id, &request, &status, &bit); 502 if (err < 0) 503 return err; 504 505 mask = 1 << bit; 506 507 value = tegra_pmc_readl(request); 508 value |= mask; 509 value &= ~IO_DPD_REQ_CODE_MASK; 510 value |= IO_DPD_REQ_CODE_OFF; 511 tegra_pmc_writel(value, request); 512 513 err = tegra_io_rail_poll(status, mask, 0, 250); 514 if (err < 0) 515 return err; 516 517 tegra_io_rail_unprepare(); 518 519 return 0; 520} 521EXPORT_SYMBOL(tegra_io_rail_power_on); 522 523int tegra_io_rail_power_off(int id) 524{ 525 unsigned long request, status, value; 526 unsigned int bit, mask; 527 int err; 528 529 err = tegra_io_rail_prepare(id, &request, &status, &bit); 530 if (err < 0) 531 return err; 532 533 mask = 1 << bit; 534 535 value = tegra_pmc_readl(request); 536 value |= mask; 537 value &= ~IO_DPD_REQ_CODE_MASK; 538 value |= IO_DPD_REQ_CODE_ON; 539 tegra_pmc_writel(value, request); 540 541 err = tegra_io_rail_poll(status, mask, mask, 250); 542 if (err < 0) 543 return err; 544 545 tegra_io_rail_unprepare(); 546 547 return 0; 548} 549EXPORT_SYMBOL(tegra_io_rail_power_off); 550 551#ifdef CONFIG_PM_SLEEP 552enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 553{ 554 return pmc->suspend_mode; 555} 556 557void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 558{ 559 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 560 return; 561 562 pmc->suspend_mode = mode; 563} 564 565void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 566{ 567 unsigned long long rate = 0; 568 u32 value; 569 570 switch (mode) { 571 case TEGRA_SUSPEND_LP1: 572 rate = 32768; 573 break; 574 575 case TEGRA_SUSPEND_LP2: 576 rate = clk_get_rate(pmc->clk); 577 break; 578 579 default: 580 break; 581 } 582 583 if (WARN_ON_ONCE(rate == 0)) 584 rate = 100000000; 585 586 if (rate != pmc->rate) { 587 u64 ticks; 588 589 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 590 do_div(ticks, USEC_PER_SEC); 591 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 592 593 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 594 do_div(ticks, USEC_PER_SEC); 595 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 596 597 wmb(); 598 599 pmc->rate = rate; 600 } 601 602 value = tegra_pmc_readl(PMC_CNTRL); 603 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 604 value |= PMC_CNTRL_CPU_PWRREQ_OE; 605 tegra_pmc_writel(value, PMC_CNTRL); 606} 607#endif 608 609static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 610{ 611 u32 value, values[2]; 612 613 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 614 } else { 615 switch (value) { 616 case 0: 617 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 618 break; 619 620 case 1: 621 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 622 break; 623 624 case 2: 625 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 626 break; 627 628 default: 629 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 630 break; 631 } 632 } 633 634 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 635 636 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 637 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 638 639 pmc->cpu_good_time = value; 640 641 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 642 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 643 644 pmc->cpu_off_time = value; 645 646 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 647 values, ARRAY_SIZE(values))) 648 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 649 650 pmc->core_osc_time = values[0]; 651 pmc->core_pmu_time = values[1]; 652 653 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 654 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 655 656 pmc->core_off_time = value; 657 658 pmc->corereq_high = of_property_read_bool(np, 659 "nvidia,core-power-req-active-high"); 660 661 pmc->sysclkreq_high = of_property_read_bool(np, 662 "nvidia,sys-clock-req-active-high"); 663 664 pmc->combined_req = of_property_read_bool(np, 665 "nvidia,combined-power-req"); 666 667 pmc->cpu_pwr_good_en = of_property_read_bool(np, 668 "nvidia,cpu-pwr-good-en"); 669 670 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 671 ARRAY_SIZE(values))) 672 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 673 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 674 675 pmc->lp0_vec_phys = values[0]; 676 pmc->lp0_vec_size = values[1]; 677 678 return 0; 679} 680 681static void tegra_pmc_init(struct tegra_pmc *pmc) 682{ 683 u32 value; 684 685 /* Always enable CPU power request */ 686 value = tegra_pmc_readl(PMC_CNTRL); 687 value |= PMC_CNTRL_CPU_PWRREQ_OE; 688 tegra_pmc_writel(value, PMC_CNTRL); 689 690 value = tegra_pmc_readl(PMC_CNTRL); 691 692 if (pmc->sysclkreq_high) 693 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 694 else 695 value |= PMC_CNTRL_SYSCLK_POLARITY; 696 697 /* configure the output polarity while the request is tristated */ 698 tegra_pmc_writel(value, PMC_CNTRL); 699 700 /* now enable the request */ 701 value = tegra_pmc_readl(PMC_CNTRL); 702 value |= PMC_CNTRL_SYSCLK_OE; 703 tegra_pmc_writel(value, PMC_CNTRL); 704} 705 706static int tegra_pmc_probe(struct platform_device *pdev) 707{ 708 void __iomem *base = pmc->base; 709 struct resource *res; 710 int err; 711 712 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 713 if (err < 0) 714 return err; 715 716 /* take over the memory region from the early initialization */ 717 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 718 pmc->base = devm_ioremap_resource(&pdev->dev, res); 719 if (IS_ERR(pmc->base)) 720 return PTR_ERR(pmc->base); 721 722 iounmap(base); 723 724 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 725 if (IS_ERR(pmc->clk)) { 726 err = PTR_ERR(pmc->clk); 727 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 728 return err; 729 } 730 731 tegra_pmc_init(pmc); 732 733 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 734 err = tegra_powergate_debugfs_init(); 735 if (err < 0) 736 return err; 737 } 738 739 return 0; 740} 741 742#ifdef CONFIG_PM_SLEEP 743static int tegra_pmc_suspend(struct device *dev) 744{ 745 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 746 747 return 0; 748} 749 750static int tegra_pmc_resume(struct device *dev) 751{ 752 tegra_pmc_writel(0x0, PMC_SCRATCH41); 753 754 return 0; 755} 756#endif 757 758static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 759 760static const char * const tegra20_powergates[] = { 761 [TEGRA_POWERGATE_CPU] = "cpu", 762 [TEGRA_POWERGATE_3D] = "3d", 763 [TEGRA_POWERGATE_VENC] = "venc", 764 [TEGRA_POWERGATE_VDEC] = "vdec", 765 [TEGRA_POWERGATE_PCIE] = "pcie", 766 [TEGRA_POWERGATE_L2] = "l2", 767 [TEGRA_POWERGATE_MPE] = "mpe", 768}; 769 770static const struct tegra_pmc_soc tegra20_pmc_soc = { 771 .num_powergates = ARRAY_SIZE(tegra20_powergates), 772 .powergates = tegra20_powergates, 773 .num_cpu_powergates = 0, 774 .cpu_powergates = NULL, 775}; 776 777static const char * const tegra30_powergates[] = { 778 [TEGRA_POWERGATE_CPU] = "cpu0", 779 [TEGRA_POWERGATE_3D] = "3d0", 780 [TEGRA_POWERGATE_VENC] = "venc", 781 [TEGRA_POWERGATE_VDEC] = "vdec", 782 [TEGRA_POWERGATE_PCIE] = "pcie", 783 [TEGRA_POWERGATE_L2] = "l2", 784 [TEGRA_POWERGATE_MPE] = "mpe", 785 [TEGRA_POWERGATE_HEG] = "heg", 786 [TEGRA_POWERGATE_SATA] = "sata", 787 [TEGRA_POWERGATE_CPU1] = "cpu1", 788 [TEGRA_POWERGATE_CPU2] = "cpu2", 789 [TEGRA_POWERGATE_CPU3] = "cpu3", 790 [TEGRA_POWERGATE_CELP] = "celp", 791 [TEGRA_POWERGATE_3D1] = "3d1", 792}; 793 794static const u8 tegra30_cpu_powergates[] = { 795 TEGRA_POWERGATE_CPU, 796 TEGRA_POWERGATE_CPU1, 797 TEGRA_POWERGATE_CPU2, 798 TEGRA_POWERGATE_CPU3, 799}; 800 801static const struct tegra_pmc_soc tegra30_pmc_soc = { 802 .num_powergates = ARRAY_SIZE(tegra30_powergates), 803 .powergates = tegra30_powergates, 804 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 805 .cpu_powergates = tegra30_cpu_powergates, 806}; 807 808static const char * const tegra114_powergates[] = { 809 [TEGRA_POWERGATE_CPU] = "crail", 810 [TEGRA_POWERGATE_3D] = "3d", 811 [TEGRA_POWERGATE_VENC] = "venc", 812 [TEGRA_POWERGATE_VDEC] = "vdec", 813 [TEGRA_POWERGATE_MPE] = "mpe", 814 [TEGRA_POWERGATE_HEG] = "heg", 815 [TEGRA_POWERGATE_CPU1] = "cpu1", 816 [TEGRA_POWERGATE_CPU2] = "cpu2", 817 [TEGRA_POWERGATE_CPU3] = "cpu3", 818 [TEGRA_POWERGATE_CELP] = "celp", 819 [TEGRA_POWERGATE_CPU0] = "cpu0", 820 [TEGRA_POWERGATE_C0NC] = "c0nc", 821 [TEGRA_POWERGATE_C1NC] = "c1nc", 822 [TEGRA_POWERGATE_DIS] = "dis", 823 [TEGRA_POWERGATE_DISB] = "disb", 824 [TEGRA_POWERGATE_XUSBA] = "xusba", 825 [TEGRA_POWERGATE_XUSBB] = "xusbb", 826 [TEGRA_POWERGATE_XUSBC] = "xusbc", 827}; 828 829static const u8 tegra114_cpu_powergates[] = { 830 TEGRA_POWERGATE_CPU0, 831 TEGRA_POWERGATE_CPU1, 832 TEGRA_POWERGATE_CPU2, 833 TEGRA_POWERGATE_CPU3, 834}; 835 836static const struct tegra_pmc_soc tegra114_pmc_soc = { 837 .num_powergates = ARRAY_SIZE(tegra114_powergates), 838 .powergates = tegra114_powergates, 839 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 840 .cpu_powergates = tegra114_cpu_powergates, 841}; 842 843static const char * const tegra124_powergates[] = { 844 [TEGRA_POWERGATE_CPU] = "crail", 845 [TEGRA_POWERGATE_3D] = "3d", 846 [TEGRA_POWERGATE_VENC] = "venc", 847 [TEGRA_POWERGATE_PCIE] = "pcie", 848 [TEGRA_POWERGATE_VDEC] = "vdec", 849 [TEGRA_POWERGATE_L2] = "l2", 850 [TEGRA_POWERGATE_MPE] = "mpe", 851 [TEGRA_POWERGATE_HEG] = "heg", 852 [TEGRA_POWERGATE_SATA] = "sata", 853 [TEGRA_POWERGATE_CPU1] = "cpu1", 854 [TEGRA_POWERGATE_CPU2] = "cpu2", 855 [TEGRA_POWERGATE_CPU3] = "cpu3", 856 [TEGRA_POWERGATE_CELP] = "celp", 857 [TEGRA_POWERGATE_CPU0] = "cpu0", 858 [TEGRA_POWERGATE_C0NC] = "c0nc", 859 [TEGRA_POWERGATE_C1NC] = "c1nc", 860 [TEGRA_POWERGATE_SOR] = "sor", 861 [TEGRA_POWERGATE_DIS] = "dis", 862 [TEGRA_POWERGATE_DISB] = "disb", 863 [TEGRA_POWERGATE_XUSBA] = "xusba", 864 [TEGRA_POWERGATE_XUSBB] = "xusbb", 865 [TEGRA_POWERGATE_XUSBC] = "xusbc", 866 [TEGRA_POWERGATE_VIC] = "vic", 867 [TEGRA_POWERGATE_IRAM] = "iram", 868}; 869 870static const u8 tegra124_cpu_powergates[] = { 871 TEGRA_POWERGATE_CPU0, 872 TEGRA_POWERGATE_CPU1, 873 TEGRA_POWERGATE_CPU2, 874 TEGRA_POWERGATE_CPU3, 875}; 876 877static const struct tegra_pmc_soc tegra124_pmc_soc = { 878 .num_powergates = ARRAY_SIZE(tegra124_powergates), 879 .powergates = tegra124_powergates, 880 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 881 .cpu_powergates = tegra124_cpu_powergates, 882}; 883 884static const struct of_device_id tegra_pmc_match[] = { 885 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 886 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 887 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 888 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 889 { } 890}; 891 892static struct platform_driver tegra_pmc_driver = { 893 .driver = { 894 .name = "tegra-pmc", 895 .suppress_bind_attrs = true, 896 .of_match_table = tegra_pmc_match, 897 .pm = &tegra_pmc_pm_ops, 898 }, 899 .probe = tegra_pmc_probe, 900}; 901module_platform_driver(tegra_pmc_driver); 902 903/* 904 * Early initialization to allow access to registers in the very early boot 905 * process. 906 */ 907static int __init tegra_pmc_early_init(void) 908{ 909 const struct of_device_id *match; 910 struct device_node *np; 911 struct resource regs; 912 bool invert; 913 u32 value; 914 915 if (!soc_is_tegra()) 916 return 0; 917 918 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 919 if (!np) { 920 pr_warn("PMC device node not found, disabling powergating\n"); 921 922 regs.start = 0x7000e400; 923 regs.end = 0x7000e7ff; 924 regs.flags = IORESOURCE_MEM; 925 926 pr_warn("Using memory region %pR\n", ®s); 927 } else { 928 pmc->soc = match->data; 929 } 930 931 if (of_address_to_resource(np, 0, ®s) < 0) { 932 pr_err("failed to get PMC registers\n"); 933 return -ENXIO; 934 } 935 936 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 937 if (!pmc->base) { 938 pr_err("failed to map PMC registers\n"); 939 return -ENXIO; 940 } 941 942 mutex_init(&pmc->powergates_lock); 943 944 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 945 946 value = tegra_pmc_readl(PMC_CNTRL); 947 948 if (invert) 949 value |= PMC_CNTRL_INTR_POLARITY; 950 else 951 value &= ~PMC_CNTRL_INTR_POLARITY; 952 953 tegra_pmc_writel(value, PMC_CNTRL); 954 955 return 0; 956} 957early_initcall(tegra_pmc_early_init); 958