1/*
2 * polling/bitbanging SPI master controller driver utilities
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
17 */
18
19#include <linux/spinlock.h>
20#include <linux/workqueue.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
30
31
32/*----------------------------------------------------------------------*/
33
34/*
35 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
36 * Use this for GPIO or shift-register level hardware APIs.
37 *
38 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
39 * to glue code.  These bitbang setup() and cleanup() routines are always
40 * used, though maybe they're called from controller-aware code.
41 *
42 * chipselect() and friends may use spi_device->controller_data and
43 * controller registers as appropriate.
44 *
45 *
46 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
47 * which means you could use a bitbang driver either to get hardware
48 * working quickly, or testing for differences that aren't speed related.
49 */
50
51struct spi_bitbang_cs {
52	unsigned	nsecs;	/* (clock cycle time)/2 */
53	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
54					u32 word, u8 bits);
55	unsigned	(*txrx_bufs)(struct spi_device *,
56					u32 (*txrx_word)(
57						struct spi_device *spi,
58						unsigned nsecs,
59						u32 word, u8 bits),
60					unsigned, struct spi_transfer *);
61};
62
63static unsigned bitbang_txrx_8(
64	struct spi_device	*spi,
65	u32			(*txrx_word)(struct spi_device *spi,
66					unsigned nsecs,
67					u32 word, u8 bits),
68	unsigned		ns,
69	struct spi_transfer	*t
70) {
71	unsigned		bits = t->bits_per_word;
72	unsigned		count = t->len;
73	const u8		*tx = t->tx_buf;
74	u8			*rx = t->rx_buf;
75
76	while (likely(count > 0)) {
77		u8		word = 0;
78
79		if (tx)
80			word = *tx++;
81		word = txrx_word(spi, ns, word, bits);
82		if (rx)
83			*rx++ = word;
84		count -= 1;
85	}
86	return t->len - count;
87}
88
89static unsigned bitbang_txrx_16(
90	struct spi_device	*spi,
91	u32			(*txrx_word)(struct spi_device *spi,
92					unsigned nsecs,
93					u32 word, u8 bits),
94	unsigned		ns,
95	struct spi_transfer	*t
96) {
97	unsigned		bits = t->bits_per_word;
98	unsigned		count = t->len;
99	const u16		*tx = t->tx_buf;
100	u16			*rx = t->rx_buf;
101
102	while (likely(count > 1)) {
103		u16		word = 0;
104
105		if (tx)
106			word = *tx++;
107		word = txrx_word(spi, ns, word, bits);
108		if (rx)
109			*rx++ = word;
110		count -= 2;
111	}
112	return t->len - count;
113}
114
115static unsigned bitbang_txrx_32(
116	struct spi_device	*spi,
117	u32			(*txrx_word)(struct spi_device *spi,
118					unsigned nsecs,
119					u32 word, u8 bits),
120	unsigned		ns,
121	struct spi_transfer	*t
122) {
123	unsigned		bits = t->bits_per_word;
124	unsigned		count = t->len;
125	const u32		*tx = t->tx_buf;
126	u32			*rx = t->rx_buf;
127
128	while (likely(count > 3)) {
129		u32		word = 0;
130
131		if (tx)
132			word = *tx++;
133		word = txrx_word(spi, ns, word, bits);
134		if (rx)
135			*rx++ = word;
136		count -= 4;
137	}
138	return t->len - count;
139}
140
141int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
142{
143	struct spi_bitbang_cs	*cs = spi->controller_state;
144	u8			bits_per_word;
145	u32			hz;
146
147	if (t) {
148		bits_per_word = t->bits_per_word;
149		hz = t->speed_hz;
150	} else {
151		bits_per_word = 0;
152		hz = 0;
153	}
154
155	/* spi_transfer level calls that work per-word */
156	if (!bits_per_word)
157		bits_per_word = spi->bits_per_word;
158	if (bits_per_word <= 8)
159		cs->txrx_bufs = bitbang_txrx_8;
160	else if (bits_per_word <= 16)
161		cs->txrx_bufs = bitbang_txrx_16;
162	else if (bits_per_word <= 32)
163		cs->txrx_bufs = bitbang_txrx_32;
164	else
165		return -EINVAL;
166
167	/* nsecs = (clock period)/2 */
168	if (!hz)
169		hz = spi->max_speed_hz;
170	if (hz) {
171		cs->nsecs = (1000000000/2) / hz;
172		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
173			return -EINVAL;
174	}
175
176	return 0;
177}
178EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
179
180/**
181 * spi_bitbang_setup - default setup for per-word I/O loops
182 */
183int spi_bitbang_setup(struct spi_device *spi)
184{
185	struct spi_bitbang_cs	*cs = spi->controller_state;
186	struct spi_bitbang	*bitbang;
187	int			retval;
188	unsigned long		flags;
189
190	bitbang = spi_master_get_devdata(spi->master);
191
192	if (!cs) {
193		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
194		if (!cs)
195			return -ENOMEM;
196		spi->controller_state = cs;
197	}
198
199	/* per-word shift register access, in hardware or bitbanging */
200	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
201	if (!cs->txrx_word)
202		return -EINVAL;
203
204	retval = bitbang->setup_transfer(spi, NULL);
205	if (retval < 0)
206		return retval;
207
208	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
209
210	/* NOTE we _need_ to call chipselect() early, ideally with adapter
211	 * setup, unless the hardware defaults cooperate to avoid confusion
212	 * between normal (active low) and inverted chipselects.
213	 */
214
215	/* deselect chip (low or high) */
216	spin_lock_irqsave(&bitbang->lock, flags);
217	if (!bitbang->busy) {
218		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
219		ndelay(cs->nsecs);
220	}
221	spin_unlock_irqrestore(&bitbang->lock, flags);
222
223	return 0;
224}
225EXPORT_SYMBOL_GPL(spi_bitbang_setup);
226
227/**
228 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
229 */
230void spi_bitbang_cleanup(struct spi_device *spi)
231{
232	kfree(spi->controller_state);
233}
234EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
235
236static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
237{
238	struct spi_bitbang_cs	*cs = spi->controller_state;
239	unsigned		nsecs = cs->nsecs;
240
241	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
242}
243
244/*----------------------------------------------------------------------*/
245
246/*
247 * SECOND PART ... simple transfer queue runner.
248 *
249 * This costs a task context per controller, running the queue by
250 * performing each transfer in sequence.  Smarter hardware can queue
251 * several DMA transfers at once, and process several controller queues
252 * in parallel; this driver doesn't match such hardware very well.
253 *
254 * Drivers can provide word-at-a-time i/o primitives, or provide
255 * transfer-at-a-time ones to leverage dma or fifo hardware.
256 */
257
258static int spi_bitbang_prepare_hardware(struct spi_master *spi)
259{
260	struct spi_bitbang	*bitbang;
261	unsigned long		flags;
262
263	bitbang = spi_master_get_devdata(spi);
264
265	spin_lock_irqsave(&bitbang->lock, flags);
266	bitbang->busy = 1;
267	spin_unlock_irqrestore(&bitbang->lock, flags);
268
269	return 0;
270}
271
272static int spi_bitbang_transfer_one(struct spi_master *master,
273				    struct spi_message *m)
274{
275	struct spi_bitbang	*bitbang;
276	unsigned		nsecs;
277	struct spi_transfer	*t = NULL;
278	unsigned		cs_change;
279	int			status;
280	int			do_setup = -1;
281	struct spi_device	*spi = m->spi;
282
283	bitbang = spi_master_get_devdata(master);
284
285	/* FIXME this is made-up ... the correct value is known to
286	 * word-at-a-time bitbang code, and presumably chipselect()
287	 * should enforce these requirements too?
288	 */
289	nsecs = 100;
290
291	cs_change = 1;
292	status = 0;
293
294	list_for_each_entry(t, &m->transfers, transfer_list) {
295
296		/* override speed or wordsize? */
297		if (t->speed_hz || t->bits_per_word)
298			do_setup = 1;
299
300		/* init (-1) or override (1) transfer params */
301		if (do_setup != 0) {
302			status = bitbang->setup_transfer(spi, t);
303			if (status < 0)
304				break;
305			if (do_setup == -1)
306				do_setup = 0;
307		}
308
309		/* set up default clock polarity, and activate chip;
310		 * this implicitly updates clock and spi modes as
311		 * previously recorded for this device via setup().
312		 * (and also deselects any other chip that might be
313		 * selected ...)
314		 */
315		if (cs_change) {
316			bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
317			ndelay(nsecs);
318		}
319		cs_change = t->cs_change;
320		if (!t->tx_buf && !t->rx_buf && t->len) {
321			status = -EINVAL;
322			break;
323		}
324
325		/* transfer data.  the lower level code handles any
326		 * new dma mappings it needs. our caller always gave
327		 * us dma-safe buffers.
328		 */
329		if (t->len) {
330			/* REVISIT dma API still needs a designated
331			 * DMA_ADDR_INVALID; ~0 might be better.
332			 */
333			if (!m->is_dma_mapped)
334				t->rx_dma = t->tx_dma = 0;
335			status = bitbang->txrx_bufs(spi, t);
336		}
337		if (status > 0)
338			m->actual_length += status;
339		if (status != t->len) {
340			/* always report some kind of error */
341			if (status >= 0)
342				status = -EREMOTEIO;
343			break;
344		}
345		status = 0;
346
347		/* protocol tweaks before next transfer */
348		if (t->delay_usecs)
349			udelay(t->delay_usecs);
350
351		if (cs_change &&
352		    !list_is_last(&t->transfer_list, &m->transfers)) {
353			/* sometimes a short mid-message deselect of the chip
354			 * may be needed to terminate a mode or command
355			 */
356			ndelay(nsecs);
357			bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
358			ndelay(nsecs);
359		}
360	}
361
362	m->status = status;
363
364	/* normally deactivate chipselect ... unless no error and
365	 * cs_change has hinted that the next message will probably
366	 * be for this chip too.
367	 */
368	if (!(status == 0 && cs_change)) {
369		ndelay(nsecs);
370		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
371		ndelay(nsecs);
372	}
373
374	spi_finalize_current_message(master);
375
376	return status;
377}
378
379static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
380{
381	struct spi_bitbang	*bitbang;
382	unsigned long		flags;
383
384	bitbang = spi_master_get_devdata(spi);
385
386	spin_lock_irqsave(&bitbang->lock, flags);
387	bitbang->busy = 0;
388	spin_unlock_irqrestore(&bitbang->lock, flags);
389
390	return 0;
391}
392
393/*----------------------------------------------------------------------*/
394
395/**
396 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
397 * @bitbang: driver handle
398 *
399 * Caller should have zero-initialized all parts of the structure, and then
400 * provided callbacks for chip selection and I/O loops.  If the master has
401 * a transfer method, its final step should call spi_bitbang_transfer; or,
402 * that's the default if the transfer routine is not initialized.  It should
403 * also set up the bus number and number of chipselects.
404 *
405 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
406 * hardware that basically exposes a shift register) or per-spi_transfer
407 * (which takes better advantage of hardware like fifos or DMA engines).
408 *
409 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
410 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
411 * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
412 * routine isn't initialized.
413 *
414 * This routine registers the spi_master, which will process requests in a
415 * dedicated task, keeping IRQs unblocked most of the time.  To stop
416 * processing those requests, call spi_bitbang_stop().
417 *
418 * On success, this routine will take a reference to master. The caller is
419 * responsible for calling spi_bitbang_stop() to decrement the reference and
420 * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
421 * leak.
422 */
423int spi_bitbang_start(struct spi_bitbang *bitbang)
424{
425	struct spi_master *master = bitbang->master;
426	int ret;
427
428	if (!master || !bitbang->chipselect)
429		return -EINVAL;
430
431	spin_lock_init(&bitbang->lock);
432
433	if (!master->mode_bits)
434		master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;
435
436	if (master->transfer || master->transfer_one_message)
437		return -EINVAL;
438
439	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
440	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
441	master->transfer_one_message = spi_bitbang_transfer_one;
442
443	if (!bitbang->txrx_bufs) {
444		bitbang->use_dma = 0;
445		bitbang->txrx_bufs = spi_bitbang_bufs;
446		if (!master->setup) {
447			if (!bitbang->setup_transfer)
448				bitbang->setup_transfer =
449					 spi_bitbang_setup_transfer;
450			master->setup = spi_bitbang_setup;
451			master->cleanup = spi_bitbang_cleanup;
452		}
453	}
454
455	/* driver may get busy before register() returns, especially
456	 * if someone registered boardinfo for devices
457	 */
458	ret = spi_register_master(spi_master_get(master));
459	if (ret)
460		spi_master_put(master);
461
462	return 0;
463}
464EXPORT_SYMBOL_GPL(spi_bitbang_start);
465
466/**
467 * spi_bitbang_stop - stops the task providing spi communication
468 */
469void spi_bitbang_stop(struct spi_bitbang *bitbang)
470{
471	spi_unregister_master(bitbang->master);
472}
473EXPORT_SYMBOL_GPL(spi_bitbang_stop);
474
475MODULE_LICENSE("GPL");
476
477