1/*
2    module/mite.h
3    Hardware driver for NI Mite PCI interface chip
4
5    COMEDI - Linux Control and Measurement Device Interface
6    Copyright (C) 1999 David A. Schleef <ds@schleef.org>
7
8    This program is free software; you can redistribute it and/or modify
9    it under the terms of the GNU General Public License as published by
10    the Free Software Foundation; either version 2 of the License, or
11    (at your option) any later version.
12
13    This program is distributed in the hope that it will be useful,
14    but WITHOUT ANY WARRANTY; without even the implied warranty of
15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16    GNU General Public License for more details.
17*/
18
19#ifndef _MITE_H_
20#define _MITE_H_
21
22#include <linux/pci.h>
23#include <linux/log2.h>
24#include <linux/slab.h>
25#include "../comedidev.h"
26
27#define PCIMIO_COMPAT
28
29#define MAX_MITE_DMA_CHANNELS 8
30
31struct mite_dma_descriptor {
32	__le32 count;
33	__le32 addr;
34	__le32 next;
35	u32 dar;
36};
37
38struct mite_dma_descriptor_ring {
39	struct device *hw_dev;
40	unsigned int n_links;
41	struct mite_dma_descriptor *descriptors;
42	dma_addr_t descriptors_dma_addr;
43};
44
45struct mite_channel {
46	struct mite_struct *mite;
47	unsigned channel;
48	int dir;
49	int done;
50	struct mite_dma_descriptor_ring *ring;
51};
52
53struct mite_struct {
54	struct pci_dev *pcidev;
55	resource_size_t mite_phys_addr;
56	void __iomem *mite_io_addr;
57	resource_size_t daq_phys_addr;
58	struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
59	short channel_allocated[MAX_MITE_DMA_CHANNELS];
60	int num_channels;
61	unsigned fifo_size;
62	spinlock_t lock;
63};
64
65struct mite_struct *mite_alloc(struct pci_dev *pcidev);
66
67int mite_setup2(struct comedi_device *, struct mite_struct *, bool use_win1);
68
69static inline int mite_setup(struct comedi_device *dev,
70			     struct mite_struct *mite)
71{
72	return mite_setup2(dev, mite, false);
73}
74
75void mite_detach(struct mite_struct *mite);
76struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite);
77void mite_free_ring(struct mite_dma_descriptor_ring *ring);
78struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
79						   struct
80						   mite_dma_descriptor_ring
81						   *ring, unsigned min_channel,
82						   unsigned max_channel);
83static inline struct mite_channel *mite_request_channel(struct mite_struct
84							*mite,
85							struct
86							mite_dma_descriptor_ring
87							*ring)
88{
89	return mite_request_channel_in_range(mite, ring, 0,
90					     mite->num_channels - 1);
91}
92
93void mite_release_channel(struct mite_channel *mite_chan);
94
95unsigned mite_dma_tcr(struct mite_channel *mite_chan);
96void mite_dma_arm(struct mite_channel *mite_chan);
97void mite_dma_disarm(struct mite_channel *mite_chan);
98int mite_sync_input_dma(struct mite_channel *mite_chan,
99			struct comedi_subdevice *s);
100int mite_sync_output_dma(struct mite_channel *mite_chan,
101			 struct comedi_subdevice *s);
102u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
103u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
104u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
105u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
106u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
107unsigned mite_get_status(struct mite_channel *mite_chan);
108int mite_done(struct mite_channel *mite_chan);
109
110void mite_prep_dma(struct mite_channel *mite_chan,
111		   unsigned int num_device_bits, unsigned int num_memory_bits);
112int mite_buf_change(struct mite_dma_descriptor_ring *ring,
113		    struct comedi_subdevice *s);
114
115enum mite_registers {
116	/* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
117	   written and read back.  The bits 0x1f always read as 1.
118	   The rest always read as zero. */
119	MITE_UNKNOWN_DMA_BURST_REG = 0x28,
120	MITE_IODWBSR = 0xc0,	/* IO Device Window Base Size Register */
121	MITE_IODWBSR_1 = 0xc4,	/*  IO Device Window Base Size Register 1 */
122	MITE_IODWCR_1 = 0xf4,
123	MITE_PCI_CONFIG_OFFSET = 0x300,
124	MITE_CSIGR = 0x460	/* chip signature */
125};
126
127#define MITE_CHAN(x)	(0x500 + 0x100 * (x))
128#define MITE_CHOR(x)	(0x00 + MITE_CHAN(x))	/* channel operation */
129#define MITE_CHCR(x)	(0x04 + MITE_CHAN(x))	/* channel control */
130#define MITE_TCR(x)	(0x08 + MITE_CHAN(x))	/* transfer count */
131#define MITE_MCR(x)	(0x0c + MITE_CHAN(x))	/* memory configuration */
132#define MITE_MAR(x)	(0x10 + MITE_CHAN(x))	/* memory address */
133#define MITE_DCR(x)	(0x14 + MITE_CHAN(x))	/* device configuration */
134#define MITE_DAR(x)	(0x18 + MITE_CHAN(x))	/* device address */
135#define MITE_LKCR(x)	(0x1c + MITE_CHAN(x))	/* link configuration */
136#define MITE_LKAR(x)	(0x20 + MITE_CHAN(x))	/* link address */
137#define MITE_LLKAR(x)	(0x24 + MITE_CHAN(x))	/* see tnt5002 manual */
138#define MITE_BAR(x)	(0x28 + MITE_CHAN(x))	/* base address */
139#define MITE_BCR(x)	(0x2c + MITE_CHAN(x))	/* base count */
140#define MITE_SAR(x)	(0x30 + MITE_CHAN(x))	/* ? address */
141#define MITE_WSCR(x)	(0x34 + MITE_CHAN(x))	/* ? */
142#define MITE_WSER(x)	(0x38 + MITE_CHAN(x))	/* ? */
143#define MITE_CHSR(x)	(0x3c + MITE_CHAN(x))	/* channel status */
144#define MITE_FCR(x)	(0x40 + MITE_CHAN(x))	/* fifo count */
145
146enum MITE_IODWBSR_bits {
147	WENAB = 0x80,		/*  window enable */
148};
149
150static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
151{
152	unsigned order = 0;
153
154	BUG_ON(size == 0);
155	order = ilog2(size);
156	BUG_ON(order < 1);
157	return (order - 1) & 0x1f;
158}
159
160enum MITE_UNKNOWN_DMA_BURST_bits {
161	UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
162};
163
164static inline int mite_csigr_version(u32 csigr_bits)
165{
166	return csigr_bits & 0xf;
167};
168
169static inline int mite_csigr_type(u32 csigr_bits)
170{				/*  original mite = 0, minimite = 1 */
171	return (csigr_bits >> 4) & 0xf;
172};
173
174static inline int mite_csigr_mmode(u32 csigr_bits)
175{				/*  mite mode, minimite = 1 */
176	return (csigr_bits >> 8) & 0x3;
177};
178
179static inline int mite_csigr_imode(u32 csigr_bits)
180{				/*  cpu port interface mode, pci = 0x3 */
181	return (csigr_bits >> 12) & 0x3;
182};
183
184static inline int mite_csigr_dmac(u32 csigr_bits)
185{				/*  number of dma channels */
186	return (csigr_bits >> 16) & 0xf;
187};
188
189static inline int mite_csigr_wpdep(u32 csigr_bits)
190{				/*  write post fifo depth */
191	unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
192
193	return (wpdep_bits) ? (1 << (wpdep_bits - 1)) : 0;
194}
195
196static inline int mite_csigr_wins(u32 csigr_bits)
197{
198	return (csigr_bits >> 24) & 0x1f;
199};
200
201static inline int mite_csigr_iowins(u32 csigr_bits)
202{				/*  number of io windows */
203	return (csigr_bits >> 29) & 0x7;
204};
205
206enum MITE_MCR_bits {
207	MCRPON = 0,
208};
209
210enum MITE_DCR_bits {
211	DCR_NORMAL = (1 << 29),
212	DCRPON = 0,
213};
214
215enum MITE_CHOR_bits {
216	CHOR_DMARESET = (1 << 31),
217	CHOR_SET_SEND_TC = (1 << 11),
218	CHOR_CLR_SEND_TC = (1 << 10),
219	CHOR_SET_LPAUSE = (1 << 9),
220	CHOR_CLR_LPAUSE = (1 << 8),
221	CHOR_CLRDONE = (1 << 7),
222	CHOR_CLRRB = (1 << 6),
223	CHOR_CLRLC = (1 << 5),
224	CHOR_FRESET = (1 << 4),
225	CHOR_ABORT = (1 << 3),	/* stop without emptying fifo */
226	CHOR_STOP = (1 << 2),	/* stop after emptying fifo */
227	CHOR_CONT = (1 << 1),
228	CHOR_START = (1 << 0),
229	CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
230};
231
232enum MITE_CHCR_bits {
233	CHCR_SET_DMA_IE = (1 << 31),
234	CHCR_CLR_DMA_IE = (1 << 30),
235	CHCR_SET_LINKP_IE = (1 << 29),
236	CHCR_CLR_LINKP_IE = (1 << 28),
237	CHCR_SET_SAR_IE = (1 << 27),
238	CHCR_CLR_SAR_IE = (1 << 26),
239	CHCR_SET_DONE_IE = (1 << 25),
240	CHCR_CLR_DONE_IE = (1 << 24),
241	CHCR_SET_MRDY_IE = (1 << 23),
242	CHCR_CLR_MRDY_IE = (1 << 22),
243	CHCR_SET_DRDY_IE = (1 << 21),
244	CHCR_CLR_DRDY_IE = (1 << 20),
245	CHCR_SET_LC_IE = (1 << 19),
246	CHCR_CLR_LC_IE = (1 << 18),
247	CHCR_SET_CONT_RB_IE = (1 << 17),
248	CHCR_CLR_CONT_RB_IE = (1 << 16),
249	CHCR_FIFODIS = (1 << 15),
250	CHCR_FIFO_ON = 0,
251	CHCR_BURSTEN = (1 << 14),
252	CHCR_NO_BURSTEN = 0,
253	CHCR_BYTE_SWAP_DEVICE = (1 << 6),
254	CHCR_BYTE_SWAP_MEMORY = (1 << 4),
255	CHCR_DIR = (1 << 3),
256	CHCR_DEV_TO_MEM = CHCR_DIR,
257	CHCR_MEM_TO_DEV = 0,
258	CHCR_NORMAL = (0 << 0),
259	CHCR_CONTINUE = (1 << 0),
260	CHCR_RINGBUFF = (2 << 0),
261	CHCR_LINKSHORT = (4 << 0),
262	CHCR_LINKLONG = (5 << 0),
263	CHCRPON =
264	    (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
265	     CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
266	     CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
267};
268
269enum ConfigRegister_bits {
270	CR_REQS_MASK = 0x7 << 16,
271	CR_ASEQDONT = 0x0 << 10,
272	CR_ASEQUP = 0x1 << 10,
273	CR_ASEQDOWN = 0x2 << 10,
274	CR_ASEQ_MASK = 0x3 << 10,
275	CR_PSIZE8 = (1 << 8),
276	CR_PSIZE16 = (2 << 8),
277	CR_PSIZE32 = (3 << 8),
278	CR_PORTCPU = (0 << 6),
279	CR_PORTIO = (1 << 6),
280	CR_PORTVXI = (2 << 6),
281	CR_PORTMXI = (3 << 6),
282	CR_AMDEVICE = (1 << 0),
283};
284static inline int CR_REQS(int source)
285{
286	return (source & 0x7) << 16;
287};
288
289static inline int CR_REQSDRQ(unsigned drq_line)
290{
291	/* This also works on m-series when
292	   using channels (drq_line) 4 or 5. */
293	return CR_REQS((drq_line & 0x3) | 0x4);
294}
295
296static inline int CR_RL(unsigned int retry_limit)
297{
298	int value = 0;
299
300	if (retry_limit)
301		value = 1 + ilog2(retry_limit);
302	if (value > 0x7)
303		value = 0x7;
304	return (value & 0x7) << 21;
305}
306
307enum CHSR_bits {
308	CHSR_INT = (1 << 31),
309	CHSR_LPAUSES = (1 << 29),
310	CHSR_SARS = (1 << 27),
311	CHSR_DONE = (1 << 25),
312	CHSR_MRDY = (1 << 23),
313	CHSR_DRDY = (1 << 21),
314	CHSR_LINKC = (1 << 19),
315	CHSR_CONTS_RB = (1 << 17),
316	CHSR_ERROR = (1 << 15),
317	CHSR_SABORT = (1 << 14),
318	CHSR_HABORT = (1 << 13),
319	CHSR_STOPS = (1 << 12),
320	CHSR_OPERR_mask = (3 << 10),
321	CHSR_OPERR_NOERROR = (0 << 10),
322	CHSR_OPERR_FIFOERROR = (1 << 10),
323	CHSR_OPERR_LINKERROR = (1 << 10),	/* ??? */
324	CHSR_XFERR = (1 << 9),
325	CHSR_END = (1 << 8),
326	CHSR_DRQ1 = (1 << 7),
327	CHSR_DRQ0 = (1 << 6),
328	CHSR_LxERR_mask = (3 << 4),
329	CHSR_LBERR = (1 << 4),
330	CHSR_LRERR = (2 << 4),
331	CHSR_LOERR = (3 << 4),
332	CHSR_MxERR_mask = (3 << 2),
333	CHSR_MBERR = (1 << 2),
334	CHSR_MRERR = (2 << 2),
335	CHSR_MOERR = (3 << 2),
336	CHSR_DxERR_mask = (3 << 0),
337	CHSR_DBERR = (1 << 0),
338	CHSR_DRERR = (2 << 0),
339	CHSR_DOERR = (3 << 0),
340};
341
342static inline void mite_dma_reset(struct mite_channel *mite_chan)
343{
344	writel(CHOR_DMARESET | CHOR_FRESET,
345	       mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
346};
347
348#endif
349