1/* 2 comedi/drivers/ni_660x.c 3 Hardware driver for NI 660x devices 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14*/ 15 16/* 17 * Driver: ni_660x 18 * Description: National Instruments 660x counter/timer boards 19 * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602, 20 * PXI-6608, PXI-6624 21 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>, 22 * Herman.Bruyninckx@mech.kuleuven.ac.be, 23 * Wim.Meeussen@mech.kuleuven.ac.be, 24 * Klaas.Gadeyne@mech.kuleuven.ac.be, 25 * Frank Mori Hess <fmhess@users.sourceforge.net> 26 * Updated: Fri, 15 Mar 2013 10:47:56 +0000 27 * Status: experimental 28 * 29 * Encoders work. PulseGeneration (both single pulse and pulse train) 30 * works. Buffered commands work for input but not output. 31 * 32 * References: 33 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01) 34 * DAQ 6601/6602 User Manual (NI 322137B-01) 35 */ 36 37#include <linux/module.h> 38#include <linux/pci.h> 39#include <linux/interrupt.h> 40 41#include "../comedidev.h" 42 43#include "comedi_fc.h" 44#include "mite.h" 45#include "ni_tio.h" 46 47enum ni_660x_constants { 48 min_counter_pfi_chan = 8, 49 max_dio_pfi_chan = 31, 50 counters_per_chip = 4 51}; 52 53#define NUM_PFI_CHANNELS 40 54/* really there are only up to 3 dma channels, but the register layout allows 55for 4 */ 56#define MAX_DMA_CHANNEL 4 57 58/* See Register-Level Programmer Manual page 3.1 */ 59enum ni_660x_register { 60 NI660X_G0_INT_ACK, 61 NI660X_G0_STATUS, 62 NI660X_G1_INT_ACK, 63 NI660X_G1_STATUS, 64 NI660X_G01_STATUS, 65 NI660X_G0_CMD, 66 NI660X_STC_DIO_PARALLEL_INPUT, 67 NI660X_G1_CMD, 68 NI660X_G0_HW_SAVE, 69 NI660X_G1_HW_SAVE, 70 NI660X_STC_DIO_OUTPUT, 71 NI660X_STC_DIO_CONTROL, 72 NI660X_G0_SW_SAVE, 73 NI660X_G1_SW_SAVE, 74 NI660X_G0_MODE, 75 NI660X_G01_STATUS1, 76 NI660X_G1_MODE, 77 NI660X_STC_DIO_SERIAL_INPUT, 78 NI660X_G0_LOADA, 79 NI660X_G01_STATUS2, 80 NI660X_G0_LOADB, 81 NI660X_G1_LOADA, 82 NI660X_G1_LOADB, 83 NI660X_G0_INPUT_SEL, 84 NI660X_G1_INPUT_SEL, 85 NI660X_G0_AUTO_INC, 86 NI660X_G1_AUTO_INC, 87 NI660X_G01_RESET, 88 NI660X_G0_INT_ENA, 89 NI660X_G1_INT_ENA, 90 NI660X_G0_CNT_MODE, 91 NI660X_G1_CNT_MODE, 92 NI660X_G0_GATE2, 93 NI660X_G1_GATE2, 94 NI660X_G0_DMA_CFG, 95 NI660X_G0_DMA_STATUS, 96 NI660X_G1_DMA_CFG, 97 NI660X_G1_DMA_STATUS, 98 NI660X_G2_INT_ACK, 99 NI660X_G2_STATUS, 100 NI660X_G3_INT_ACK, 101 NI660X_G3_STATUS, 102 NI660X_G23_STATUS, 103 NI660X_G2_CMD, 104 NI660X_G3_CMD, 105 NI660X_G2_HW_SAVE, 106 NI660X_G3_HW_SAVE, 107 NI660X_G2_SW_SAVE, 108 NI660X_G3_SW_SAVE, 109 NI660X_G2_MODE, 110 NI660X_G23_STATUS1, 111 NI660X_G3_MODE, 112 NI660X_G2_LOADA, 113 NI660X_G23_STATUS2, 114 NI660X_G2_LOADB, 115 NI660X_G3_LOADA, 116 NI660X_G3_LOADB, 117 NI660X_G2_INPUT_SEL, 118 NI660X_G3_INPUT_SEL, 119 NI660X_G2_AUTO_INC, 120 NI660X_G3_AUTO_INC, 121 NI660X_G23_RESET, 122 NI660X_G2_INT_ENA, 123 NI660X_G3_INT_ENA, 124 NI660X_G2_CNT_MODE, 125 NI660X_G3_CNT_MODE, 126 NI660X_G3_GATE2, 127 NI660X_G2_GATE2, 128 NI660X_G2_DMA_CFG, 129 NI660X_G2_DMA_STATUS, 130 NI660X_G3_DMA_CFG, 131 NI660X_G3_DMA_STATUS, 132 NI660X_DIO32_INPUT, 133 NI660X_DIO32_OUTPUT, 134 NI660X_CLK_CFG, 135 NI660X_GLOBAL_INT_STATUS, 136 NI660X_DMA_CFG, 137 NI660X_GLOBAL_INT_CFG, 138 NI660X_IO_CFG_0_1, 139 NI660X_IO_CFG_2_3, 140 NI660X_IO_CFG_4_5, 141 NI660X_IO_CFG_6_7, 142 NI660X_IO_CFG_8_9, 143 NI660X_IO_CFG_10_11, 144 NI660X_IO_CFG_12_13, 145 NI660X_IO_CFG_14_15, 146 NI660X_IO_CFG_16_17, 147 NI660X_IO_CFG_18_19, 148 NI660X_IO_CFG_20_21, 149 NI660X_IO_CFG_22_23, 150 NI660X_IO_CFG_24_25, 151 NI660X_IO_CFG_26_27, 152 NI660X_IO_CFG_28_29, 153 NI660X_IO_CFG_30_31, 154 NI660X_IO_CFG_32_33, 155 NI660X_IO_CFG_34_35, 156 NI660X_IO_CFG_36_37, 157 NI660X_IO_CFG_38_39, 158 NI660X_NUM_REGS, 159}; 160 161static inline unsigned IOConfigReg(unsigned pfi_channel) 162{ 163 unsigned reg = NI660X_IO_CFG_0_1 + pfi_channel / 2; 164 165 BUG_ON(reg > NI660X_IO_CFG_38_39); 166 return reg; 167} 168 169enum ni_660x_register_width { 170 DATA_1B, 171 DATA_2B, 172 DATA_4B 173}; 174 175enum ni_660x_register_direction { 176 NI_660x_READ, 177 NI_660x_WRITE, 178 NI_660x_READ_WRITE 179}; 180 181enum ni_660x_pfi_output_select { 182 pfi_output_select_high_Z = 0, 183 pfi_output_select_counter = 1, 184 pfi_output_select_do = 2, 185 num_pfi_output_selects 186}; 187 188enum ni_660x_subdevices { 189 NI_660X_DIO_SUBDEV = 1, 190 NI_660X_GPCT_SUBDEV_0 = 2 191}; 192static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index) 193{ 194 return NI_660X_GPCT_SUBDEV_0 + index; 195} 196 197struct NI_660xRegisterData { 198 199 const char *name; /* Register Name */ 200 int offset; /* Offset from base address from GPCT chip */ 201 enum ni_660x_register_direction direction; 202 enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ 203}; 204 205static const struct NI_660xRegisterData registerData[NI660X_NUM_REGS] = { 206 {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B}, 207 {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B}, 208 {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B}, 209 {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B}, 210 {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B}, 211 {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B}, 212 {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B}, 213 {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B}, 214 {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B}, 215 {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B}, 216 {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B}, 217 {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B}, 218 {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B}, 219 {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B}, 220 {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B}, 221 {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B}, 222 {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B}, 223 {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B}, 224 {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B}, 225 {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B}, 226 {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B}, 227 {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B}, 228 {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B}, 229 {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B}, 230 {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B}, 231 {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B}, 232 {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B}, 233 {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B}, 234 {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B}, 235 {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B}, 236 {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B}, 237 {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B}, 238 {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B}, 239 {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B}, 240 {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B}, 241 {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B}, 242 {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B}, 243 {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B}, 244 {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B}, 245 {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B}, 246 {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B}, 247 {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B}, 248 {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B}, 249 {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B}, 250 {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B}, 251 {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B}, 252 {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B}, 253 {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B}, 254 {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B}, 255 {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B}, 256 {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B}, 257 {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B}, 258 {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B}, 259 {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B}, 260 {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B}, 261 {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B}, 262 {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B}, 263 {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B}, 264 {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B}, 265 {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B}, 266 {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B}, 267 {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B}, 268 {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B}, 269 {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B}, 270 {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B}, 271 {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B}, 272 {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B}, 273 {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B}, 274 {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B}, 275 {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B}, 276 {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B}, 277 {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B}, 278 {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B}, 279 {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B}, 280 {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B}, 281 {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B}, 282 {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B}, 283 {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B}, 284 {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B}, 285 {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B}, 286 {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B}, 287 {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B}, 288 {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B}, 289 {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B}, 290 {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B}, 291 {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B}, 292 {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B}, 293 {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B}, 294 {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B}, 295 {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B}, 296 {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B}, 297 {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B}, 298 {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B}, 299 {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B}, 300 {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B}, 301 {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B}, 302 {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B}, 303 {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B} 304}; 305 306/* kind of ENABLE for the second counter */ 307enum clock_config_register_bits { 308 CounterSwap = 0x1 << 21 309}; 310 311/* ioconfigreg */ 312static inline unsigned ioconfig_bitshift(unsigned pfi_channel) 313{ 314 return (pfi_channel % 2) ? 0 : 8; 315} 316 317static inline unsigned pfi_output_select_mask(unsigned pfi_channel) 318{ 319 return 0x3 << ioconfig_bitshift(pfi_channel); 320} 321 322static inline unsigned pfi_output_select_bits(unsigned pfi_channel, 323 unsigned output_select) 324{ 325 return (output_select & 0x3) << ioconfig_bitshift(pfi_channel); 326} 327 328static inline unsigned pfi_input_select_mask(unsigned pfi_channel) 329{ 330 return 0x7 << (4 + ioconfig_bitshift(pfi_channel)); 331} 332 333static inline unsigned pfi_input_select_bits(unsigned pfi_channel, 334 unsigned input_select) 335{ 336 return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel)); 337} 338 339/* dma configuration register bits */ 340static inline unsigned dma_select_mask(unsigned dma_channel) 341{ 342 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 343 return 0x1f << (8 * dma_channel); 344} 345 346enum dma_selection { 347 dma_selection_none = 0x1f, 348}; 349 350static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection) 351{ 352 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 353 return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel); 354} 355 356static inline unsigned dma_reset_bit(unsigned dma_channel) 357{ 358 BUG_ON(dma_channel >= MAX_DMA_CHANNEL); 359 return 0x80 << (8 * dma_channel); 360} 361 362enum global_interrupt_status_register_bits { 363 Counter_0_Int_Bit = 0x100, 364 Counter_1_Int_Bit = 0x200, 365 Counter_2_Int_Bit = 0x400, 366 Counter_3_Int_Bit = 0x800, 367 Cascade_Int_Bit = 0x20000000, 368 Global_Int_Bit = 0x80000000 369}; 370 371enum global_interrupt_config_register_bits { 372 Cascade_Int_Enable_Bit = 0x20000000, 373 Global_Int_Polarity_Bit = 0x40000000, 374 Global_Int_Enable_Bit = 0x80000000 375}; 376 377/* Offset of the GPCT chips from the base-address of the card */ 378/* First chip is at base-address + 0x00, etc. */ 379static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; 380 381enum ni_660x_boardid { 382 BOARD_PCI6601, 383 BOARD_PCI6602, 384 BOARD_PXI6602, 385 BOARD_PXI6608, 386 BOARD_PXI6624 387}; 388 389struct ni_660x_board { 390 const char *name; 391 unsigned n_chips; /* total number of TIO chips */ 392}; 393 394static const struct ni_660x_board ni_660x_boards[] = { 395 [BOARD_PCI6601] = { 396 .name = "PCI-6601", 397 .n_chips = 1, 398 }, 399 [BOARD_PCI6602] = { 400 .name = "PCI-6602", 401 .n_chips = 2, 402 }, 403 [BOARD_PXI6602] = { 404 .name = "PXI-6602", 405 .n_chips = 2, 406 }, 407 [BOARD_PXI6608] = { 408 .name = "PXI-6608", 409 .n_chips = 2, 410 }, 411 [BOARD_PXI6624] = { 412 .name = "PXI-6624", 413 .n_chips = 2, 414 }, 415}; 416 417#define NI_660X_MAX_NUM_CHIPS 2 418#define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip) 419 420struct ni_660x_private { 421 struct mite_struct *mite; 422 struct ni_gpct_device *counter_dev; 423 uint64_t pfi_direction_bits; 424 struct mite_dma_descriptor_ring 425 *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip]; 426 spinlock_t mite_channel_lock; 427 /* interrupt_lock prevents races between interrupt and comedi_poll */ 428 spinlock_t interrupt_lock; 429 unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS]; 430 spinlock_t soft_reg_copy_lock; 431 unsigned short pfi_output_selects[NUM_PFI_CHANNELS]; 432}; 433 434static inline unsigned ni_660x_num_counters(struct comedi_device *dev) 435{ 436 const struct ni_660x_board *board = dev->board_ptr; 437 438 return board->n_chips * counters_per_chip; 439} 440 441static enum ni_660x_register ni_gpct_to_660x_register(enum ni_gpct_register reg) 442{ 443 switch (reg) { 444 case NITIO_G0_AUTO_INC: 445 return NI660X_G0_AUTO_INC; 446 case NITIO_G1_AUTO_INC: 447 return NI660X_G1_AUTO_INC; 448 case NITIO_G2_AUTO_INC: 449 return NI660X_G2_AUTO_INC; 450 case NITIO_G3_AUTO_INC: 451 return NI660X_G3_AUTO_INC; 452 case NITIO_G0_CMD: 453 return NI660X_G0_CMD; 454 case NITIO_G1_CMD: 455 return NI660X_G1_CMD; 456 case NITIO_G2_CMD: 457 return NI660X_G2_CMD; 458 case NITIO_G3_CMD: 459 return NI660X_G3_CMD; 460 case NITIO_G0_HW_SAVE: 461 return NI660X_G0_HW_SAVE; 462 case NITIO_G1_HW_SAVE: 463 return NI660X_G1_HW_SAVE; 464 case NITIO_G2_HW_SAVE: 465 return NI660X_G2_HW_SAVE; 466 case NITIO_G3_HW_SAVE: 467 return NI660X_G3_HW_SAVE; 468 case NITIO_G0_SW_SAVE: 469 return NI660X_G0_SW_SAVE; 470 case NITIO_G1_SW_SAVE: 471 return NI660X_G1_SW_SAVE; 472 case NITIO_G2_SW_SAVE: 473 return NI660X_G2_SW_SAVE; 474 case NITIO_G3_SW_SAVE: 475 return NI660X_G3_SW_SAVE; 476 case NITIO_G0_MODE: 477 return NI660X_G0_MODE; 478 case NITIO_G1_MODE: 479 return NI660X_G1_MODE; 480 case NITIO_G2_MODE: 481 return NI660X_G2_MODE; 482 case NITIO_G3_MODE: 483 return NI660X_G3_MODE; 484 case NITIO_G0_LOADA: 485 return NI660X_G0_LOADA; 486 case NITIO_G1_LOADA: 487 return NI660X_G1_LOADA; 488 case NITIO_G2_LOADA: 489 return NI660X_G2_LOADA; 490 case NITIO_G3_LOADA: 491 return NI660X_G3_LOADA; 492 case NITIO_G0_LOADB: 493 return NI660X_G0_LOADB; 494 case NITIO_G1_LOADB: 495 return NI660X_G1_LOADB; 496 case NITIO_G2_LOADB: 497 return NI660X_G2_LOADB; 498 case NITIO_G3_LOADB: 499 return NI660X_G3_LOADB; 500 case NITIO_G0_INPUT_SEL: 501 return NI660X_G0_INPUT_SEL; 502 case NITIO_G1_INPUT_SEL: 503 return NI660X_G1_INPUT_SEL; 504 case NITIO_G2_INPUT_SEL: 505 return NI660X_G2_INPUT_SEL; 506 case NITIO_G3_INPUT_SEL: 507 return NI660X_G3_INPUT_SEL; 508 case NITIO_G01_STATUS: 509 return NI660X_G01_STATUS; 510 case NITIO_G23_STATUS: 511 return NI660X_G23_STATUS; 512 case NITIO_G01_RESET: 513 return NI660X_G01_RESET; 514 case NITIO_G23_RESET: 515 return NI660X_G23_RESET; 516 case NITIO_G01_STATUS1: 517 return NI660X_G01_STATUS1; 518 case NITIO_G23_STATUS1: 519 return NI660X_G23_STATUS1; 520 case NITIO_G01_STATUS2: 521 return NI660X_G01_STATUS2; 522 case NITIO_G23_STATUS2: 523 return NI660X_G23_STATUS2; 524 case NITIO_G0_CNT_MODE: 525 return NI660X_G0_CNT_MODE; 526 case NITIO_G1_CNT_MODE: 527 return NI660X_G1_CNT_MODE; 528 case NITIO_G2_CNT_MODE: 529 return NI660X_G2_CNT_MODE; 530 case NITIO_G3_CNT_MODE: 531 return NI660X_G3_CNT_MODE; 532 case NITIO_G0_GATE2: 533 return NI660X_G0_GATE2; 534 case NITIO_G1_GATE2: 535 return NI660X_G1_GATE2; 536 case NITIO_G2_GATE2: 537 return NI660X_G2_GATE2; 538 case NITIO_G3_GATE2: 539 return NI660X_G3_GATE2; 540 case NITIO_G0_DMA_CFG: 541 return NI660X_G0_DMA_CFG; 542 case NITIO_G0_DMA_STATUS: 543 return NI660X_G0_DMA_STATUS; 544 case NITIO_G1_DMA_CFG: 545 return NI660X_G1_DMA_CFG; 546 case NITIO_G1_DMA_STATUS: 547 return NI660X_G1_DMA_STATUS; 548 case NITIO_G2_DMA_CFG: 549 return NI660X_G2_DMA_CFG; 550 case NITIO_G2_DMA_STATUS: 551 return NI660X_G2_DMA_STATUS; 552 case NITIO_G3_DMA_CFG: 553 return NI660X_G3_DMA_CFG; 554 case NITIO_G3_DMA_STATUS: 555 return NI660X_G3_DMA_STATUS; 556 case NITIO_G0_INT_ACK: 557 return NI660X_G0_INT_ACK; 558 case NITIO_G1_INT_ACK: 559 return NI660X_G1_INT_ACK; 560 case NITIO_G2_INT_ACK: 561 return NI660X_G2_INT_ACK; 562 case NITIO_G3_INT_ACK: 563 return NI660X_G3_INT_ACK; 564 case NITIO_G0_STATUS: 565 return NI660X_G0_STATUS; 566 case NITIO_G1_STATUS: 567 return NI660X_G1_STATUS; 568 case NITIO_G2_STATUS: 569 return NI660X_G2_STATUS; 570 case NITIO_G3_STATUS: 571 return NI660X_G3_STATUS; 572 case NITIO_G0_INT_ENA: 573 return NI660X_G0_INT_ENA; 574 case NITIO_G1_INT_ENA: 575 return NI660X_G1_INT_ENA; 576 case NITIO_G2_INT_ENA: 577 return NI660X_G2_INT_ENA; 578 case NITIO_G3_INT_ENA: 579 return NI660X_G3_INT_ENA; 580 default: 581 BUG(); 582 return 0; 583 } 584} 585 586static inline void ni_660x_write_register(struct comedi_device *dev, 587 unsigned chip, unsigned bits, 588 enum ni_660x_register reg) 589{ 590 unsigned int addr = GPCT_OFFSET[chip] + registerData[reg].offset; 591 592 switch (registerData[reg].size) { 593 case DATA_2B: 594 writew(bits, dev->mmio + addr); 595 break; 596 case DATA_4B: 597 writel(bits, dev->mmio + addr); 598 break; 599 default: 600 BUG(); 601 break; 602 } 603} 604 605static inline unsigned ni_660x_read_register(struct comedi_device *dev, 606 unsigned chip, 607 enum ni_660x_register reg) 608{ 609 unsigned int addr = GPCT_OFFSET[chip] + registerData[reg].offset; 610 611 switch (registerData[reg].size) { 612 case DATA_2B: 613 return readw(dev->mmio + addr); 614 case DATA_4B: 615 return readl(dev->mmio + addr); 616 default: 617 BUG(); 618 break; 619 } 620 return 0; 621} 622 623static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 624 enum ni_gpct_register reg) 625{ 626 struct comedi_device *dev = counter->counter_dev->dev; 627 enum ni_660x_register ni_660x_register = ni_gpct_to_660x_register(reg); 628 unsigned chip = counter->chip_index; 629 630 ni_660x_write_register(dev, chip, bits, ni_660x_register); 631} 632 633static unsigned ni_gpct_read_register(struct ni_gpct *counter, 634 enum ni_gpct_register reg) 635{ 636 struct comedi_device *dev = counter->counter_dev->dev; 637 enum ni_660x_register ni_660x_register = ni_gpct_to_660x_register(reg); 638 unsigned chip = counter->chip_index; 639 640 return ni_660x_read_register(dev, chip, ni_660x_register); 641} 642 643static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private 644 *priv, 645 struct ni_gpct 646 *counter) 647{ 648 unsigned chip = counter->chip_index; 649 650 return priv->mite_rings[chip][counter->counter_index]; 651} 652 653static inline void ni_660x_set_dma_channel(struct comedi_device *dev, 654 unsigned mite_channel, 655 struct ni_gpct *counter) 656{ 657 struct ni_660x_private *devpriv = dev->private; 658 unsigned chip = counter->chip_index; 659 unsigned long flags; 660 661 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 662 devpriv->dma_configuration_soft_copies[chip] &= 663 ~dma_select_mask(mite_channel); 664 devpriv->dma_configuration_soft_copies[chip] |= 665 dma_select_bits(mite_channel, counter->counter_index); 666 ni_660x_write_register(dev, chip, 667 devpriv->dma_configuration_soft_copies[chip] | 668 dma_reset_bit(mite_channel), NI660X_DMA_CFG); 669 mmiowb(); 670 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 671} 672 673static inline void ni_660x_unset_dma_channel(struct comedi_device *dev, 674 unsigned mite_channel, 675 struct ni_gpct *counter) 676{ 677 struct ni_660x_private *devpriv = dev->private; 678 unsigned chip = counter->chip_index; 679 unsigned long flags; 680 681 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 682 devpriv->dma_configuration_soft_copies[chip] &= 683 ~dma_select_mask(mite_channel); 684 devpriv->dma_configuration_soft_copies[chip] |= 685 dma_select_bits(mite_channel, dma_selection_none); 686 ni_660x_write_register(dev, chip, 687 devpriv->dma_configuration_soft_copies[chip], 688 NI660X_DMA_CFG); 689 mmiowb(); 690 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 691} 692 693static int ni_660x_request_mite_channel(struct comedi_device *dev, 694 struct ni_gpct *counter, 695 enum comedi_io_direction direction) 696{ 697 struct ni_660x_private *devpriv = dev->private; 698 unsigned long flags; 699 struct mite_channel *mite_chan; 700 701 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 702 BUG_ON(counter->mite_chan); 703 mite_chan = mite_request_channel(devpriv->mite, 704 mite_ring(devpriv, counter)); 705 if (mite_chan == NULL) { 706 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 707 dev_err(dev->class_dev, 708 "failed to reserve mite dma channel for counter\n"); 709 return -EBUSY; 710 } 711 mite_chan->dir = direction; 712 ni_tio_set_mite_channel(counter, mite_chan); 713 ni_660x_set_dma_channel(dev, mite_chan->channel, counter); 714 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 715 return 0; 716} 717 718static void ni_660x_release_mite_channel(struct comedi_device *dev, 719 struct ni_gpct *counter) 720{ 721 struct ni_660x_private *devpriv = dev->private; 722 unsigned long flags; 723 724 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 725 if (counter->mite_chan) { 726 struct mite_channel *mite_chan = counter->mite_chan; 727 728 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter); 729 ni_tio_set_mite_channel(counter, NULL); 730 mite_release_channel(mite_chan); 731 } 732 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 733} 734 735static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 736{ 737 struct ni_gpct *counter = s->private; 738 int retval; 739 740 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT); 741 if (retval) { 742 dev_err(dev->class_dev, 743 "no dma channel available for use by counter\n"); 744 return retval; 745 } 746 ni_tio_acknowledge(counter); 747 748 return ni_tio_cmd(dev, s); 749} 750 751static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 752{ 753 struct ni_gpct *counter = s->private; 754 int retval; 755 756 retval = ni_tio_cancel(counter); 757 ni_660x_release_mite_channel(dev, counter); 758 return retval; 759} 760 761static void set_tio_counterswap(struct comedi_device *dev, int chip) 762{ 763 unsigned bits = 0; 764 765 /* 766 * See P. 3.5 of the Register-Level Programming manual. 767 * The CounterSwap bit has to be set on the second chip, 768 * otherwise it will try to use the same pins as the 769 * first chip. 770 */ 771 if (chip) 772 bits = CounterSwap; 773 774 ni_660x_write_register(dev, chip, bits, NI660X_CLK_CFG); 775} 776 777static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev, 778 struct comedi_subdevice *s) 779{ 780 struct ni_gpct *counter = s->private; 781 782 ni_tio_handle_interrupt(counter, s); 783 cfc_handle_events(dev, s); 784} 785 786static irqreturn_t ni_660x_interrupt(int irq, void *d) 787{ 788 struct comedi_device *dev = d; 789 struct ni_660x_private *devpriv = dev->private; 790 struct comedi_subdevice *s; 791 unsigned i; 792 unsigned long flags; 793 794 if (!dev->attached) 795 return IRQ_NONE; 796 /* lock to avoid race with comedi_poll */ 797 spin_lock_irqsave(&devpriv->interrupt_lock, flags); 798 smp_mb(); 799 for (i = 0; i < ni_660x_num_counters(dev); ++i) { 800 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)]; 801 ni_660x_handle_gpct_interrupt(dev, s); 802 } 803 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags); 804 return IRQ_HANDLED; 805} 806 807static int ni_660x_input_poll(struct comedi_device *dev, 808 struct comedi_subdevice *s) 809{ 810 struct ni_660x_private *devpriv = dev->private; 811 struct ni_gpct *counter = s->private; 812 unsigned long flags; 813 814 /* lock to avoid race with comedi_poll */ 815 spin_lock_irqsave(&devpriv->interrupt_lock, flags); 816 mite_sync_input_dma(counter->mite_chan, s); 817 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags); 818 return comedi_buf_read_n_available(s); 819} 820 821static int ni_660x_buf_change(struct comedi_device *dev, 822 struct comedi_subdevice *s) 823{ 824 struct ni_660x_private *devpriv = dev->private; 825 struct ni_gpct *counter = s->private; 826 int ret; 827 828 ret = mite_buf_change(mite_ring(devpriv, counter), s); 829 if (ret < 0) 830 return ret; 831 832 return 0; 833} 834 835static int ni_660x_allocate_private(struct comedi_device *dev) 836{ 837 struct ni_660x_private *devpriv; 838 unsigned i; 839 840 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); 841 if (!devpriv) 842 return -ENOMEM; 843 844 spin_lock_init(&devpriv->mite_channel_lock); 845 spin_lock_init(&devpriv->interrupt_lock); 846 spin_lock_init(&devpriv->soft_reg_copy_lock); 847 for (i = 0; i < NUM_PFI_CHANNELS; ++i) 848 devpriv->pfi_output_selects[i] = pfi_output_select_counter; 849 850 return 0; 851} 852 853static int ni_660x_alloc_mite_rings(struct comedi_device *dev) 854{ 855 const struct ni_660x_board *board = dev->board_ptr; 856 struct ni_660x_private *devpriv = dev->private; 857 unsigned i; 858 unsigned j; 859 860 for (i = 0; i < board->n_chips; ++i) { 861 for (j = 0; j < counters_per_chip; ++j) { 862 devpriv->mite_rings[i][j] = 863 mite_alloc_ring(devpriv->mite); 864 if (devpriv->mite_rings[i][j] == NULL) 865 return -ENOMEM; 866 } 867 } 868 return 0; 869} 870 871static void ni_660x_free_mite_rings(struct comedi_device *dev) 872{ 873 const struct ni_660x_board *board = dev->board_ptr; 874 struct ni_660x_private *devpriv = dev->private; 875 unsigned i; 876 unsigned j; 877 878 for (i = 0; i < board->n_chips; ++i) { 879 for (j = 0; j < counters_per_chip; ++j) 880 mite_free_ring(devpriv->mite_rings[i][j]); 881 } 882} 883 884static void init_tio_chip(struct comedi_device *dev, int chipset) 885{ 886 struct ni_660x_private *devpriv = dev->private; 887 unsigned i; 888 889 /* init dma configuration register */ 890 devpriv->dma_configuration_soft_copies[chipset] = 0; 891 for (i = 0; i < MAX_DMA_CHANNEL; ++i) { 892 devpriv->dma_configuration_soft_copies[chipset] |= 893 dma_select_bits(i, dma_selection_none) & dma_select_mask(i); 894 } 895 ni_660x_write_register(dev, chipset, 896 devpriv->dma_configuration_soft_copies[chipset], 897 NI660X_DMA_CFG); 898 for (i = 0; i < NUM_PFI_CHANNELS; ++i) 899 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); 900} 901 902static int ni_660x_dio_insn_bits(struct comedi_device *dev, 903 struct comedi_subdevice *s, 904 struct comedi_insn *insn, unsigned int *data) 905{ 906 unsigned base_bitfield_channel = CR_CHAN(insn->chanspec); 907 908 /* Check if we have to write some bits */ 909 if (data[0]) { 910 s->state &= ~(data[0] << base_bitfield_channel); 911 s->state |= (data[0] & data[1]) << base_bitfield_channel; 912 /* Write out the new digital output lines */ 913 ni_660x_write_register(dev, 0, s->state, NI660X_DIO32_OUTPUT); 914 } 915 /* on return, data[1] contains the value of the digital 916 * input and output lines. */ 917 data[1] = (ni_660x_read_register(dev, 0, NI660X_DIO32_INPUT) >> 918 base_bitfield_channel); 919 920 return insn->n; 921} 922 923static void ni_660x_select_pfi_output(struct comedi_device *dev, 924 unsigned pfi_channel, 925 unsigned output_select) 926{ 927 const struct ni_660x_board *board = dev->board_ptr; 928 static const unsigned counter_4_7_first_pfi = 8; 929 static const unsigned counter_4_7_last_pfi = 23; 930 unsigned active_chipset = 0; 931 unsigned idle_chipset = 0; 932 unsigned active_bits; 933 unsigned idle_bits; 934 935 if (board->n_chips > 1) { 936 if (output_select == pfi_output_select_counter && 937 pfi_channel >= counter_4_7_first_pfi && 938 pfi_channel <= counter_4_7_last_pfi) { 939 active_chipset = 1; 940 idle_chipset = 0; 941 } else { 942 active_chipset = 0; 943 idle_chipset = 1; 944 } 945 } 946 947 if (idle_chipset != active_chipset) { 948 idle_bits = 949 ni_660x_read_register(dev, idle_chipset, 950 IOConfigReg(pfi_channel)); 951 idle_bits &= ~pfi_output_select_mask(pfi_channel); 952 idle_bits |= 953 pfi_output_select_bits(pfi_channel, 954 pfi_output_select_high_Z); 955 ni_660x_write_register(dev, idle_chipset, idle_bits, 956 IOConfigReg(pfi_channel)); 957 } 958 959 active_bits = 960 ni_660x_read_register(dev, active_chipset, 961 IOConfigReg(pfi_channel)); 962 active_bits &= ~pfi_output_select_mask(pfi_channel); 963 active_bits |= pfi_output_select_bits(pfi_channel, output_select); 964 ni_660x_write_register(dev, active_chipset, active_bits, 965 IOConfigReg(pfi_channel)); 966} 967 968static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan, 969 unsigned source) 970{ 971 struct ni_660x_private *devpriv = dev->private; 972 973 if (source > num_pfi_output_selects) 974 return -EINVAL; 975 if (source == pfi_output_select_high_Z) 976 return -EINVAL; 977 if (chan < min_counter_pfi_chan) { 978 if (source == pfi_output_select_counter) 979 return -EINVAL; 980 } else if (chan > max_dio_pfi_chan) { 981 if (source == pfi_output_select_do) 982 return -EINVAL; 983 } 984 985 devpriv->pfi_output_selects[chan] = source; 986 if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan)) 987 ni_660x_select_pfi_output(dev, chan, 988 devpriv->pfi_output_selects[chan]); 989 return 0; 990} 991 992static int ni_660x_dio_insn_config(struct comedi_device *dev, 993 struct comedi_subdevice *s, 994 struct comedi_insn *insn, 995 unsigned int *data) 996{ 997 struct ni_660x_private *devpriv = dev->private; 998 unsigned int chan = CR_CHAN(insn->chanspec); 999 uint64_t bit = 1ULL << chan; 1000 unsigned int val; 1001 int ret; 1002 1003 switch (data[0]) { 1004 case INSN_CONFIG_DIO_OUTPUT: 1005 devpriv->pfi_direction_bits |= bit; 1006 ni_660x_select_pfi_output(dev, chan, 1007 devpriv->pfi_output_selects[chan]); 1008 break; 1009 1010 case INSN_CONFIG_DIO_INPUT: 1011 devpriv->pfi_direction_bits &= ~bit; 1012 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z); 1013 break; 1014 1015 case INSN_CONFIG_DIO_QUERY: 1016 data[1] = (devpriv->pfi_direction_bits & bit) ? COMEDI_OUTPUT 1017 : COMEDI_INPUT; 1018 break; 1019 1020 case INSN_CONFIG_SET_ROUTING: 1021 ret = ni_660x_set_pfi_routing(dev, chan, data[1]); 1022 if (ret) 1023 return ret; 1024 break; 1025 1026 case INSN_CONFIG_GET_ROUTING: 1027 data[1] = devpriv->pfi_output_selects[chan]; 1028 break; 1029 1030 case INSN_CONFIG_FILTER: 1031 val = ni_660x_read_register(dev, 0, IOConfigReg(chan)); 1032 val &= ~pfi_input_select_mask(chan); 1033 val |= pfi_input_select_bits(chan, data[1]); 1034 ni_660x_write_register(dev, 0, val, IOConfigReg(chan)); 1035 break; 1036 1037 default: 1038 return -EINVAL; 1039 } 1040 1041 return insn->n; 1042} 1043 1044static int ni_660x_auto_attach(struct comedi_device *dev, 1045 unsigned long context) 1046{ 1047 struct pci_dev *pcidev = comedi_to_pci_dev(dev); 1048 const struct ni_660x_board *board = NULL; 1049 struct ni_660x_private *devpriv; 1050 struct comedi_subdevice *s; 1051 int ret; 1052 unsigned i; 1053 unsigned global_interrupt_config_bits; 1054 1055 if (context < ARRAY_SIZE(ni_660x_boards)) 1056 board = &ni_660x_boards[context]; 1057 if (!board) 1058 return -ENODEV; 1059 dev->board_ptr = board; 1060 dev->board_name = board->name; 1061 1062 ret = comedi_pci_enable(dev); 1063 if (ret) 1064 return ret; 1065 1066 ret = ni_660x_allocate_private(dev); 1067 if (ret < 0) 1068 return ret; 1069 devpriv = dev->private; 1070 1071 devpriv->mite = mite_alloc(pcidev); 1072 if (!devpriv->mite) 1073 return -ENOMEM; 1074 1075 ret = mite_setup2(dev, devpriv->mite, true); 1076 if (ret < 0) 1077 return ret; 1078 1079 ret = ni_660x_alloc_mite_rings(dev); 1080 if (ret < 0) 1081 return ret; 1082 1083 ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS); 1084 if (ret) 1085 return ret; 1086 1087 s = &dev->subdevices[0]; 1088 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */ 1089 s->type = COMEDI_SUBD_UNUSED; 1090 1091 s = &dev->subdevices[NI_660X_DIO_SUBDEV]; 1092 /* DIGITAL I/O SUBDEVICE */ 1093 s->type = COMEDI_SUBD_DIO; 1094 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 1095 s->n_chan = NUM_PFI_CHANNELS; 1096 s->maxdata = 1; 1097 s->range_table = &range_digital; 1098 s->insn_bits = ni_660x_dio_insn_bits; 1099 s->insn_config = ni_660x_dio_insn_config; 1100 /* we use the ioconfig registers to control dio direction, so zero 1101 output enables in stc dio control reg */ 1102 ni_660x_write_register(dev, 0, 0, NI660X_STC_DIO_CONTROL); 1103 1104 devpriv->counter_dev = ni_gpct_device_construct(dev, 1105 &ni_gpct_write_register, 1106 &ni_gpct_read_register, 1107 ni_gpct_variant_660x, 1108 ni_660x_num_counters 1109 (dev)); 1110 if (devpriv->counter_dev == NULL) 1111 return -ENOMEM; 1112 for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { 1113 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)]; 1114 if (i < ni_660x_num_counters(dev)) { 1115 s->type = COMEDI_SUBD_COUNTER; 1116 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | 1117 SDF_LSAMPL | SDF_CMD_READ; 1118 s->n_chan = 3; 1119 s->maxdata = 0xffffffff; 1120 s->insn_read = ni_tio_insn_read; 1121 s->insn_write = ni_tio_insn_write; 1122 s->insn_config = ni_tio_insn_config; 1123 s->do_cmd = &ni_660x_cmd; 1124 s->len_chanlist = 1; 1125 s->do_cmdtest = ni_tio_cmdtest; 1126 s->cancel = &ni_660x_cancel; 1127 s->poll = &ni_660x_input_poll; 1128 s->async_dma_dir = DMA_BIDIRECTIONAL; 1129 s->buf_change = &ni_660x_buf_change; 1130 s->private = &devpriv->counter_dev->counters[i]; 1131 1132 devpriv->counter_dev->counters[i].chip_index = 1133 i / counters_per_chip; 1134 devpriv->counter_dev->counters[i].counter_index = 1135 i % counters_per_chip; 1136 } else { 1137 s->type = COMEDI_SUBD_UNUSED; 1138 } 1139 } 1140 for (i = 0; i < board->n_chips; ++i) 1141 init_tio_chip(dev, i); 1142 1143 for (i = 0; i < ni_660x_num_counters(dev); ++i) 1144 ni_tio_init_counter(&devpriv->counter_dev->counters[i]); 1145 1146 for (i = 0; i < NUM_PFI_CHANNELS; ++i) { 1147 if (i < min_counter_pfi_chan) 1148 ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); 1149 else 1150 ni_660x_set_pfi_routing(dev, i, 1151 pfi_output_select_counter); 1152 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z); 1153 } 1154 /* to be safe, set counterswap bits on tio chips after all the counter 1155 outputs have been set to high impedance mode */ 1156 for (i = 0; i < board->n_chips; ++i) 1157 set_tio_counterswap(dev, i); 1158 1159 ret = request_irq(pcidev->irq, ni_660x_interrupt, IRQF_SHARED, 1160 dev->board_name, dev); 1161 if (ret < 0) { 1162 dev_warn(dev->class_dev, " irq not available\n"); 1163 return ret; 1164 } 1165 dev->irq = pcidev->irq; 1166 global_interrupt_config_bits = Global_Int_Enable_Bit; 1167 if (board->n_chips > 1) 1168 global_interrupt_config_bits |= Cascade_Int_Enable_Bit; 1169 ni_660x_write_register(dev, 0, global_interrupt_config_bits, 1170 NI660X_GLOBAL_INT_CFG); 1171 1172 return 0; 1173} 1174 1175static void ni_660x_detach(struct comedi_device *dev) 1176{ 1177 struct ni_660x_private *devpriv = dev->private; 1178 1179 if (dev->irq) 1180 free_irq(dev->irq, dev); 1181 if (devpriv) { 1182 if (devpriv->counter_dev) 1183 ni_gpct_device_destroy(devpriv->counter_dev); 1184 ni_660x_free_mite_rings(dev); 1185 mite_detach(devpriv->mite); 1186 } 1187 if (dev->mmio) 1188 iounmap(dev->mmio); 1189 comedi_pci_disable(dev); 1190} 1191 1192static struct comedi_driver ni_660x_driver = { 1193 .driver_name = "ni_660x", 1194 .module = THIS_MODULE, 1195 .auto_attach = ni_660x_auto_attach, 1196 .detach = ni_660x_detach, 1197}; 1198 1199static int ni_660x_pci_probe(struct pci_dev *dev, 1200 const struct pci_device_id *id) 1201{ 1202 return comedi_pci_auto_config(dev, &ni_660x_driver, id->driver_data); 1203} 1204 1205static const struct pci_device_id ni_660x_pci_table[] = { 1206 { PCI_VDEVICE(NI, 0x1310), BOARD_PCI6602 }, 1207 { PCI_VDEVICE(NI, 0x1360), BOARD_PXI6602 }, 1208 { PCI_VDEVICE(NI, 0x2c60), BOARD_PCI6601 }, 1209 { PCI_VDEVICE(NI, 0x2cc0), BOARD_PXI6608 }, 1210 { PCI_VDEVICE(NI, 0x1e40), BOARD_PXI6624 }, 1211 { 0 } 1212}; 1213MODULE_DEVICE_TABLE(pci, ni_660x_pci_table); 1214 1215static struct pci_driver ni_660x_pci_driver = { 1216 .name = "ni_660x", 1217 .id_table = ni_660x_pci_table, 1218 .probe = ni_660x_pci_probe, 1219 .remove = comedi_pci_auto_unconfig, 1220}; 1221module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver); 1222 1223MODULE_AUTHOR("Comedi http://www.comedi.org"); 1224MODULE_DESCRIPTION("Comedi low-level driver"); 1225MODULE_LICENSE("GPL"); 1226