1/* 2 comedi/drivers/ni_mio_common.c 3 Hardware driver for DAQ-STC based boards 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> 7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18*/ 19 20/* 21 This file is meant to be included by another file, e.g., 22 ni_atmio.c or ni_pcimio.c. 23 24 Interrupt support originally added by Truxton Fulton 25 <trux@truxton.com> 26 27 References (from ftp://ftp.natinst.com/support/manuals): 28 29 340747b.pdf AT-MIO E series Register Level Programmer Manual 30 341079b.pdf PCI E Series RLPM 31 340934b.pdf DAQ-STC reference manual 32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/) 33 release_ni611x.pdf 34 release_ni67xx.pdf 35 Other possibly relevant info: 36 37 320517c.pdf User manual (obsolete) 38 320517f.pdf User manual (new) 39 320889a.pdf delete 40 320906c.pdf maximum signal ratings 41 321066a.pdf about 16x 42 321791a.pdf discontinuation of at-mio-16e-10 rev. c 43 321808a.pdf about at-mio-16e-10 rev P 44 321837a.pdf discontinuation of at-mio-16de-10 rev d 45 321838a.pdf about at-mio-16de-10 rev N 46 47 ISSUES: 48 49 - the interrupt routine needs to be cleaned up 50 51 2006-02-07: S-Series PCI-6143: Support has been added but is not 52 fully tested as yet. Terry Barnaby, BEAM Ltd. 53*/ 54 55#include <linux/interrupt.h> 56#include <linux/sched.h> 57#include <linux/delay.h> 58#include "8255.h" 59#include "mite.h" 60#include "comedi_fc.h" 61 62/* A timeout count */ 63#define NI_TIMEOUT 1000 64static const unsigned old_RTSI_clock_channel = 7; 65 66/* Note: this table must match the ai_gain_* definitions */ 67static const short ni_gainlkup[][16] = { 68 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7, 69 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, 70 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107}, 71 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7, 72 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, 73 [ai_gain_4] = {0, 1, 4, 7}, 74 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002, 75 0x003, 0x004, 0x005, 0x006}, 76 [ai_gain_622x] = {0, 1, 4, 5}, 77 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7}, 78 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 79}; 80 81static const struct comedi_lrange range_ni_E_ai = { 82 16, { 83 BIP_RANGE(10), 84 BIP_RANGE(5), 85 BIP_RANGE(2.5), 86 BIP_RANGE(1), 87 BIP_RANGE(0.5), 88 BIP_RANGE(0.25), 89 BIP_RANGE(0.1), 90 BIP_RANGE(0.05), 91 UNI_RANGE(20), 92 UNI_RANGE(10), 93 UNI_RANGE(5), 94 UNI_RANGE(2), 95 UNI_RANGE(1), 96 UNI_RANGE(0.5), 97 UNI_RANGE(0.2), 98 UNI_RANGE(0.1) 99 } 100}; 101 102static const struct comedi_lrange range_ni_E_ai_limited = { 103 8, { 104 BIP_RANGE(10), 105 BIP_RANGE(5), 106 BIP_RANGE(1), 107 BIP_RANGE(0.1), 108 UNI_RANGE(10), 109 UNI_RANGE(5), 110 UNI_RANGE(1), 111 UNI_RANGE(0.1) 112 } 113}; 114 115static const struct comedi_lrange range_ni_E_ai_limited14 = { 116 14, { 117 BIP_RANGE(10), 118 BIP_RANGE(5), 119 BIP_RANGE(2), 120 BIP_RANGE(1), 121 BIP_RANGE(0.5), 122 BIP_RANGE(0.2), 123 BIP_RANGE(0.1), 124 UNI_RANGE(10), 125 UNI_RANGE(5), 126 UNI_RANGE(2), 127 UNI_RANGE(1), 128 UNI_RANGE(0.5), 129 UNI_RANGE(0.2), 130 UNI_RANGE(0.1) 131 } 132}; 133 134static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 135 4, { 136 BIP_RANGE(10), 137 BIP_RANGE(5), 138 BIP_RANGE(0.5), 139 BIP_RANGE(0.05) 140 } 141}; 142 143static const struct comedi_lrange range_ni_E_ai_611x = { 144 8, { 145 BIP_RANGE(50), 146 BIP_RANGE(20), 147 BIP_RANGE(10), 148 BIP_RANGE(5), 149 BIP_RANGE(2), 150 BIP_RANGE(1), 151 BIP_RANGE(0.5), 152 BIP_RANGE(0.2) 153 } 154}; 155 156static const struct comedi_lrange range_ni_M_ai_622x = { 157 4, { 158 BIP_RANGE(10), 159 BIP_RANGE(5), 160 BIP_RANGE(1), 161 BIP_RANGE(0.2) 162 } 163}; 164 165static const struct comedi_lrange range_ni_M_ai_628x = { 166 7, { 167 BIP_RANGE(10), 168 BIP_RANGE(5), 169 BIP_RANGE(2), 170 BIP_RANGE(1), 171 BIP_RANGE(0.5), 172 BIP_RANGE(0.2), 173 BIP_RANGE(0.1) 174 } 175}; 176 177static const struct comedi_lrange range_ni_E_ao_ext = { 178 4, { 179 BIP_RANGE(10), 180 UNI_RANGE(10), 181 RANGE_ext(-1, 1), 182 RANGE_ext(0, 1) 183 } 184}; 185 186static const struct comedi_lrange *const ni_range_lkup[] = { 187 [ai_gain_16] = &range_ni_E_ai, 188 [ai_gain_8] = &range_ni_E_ai_limited, 189 [ai_gain_14] = &range_ni_E_ai_limited14, 190 [ai_gain_4] = &range_ni_E_ai_bipolar4, 191 [ai_gain_611x] = &range_ni_E_ai_611x, 192 [ai_gain_622x] = &range_ni_M_ai_622x, 193 [ai_gain_628x] = &range_ni_M_ai_628x, 194 [ai_gain_6143] = &range_bipolar5 195}; 196 197enum aimodes { 198 AIMODE_NONE = 0, 199 AIMODE_HALF_FULL = 1, 200 AIMODE_SCAN = 2, 201 AIMODE_SAMPLE = 3, 202}; 203 204enum ni_common_subdevices { 205 NI_AI_SUBDEV, 206 NI_AO_SUBDEV, 207 NI_DIO_SUBDEV, 208 NI_8255_DIO_SUBDEV, 209 NI_UNUSED_SUBDEV, 210 NI_CALIBRATION_SUBDEV, 211 NI_EEPROM_SUBDEV, 212 NI_PFI_DIO_SUBDEV, 213 NI_CS5529_CALIBRATION_SUBDEV, 214 NI_SERIAL_SUBDEV, 215 NI_RTSI_SUBDEV, 216 NI_GPCT0_SUBDEV, 217 NI_GPCT1_SUBDEV, 218 NI_FREQ_OUT_SUBDEV, 219 NI_NUM_SUBDEVICES 220}; 221static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index) 222{ 223 switch (counter_index) { 224 case 0: 225 return NI_GPCT0_SUBDEV; 226 case 1: 227 return NI_GPCT1_SUBDEV; 228 default: 229 break; 230 } 231 BUG(); 232 return NI_GPCT0_SUBDEV; 233} 234 235enum timebase_nanoseconds { 236 TIMEBASE_1_NS = 50, 237 TIMEBASE_2_NS = 10000 238}; 239 240#define SERIAL_DISABLED 0 241#define SERIAL_600NS 600 242#define SERIAL_1_2US 1200 243#define SERIAL_10US 10000 244 245static const int num_adc_stages_611x = 3; 246 247static void ni_writel(struct comedi_device *dev, uint32_t data, int reg) 248{ 249 if (dev->mmio) 250 writel(data, dev->mmio + reg); 251 252 outl(data, dev->iobase + reg); 253} 254 255static void ni_writew(struct comedi_device *dev, uint16_t data, int reg) 256{ 257 if (dev->mmio) 258 writew(data, dev->mmio + reg); 259 260 outw(data, dev->iobase + reg); 261} 262 263static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg) 264{ 265 if (dev->mmio) 266 writeb(data, dev->mmio + reg); 267 268 outb(data, dev->iobase + reg); 269} 270 271static uint32_t ni_readl(struct comedi_device *dev, int reg) 272{ 273 if (dev->mmio) 274 return readl(dev->mmio + reg); 275 276 return inl(dev->iobase + reg); 277} 278 279static uint16_t ni_readw(struct comedi_device *dev, int reg) 280{ 281 if (dev->mmio) 282 return readw(dev->mmio + reg); 283 284 return inw(dev->iobase + reg); 285} 286 287static uint8_t ni_readb(struct comedi_device *dev, int reg) 288{ 289 if (dev->mmio) 290 return readb(dev->mmio + reg); 291 292 return inb(dev->iobase + reg); 293} 294 295/* 296 * We automatically take advantage of STC registers that can be 297 * read/written directly in the I/O space of the board. 298 * 299 * The AT-MIO and DAQCard devices map the low 8 STC registers to 300 * iobase+reg*2. 301 * 302 * Most PCIMIO devices also map the low 8 STC registers but the 303 * 611x devices map the read registers to iobase+(addr-1)*2. 304 * For now non-windowed STC access is disabled if a PCIMIO device 305 * is detected (devpriv->mite has been initialized). 306 * 307 * The M series devices do not used windowed registers for the 308 * STC registers. The functions below handle the mapping of the 309 * windowed STC registers to the m series register offsets. 310 */ 311 312static void m_series_stc_writel(struct comedi_device *dev, 313 uint32_t data, int reg) 314{ 315 unsigned offset; 316 317 switch (reg) { 318 case AI_SC_Load_A_Registers: 319 offset = M_Offset_AI_SC_Load_A; 320 break; 321 case AI_SI_Load_A_Registers: 322 offset = M_Offset_AI_SI_Load_A; 323 break; 324 case AO_BC_Load_A_Register: 325 offset = M_Offset_AO_BC_Load_A; 326 break; 327 case AO_UC_Load_A_Register: 328 offset = M_Offset_AO_UC_Load_A; 329 break; 330 case AO_UI_Load_A_Register: 331 offset = M_Offset_AO_UI_Load_A; 332 break; 333 case G_Load_A_Register(0): 334 offset = M_Offset_G0_Load_A; 335 break; 336 case G_Load_A_Register(1): 337 offset = M_Offset_G1_Load_A; 338 break; 339 case G_Load_B_Register(0): 340 offset = M_Offset_G0_Load_B; 341 break; 342 case G_Load_B_Register(1): 343 offset = M_Offset_G1_Load_B; 344 break; 345 default: 346 dev_warn(dev->class_dev, 347 "%s: bug! unhandled register=0x%x in switch\n", 348 __func__, reg); 349 return; 350 } 351 ni_writel(dev, data, offset); 352} 353 354static void m_series_stc_writew(struct comedi_device *dev, 355 uint16_t data, int reg) 356{ 357 unsigned offset; 358 359 switch (reg) { 360 case ADC_FIFO_Clear: 361 offset = M_Offset_AI_FIFO_Clear; 362 break; 363 case AI_Command_1_Register: 364 offset = M_Offset_AI_Command_1; 365 break; 366 case AI_Command_2_Register: 367 offset = M_Offset_AI_Command_2; 368 break; 369 case AI_Mode_1_Register: 370 offset = M_Offset_AI_Mode_1; 371 break; 372 case AI_Mode_2_Register: 373 offset = M_Offset_AI_Mode_2; 374 break; 375 case AI_Mode_3_Register: 376 offset = M_Offset_AI_Mode_3; 377 break; 378 case AI_Output_Control_Register: 379 offset = M_Offset_AI_Output_Control; 380 break; 381 case AI_Personal_Register: 382 offset = M_Offset_AI_Personal; 383 break; 384 case AI_SI2_Load_A_Register: 385 /* this is a 32 bit register on m series boards */ 386 ni_writel(dev, data, M_Offset_AI_SI2_Load_A); 387 return; 388 case AI_SI2_Load_B_Register: 389 /* this is a 32 bit register on m series boards */ 390 ni_writel(dev, data, M_Offset_AI_SI2_Load_B); 391 return; 392 case AI_START_STOP_Select_Register: 393 offset = M_Offset_AI_START_STOP_Select; 394 break; 395 case AI_Trigger_Select_Register: 396 offset = M_Offset_AI_Trigger_Select; 397 break; 398 case Analog_Trigger_Etc_Register: 399 offset = M_Offset_Analog_Trigger_Etc; 400 break; 401 case AO_Command_1_Register: 402 offset = M_Offset_AO_Command_1; 403 break; 404 case AO_Command_2_Register: 405 offset = M_Offset_AO_Command_2; 406 break; 407 case AO_Mode_1_Register: 408 offset = M_Offset_AO_Mode_1; 409 break; 410 case AO_Mode_2_Register: 411 offset = M_Offset_AO_Mode_2; 412 break; 413 case AO_Mode_3_Register: 414 offset = M_Offset_AO_Mode_3; 415 break; 416 case AO_Output_Control_Register: 417 offset = M_Offset_AO_Output_Control; 418 break; 419 case AO_Personal_Register: 420 offset = M_Offset_AO_Personal; 421 break; 422 case AO_Start_Select_Register: 423 offset = M_Offset_AO_Start_Select; 424 break; 425 case AO_Trigger_Select_Register: 426 offset = M_Offset_AO_Trigger_Select; 427 break; 428 case Clock_and_FOUT_Register: 429 offset = M_Offset_Clock_and_FOUT; 430 break; 431 case Configuration_Memory_Clear: 432 offset = M_Offset_Configuration_Memory_Clear; 433 break; 434 case DAC_FIFO_Clear: 435 offset = M_Offset_AO_FIFO_Clear; 436 break; 437 case DIO_Control_Register: 438 dev_dbg(dev->class_dev, 439 "%s: FIXME: register 0x%x does not map cleanly on to m-series boards\n", 440 __func__, reg); 441 return; 442 case G_Autoincrement_Register(0): 443 offset = M_Offset_G0_Autoincrement; 444 break; 445 case G_Autoincrement_Register(1): 446 offset = M_Offset_G1_Autoincrement; 447 break; 448 case G_Command_Register(0): 449 offset = M_Offset_G0_Command; 450 break; 451 case G_Command_Register(1): 452 offset = M_Offset_G1_Command; 453 break; 454 case G_Input_Select_Register(0): 455 offset = M_Offset_G0_Input_Select; 456 break; 457 case G_Input_Select_Register(1): 458 offset = M_Offset_G1_Input_Select; 459 break; 460 case G_Mode_Register(0): 461 offset = M_Offset_G0_Mode; 462 break; 463 case G_Mode_Register(1): 464 offset = M_Offset_G1_Mode; 465 break; 466 case Interrupt_A_Ack_Register: 467 offset = M_Offset_Interrupt_A_Ack; 468 break; 469 case Interrupt_A_Enable_Register: 470 offset = M_Offset_Interrupt_A_Enable; 471 break; 472 case Interrupt_B_Ack_Register: 473 offset = M_Offset_Interrupt_B_Ack; 474 break; 475 case Interrupt_B_Enable_Register: 476 offset = M_Offset_Interrupt_B_Enable; 477 break; 478 case Interrupt_Control_Register: 479 offset = M_Offset_Interrupt_Control; 480 break; 481 case IO_Bidirection_Pin_Register: 482 offset = M_Offset_IO_Bidirection_Pin; 483 break; 484 case Joint_Reset_Register: 485 offset = M_Offset_Joint_Reset; 486 break; 487 case RTSI_Trig_A_Output_Register: 488 offset = M_Offset_RTSI_Trig_A_Output; 489 break; 490 case RTSI_Trig_B_Output_Register: 491 offset = M_Offset_RTSI_Trig_B_Output; 492 break; 493 case RTSI_Trig_Direction_Register: 494 offset = M_Offset_RTSI_Trig_Direction; 495 break; 496 /* 497 * FIXME: DIO_Output_Register (16 bit reg) is replaced by 498 * M_Offset_Static_Digital_Output (32 bit) and 499 * M_Offset_SCXI_Serial_Data_Out (8 bit) 500 */ 501 default: 502 dev_warn(dev->class_dev, 503 "%s: bug! unhandled register=0x%x in switch\n", 504 __func__, reg); 505 return; 506 } 507 ni_writew(dev, data, offset); 508} 509 510static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg) 511{ 512 unsigned offset; 513 514 switch (reg) { 515 case G_HW_Save_Register(0): 516 offset = M_Offset_G0_HW_Save; 517 break; 518 case G_HW_Save_Register(1): 519 offset = M_Offset_G1_HW_Save; 520 break; 521 case G_Save_Register(0): 522 offset = M_Offset_G0_Save; 523 break; 524 case G_Save_Register(1): 525 offset = M_Offset_G1_Save; 526 break; 527 default: 528 dev_warn(dev->class_dev, 529 "%s: bug! unhandled register=0x%x in switch\n", 530 __func__, reg); 531 return 0; 532 } 533 return ni_readl(dev, offset); 534} 535 536static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg) 537{ 538 unsigned offset; 539 540 switch (reg) { 541 case AI_Status_1_Register: 542 offset = M_Offset_AI_Status_1; 543 break; 544 case AO_Status_1_Register: 545 offset = M_Offset_AO_Status_1; 546 break; 547 case AO_Status_2_Register: 548 offset = M_Offset_AO_Status_2; 549 break; 550 case DIO_Serial_Input_Register: 551 return ni_readb(dev, M_Offset_SCXI_Serial_Data_In); 552 case Joint_Status_1_Register: 553 offset = M_Offset_Joint_Status_1; 554 break; 555 case Joint_Status_2_Register: 556 offset = M_Offset_Joint_Status_2; 557 break; 558 case G_Status_Register: 559 offset = M_Offset_G01_Status; 560 break; 561 default: 562 dev_warn(dev->class_dev, 563 "%s: bug! unhandled register=0x%x in switch\n", 564 __func__, reg); 565 return 0; 566 } 567 return ni_readw(dev, offset); 568} 569 570static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) 571{ 572 struct ni_private *devpriv = dev->private; 573 unsigned long flags; 574 575 if (devpriv->is_m_series) { 576 m_series_stc_writew(dev, data, reg); 577 } else { 578 spin_lock_irqsave(&devpriv->window_lock, flags); 579 if (!devpriv->mite && reg < 8) { 580 ni_writew(dev, data, reg * 2); 581 } else { 582 ni_writew(dev, reg, Window_Address); 583 ni_writew(dev, data, Window_Data); 584 } 585 spin_unlock_irqrestore(&devpriv->window_lock, flags); 586 } 587} 588 589static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg) 590{ 591 struct ni_private *devpriv = dev->private; 592 593 if (devpriv->is_m_series) { 594 m_series_stc_writel(dev, data, reg); 595 } else { 596 ni_stc_writew(dev, data >> 16, reg); 597 ni_stc_writew(dev, data & 0xffff, reg + 1); 598 } 599} 600 601static uint16_t ni_stc_readw(struct comedi_device *dev, int reg) 602{ 603 struct ni_private *devpriv = dev->private; 604 unsigned long flags; 605 uint16_t val; 606 607 if (devpriv->is_m_series) { 608 val = m_series_stc_readw(dev, reg); 609 } else { 610 spin_lock_irqsave(&devpriv->window_lock, flags); 611 if (!devpriv->mite && reg < 8) { 612 val = ni_readw(dev, reg * 2); 613 } else { 614 ni_writew(dev, reg, Window_Address); 615 val = ni_readw(dev, Window_Data); 616 } 617 spin_unlock_irqrestore(&devpriv->window_lock, flags); 618 } 619 return val; 620} 621 622static uint32_t ni_stc_readl(struct comedi_device *dev, int reg) 623{ 624 struct ni_private *devpriv = dev->private; 625 uint32_t val; 626 627 if (devpriv->is_m_series) { 628 val = m_series_stc_readl(dev, reg); 629 } else { 630 val = ni_stc_readw(dev, reg) << 16; 631 val |= ni_stc_readw(dev, reg + 1); 632 } 633 return val; 634} 635 636static inline void ni_set_bitfield(struct comedi_device *dev, int reg, 637 unsigned bit_mask, unsigned bit_values) 638{ 639 struct ni_private *devpriv = dev->private; 640 unsigned long flags; 641 642 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 643 switch (reg) { 644 case Interrupt_A_Enable_Register: 645 devpriv->int_a_enable_reg &= ~bit_mask; 646 devpriv->int_a_enable_reg |= bit_values & bit_mask; 647 ni_stc_writew(dev, devpriv->int_a_enable_reg, 648 Interrupt_A_Enable_Register); 649 break; 650 case Interrupt_B_Enable_Register: 651 devpriv->int_b_enable_reg &= ~bit_mask; 652 devpriv->int_b_enable_reg |= bit_values & bit_mask; 653 ni_stc_writew(dev, devpriv->int_b_enable_reg, 654 Interrupt_B_Enable_Register); 655 break; 656 case IO_Bidirection_Pin_Register: 657 devpriv->io_bidirection_pin_reg &= ~bit_mask; 658 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; 659 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, 660 IO_Bidirection_Pin_Register); 661 break; 662 case AI_AO_Select: 663 devpriv->ai_ao_select_reg &= ~bit_mask; 664 devpriv->ai_ao_select_reg |= bit_values & bit_mask; 665 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select); 666 break; 667 case G0_G1_Select: 668 devpriv->g0_g1_select_reg &= ~bit_mask; 669 devpriv->g0_g1_select_reg |= bit_values & bit_mask; 670 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select); 671 break; 672 default: 673 dev_err(dev->class_dev, 674 "%s called with invalid register %d\n", __func__, reg); 675 break; 676 } 677 mmiowb(); 678 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 679} 680 681#ifdef PCIDMA 682/* DMA channel setup */ 683 684/* negative channel means no channel */ 685static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel) 686{ 687 unsigned bitfield; 688 689 if (channel >= 0) { 690 bitfield = 691 (ni_stc_dma_channel_select_bitfield(channel) << 692 AI_DMA_Select_Shift) & AI_DMA_Select_Mask; 693 } else { 694 bitfield = 0; 695 } 696 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield); 697} 698 699/* negative channel means no channel */ 700static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel) 701{ 702 unsigned bitfield; 703 704 if (channel >= 0) { 705 bitfield = 706 (ni_stc_dma_channel_select_bitfield(channel) << 707 AO_DMA_Select_Shift) & AO_DMA_Select_Mask; 708 } else { 709 bitfield = 0; 710 } 711 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield); 712} 713 714/* negative mite_channel means no channel */ 715static inline void ni_set_gpct_dma_channel(struct comedi_device *dev, 716 unsigned gpct_index, 717 int mite_channel) 718{ 719 unsigned bitfield; 720 721 if (mite_channel >= 0) 722 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel); 723 else 724 bitfield = 0; 725 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index), 726 bitfield); 727} 728 729/* negative mite_channel means no channel */ 730static inline void ni_set_cdo_dma_channel(struct comedi_device *dev, 731 int mite_channel) 732{ 733 struct ni_private *devpriv = dev->private; 734 unsigned long flags; 735 736 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 737 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask; 738 if (mite_channel >= 0) { 739 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits, 740 under the assumption the cdio dma selection works just like ai/ao/gpct. 741 Definitely works for dma channels 0 and 1. */ 742 devpriv->cdio_dma_select_reg |= 743 (ni_stc_dma_channel_select_bitfield(mite_channel) << 744 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask; 745 } 746 ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); 747 mmiowb(); 748 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 749} 750 751static int ni_request_ai_mite_channel(struct comedi_device *dev) 752{ 753 struct ni_private *devpriv = dev->private; 754 unsigned long flags; 755 756 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 757 BUG_ON(devpriv->ai_mite_chan); 758 devpriv->ai_mite_chan = 759 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); 760 if (devpriv->ai_mite_chan == NULL) { 761 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 762 dev_err(dev->class_dev, 763 "failed to reserve mite dma channel for analog input\n"); 764 return -EBUSY; 765 } 766 devpriv->ai_mite_chan->dir = COMEDI_INPUT; 767 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel); 768 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 769 return 0; 770} 771 772static int ni_request_ao_mite_channel(struct comedi_device *dev) 773{ 774 struct ni_private *devpriv = dev->private; 775 unsigned long flags; 776 777 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 778 BUG_ON(devpriv->ao_mite_chan); 779 devpriv->ao_mite_chan = 780 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); 781 if (devpriv->ao_mite_chan == NULL) { 782 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 783 dev_err(dev->class_dev, 784 "failed to reserve mite dma channel for analog outut\n"); 785 return -EBUSY; 786 } 787 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT; 788 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel); 789 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 790 return 0; 791} 792 793static int ni_request_gpct_mite_channel(struct comedi_device *dev, 794 unsigned gpct_index, 795 enum comedi_io_direction direction) 796{ 797 struct ni_private *devpriv = dev->private; 798 unsigned long flags; 799 struct mite_channel *mite_chan; 800 801 BUG_ON(gpct_index >= NUM_GPCT); 802 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 803 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan); 804 mite_chan = 805 mite_request_channel(devpriv->mite, 806 devpriv->gpct_mite_ring[gpct_index]); 807 if (mite_chan == NULL) { 808 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 809 dev_err(dev->class_dev, 810 "failed to reserve mite dma channel for counter\n"); 811 return -EBUSY; 812 } 813 mite_chan->dir = direction; 814 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], 815 mite_chan); 816 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel); 817 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 818 return 0; 819} 820 821#endif /* PCIDMA */ 822 823static int ni_request_cdo_mite_channel(struct comedi_device *dev) 824{ 825#ifdef PCIDMA 826 struct ni_private *devpriv = dev->private; 827 unsigned long flags; 828 829 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 830 BUG_ON(devpriv->cdo_mite_chan); 831 devpriv->cdo_mite_chan = 832 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); 833 if (devpriv->cdo_mite_chan == NULL) { 834 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 835 dev_err(dev->class_dev, 836 "failed to reserve mite dma channel for correlated digital output\n"); 837 return -EBUSY; 838 } 839 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT; 840 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel); 841 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 842#endif /* PCIDMA */ 843 return 0; 844} 845 846static void ni_release_ai_mite_channel(struct comedi_device *dev) 847{ 848#ifdef PCIDMA 849 struct ni_private *devpriv = dev->private; 850 unsigned long flags; 851 852 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 853 if (devpriv->ai_mite_chan) { 854 ni_set_ai_dma_channel(dev, -1); 855 mite_release_channel(devpriv->ai_mite_chan); 856 devpriv->ai_mite_chan = NULL; 857 } 858 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 859#endif /* PCIDMA */ 860} 861 862static void ni_release_ao_mite_channel(struct comedi_device *dev) 863{ 864#ifdef PCIDMA 865 struct ni_private *devpriv = dev->private; 866 unsigned long flags; 867 868 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 869 if (devpriv->ao_mite_chan) { 870 ni_set_ao_dma_channel(dev, -1); 871 mite_release_channel(devpriv->ao_mite_chan); 872 devpriv->ao_mite_chan = NULL; 873 } 874 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 875#endif /* PCIDMA */ 876} 877 878#ifdef PCIDMA 879static void ni_release_gpct_mite_channel(struct comedi_device *dev, 880 unsigned gpct_index) 881{ 882 struct ni_private *devpriv = dev->private; 883 unsigned long flags; 884 885 BUG_ON(gpct_index >= NUM_GPCT); 886 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 887 if (devpriv->counter_dev->counters[gpct_index].mite_chan) { 888 struct mite_channel *mite_chan = 889 devpriv->counter_dev->counters[gpct_index].mite_chan; 890 891 ni_set_gpct_dma_channel(dev, gpct_index, -1); 892 ni_tio_set_mite_channel(&devpriv-> 893 counter_dev->counters[gpct_index], 894 NULL); 895 mite_release_channel(mite_chan); 896 } 897 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 898} 899#endif /* PCIDMA */ 900 901static void ni_release_cdo_mite_channel(struct comedi_device *dev) 902{ 903#ifdef PCIDMA 904 struct ni_private *devpriv = dev->private; 905 unsigned long flags; 906 907 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 908 if (devpriv->cdo_mite_chan) { 909 ni_set_cdo_dma_channel(dev, -1); 910 mite_release_channel(devpriv->cdo_mite_chan); 911 devpriv->cdo_mite_chan = NULL; 912 } 913 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 914#endif /* PCIDMA */ 915} 916 917#ifdef PCIDMA 918static void ni_e_series_enable_second_irq(struct comedi_device *dev, 919 unsigned gpct_index, short enable) 920{ 921 struct ni_private *devpriv = dev->private; 922 uint16_t val = 0; 923 int reg; 924 925 if (devpriv->is_m_series || gpct_index > 1) 926 return; 927 928 /* 929 * e-series boards use the second irq signals to generate 930 * dma requests for their counters 931 */ 932 if (gpct_index == 0) { 933 reg = Second_IRQ_A_Enable_Register; 934 if (enable) 935 val = G0_Gate_Second_Irq_Enable; 936 } else { 937 reg = Second_IRQ_B_Enable_Register; 938 if (enable) 939 val = G1_Gate_Second_Irq_Enable; 940 } 941 ni_stc_writew(dev, val, reg); 942} 943#endif /* PCIDMA */ 944 945static void ni_clear_ai_fifo(struct comedi_device *dev) 946{ 947 struct ni_private *devpriv = dev->private; 948 static const int timeout = 10000; 949 int i; 950 951 if (devpriv->is_6143) { 952 /* Flush the 6143 data FIFO */ 953 ni_writel(dev, 0x10, AIFIFO_Control_6143); 954 ni_writel(dev, 0x00, AIFIFO_Control_6143); 955 /* Wait for complete */ 956 for (i = 0; i < timeout; i++) { 957 if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10)) 958 break; 959 udelay(1); 960 } 961 if (i == timeout) 962 dev_err(dev->class_dev, "FIFO flush timeout\n"); 963 } else { 964 ni_stc_writew(dev, 1, ADC_FIFO_Clear); 965 if (devpriv->is_625x) { 966 ni_writeb(dev, 0, M_Offset_Static_AI_Control(0)); 967 ni_writeb(dev, 1, M_Offset_Static_AI_Control(0)); 968#if 0 969 /* the NI example code does 3 convert pulses for 625x boards, 970 but that appears to be wrong in practice. */ 971 ni_stc_writew(dev, AI_CONVERT_Pulse, 972 AI_Command_1_Register); 973 ni_stc_writew(dev, AI_CONVERT_Pulse, 974 AI_Command_1_Register); 975 ni_stc_writew(dev, AI_CONVERT_Pulse, 976 AI_Command_1_Register); 977#endif 978 } 979 } 980} 981 982static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, 983 int addr) 984{ 985 struct ni_private *devpriv = dev->private; 986 unsigned long flags; 987 988 spin_lock_irqsave(&devpriv->window_lock, flags); 989 ni_writew(dev, addr, AO_Window_Address_611x); 990 ni_writew(dev, data, AO_Window_Data_611x); 991 spin_unlock_irqrestore(&devpriv->window_lock, flags); 992} 993 994static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data, 995 int addr) 996{ 997 struct ni_private *devpriv = dev->private; 998 unsigned long flags; 999 1000 spin_lock_irqsave(&devpriv->window_lock, flags); 1001 ni_writew(dev, addr, AO_Window_Address_611x); 1002 ni_writel(dev, data, AO_Window_Data_611x); 1003 spin_unlock_irqrestore(&devpriv->window_lock, flags); 1004} 1005 1006static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) 1007{ 1008 struct ni_private *devpriv = dev->private; 1009 unsigned long flags; 1010 unsigned short data; 1011 1012 spin_lock_irqsave(&devpriv->window_lock, flags); 1013 ni_writew(dev, addr, AO_Window_Address_611x); 1014 data = ni_readw(dev, AO_Window_Data_611x); 1015 spin_unlock_irqrestore(&devpriv->window_lock, flags); 1016 return data; 1017} 1018 1019/* ni_set_bits( ) allows different parts of the ni_mio_common driver to 1020* share registers (such as Interrupt_A_Register) without interfering with 1021* each other. 1022* 1023* NOTE: the switch/case statements are optimized out for a constant argument 1024* so this is actually quite fast--- If you must wrap another function around this 1025* make it inline to avoid a large speed penalty. 1026* 1027* value should only be 1 or 0. 1028*/ 1029static inline void ni_set_bits(struct comedi_device *dev, int reg, 1030 unsigned bits, unsigned value) 1031{ 1032 unsigned bit_values; 1033 1034 if (value) 1035 bit_values = bits; 1036 else 1037 bit_values = 0; 1038 ni_set_bitfield(dev, reg, bits, bit_values); 1039} 1040 1041#ifdef PCIDMA 1042static void ni_sync_ai_dma(struct comedi_device *dev) 1043{ 1044 struct ni_private *devpriv = dev->private; 1045 struct comedi_subdevice *s = dev->read_subdev; 1046 unsigned long flags; 1047 1048 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1049 if (devpriv->ai_mite_chan) 1050 mite_sync_input_dma(devpriv->ai_mite_chan, s); 1051 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1052} 1053 1054static int ni_ai_drain_dma(struct comedi_device *dev) 1055{ 1056 struct ni_private *devpriv = dev->private; 1057 int i; 1058 static const int timeout = 10000; 1059 unsigned long flags; 1060 int retval = 0; 1061 1062 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1063 if (devpriv->ai_mite_chan) { 1064 for (i = 0; i < timeout; i++) { 1065 if ((ni_stc_readw(dev, AI_Status_1_Register) & 1066 AI_FIFO_Empty_St) 1067 && mite_bytes_in_transit(devpriv->ai_mite_chan) == 1068 0) 1069 break; 1070 udelay(5); 1071 } 1072 if (i == timeout) { 1073 dev_err(dev->class_dev, "%s timed out\n", __func__); 1074 dev_err(dev->class_dev, 1075 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n", 1076 mite_bytes_in_transit(devpriv->ai_mite_chan), 1077 ni_stc_readw(dev, AI_Status_1_Register)); 1078 retval = -1; 1079 } 1080 } 1081 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1082 1083 ni_sync_ai_dma(dev); 1084 1085 return retval; 1086} 1087 1088static void mite_handle_b_linkc(struct mite_struct *mite, 1089 struct comedi_device *dev) 1090{ 1091 struct ni_private *devpriv = dev->private; 1092 struct comedi_subdevice *s = dev->write_subdev; 1093 unsigned long flags; 1094 1095 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1096 if (devpriv->ao_mite_chan) 1097 mite_sync_output_dma(devpriv->ao_mite_chan, s); 1098 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1099} 1100 1101static int ni_ao_wait_for_dma_load(struct comedi_device *dev) 1102{ 1103 static const int timeout = 10000; 1104 int i; 1105 1106 for (i = 0; i < timeout; i++) { 1107 unsigned short b_status; 1108 1109 b_status = ni_stc_readw(dev, AO_Status_1_Register); 1110 if (b_status & AO_FIFO_Half_Full_St) 1111 break; 1112 /* if we poll too often, the pci bus activity seems 1113 to slow the dma transfer down */ 1114 udelay(10); 1115 } 1116 if (i == timeout) { 1117 dev_err(dev->class_dev, "timed out waiting for dma load\n"); 1118 return -EPIPE; 1119 } 1120 return 0; 1121} 1122#endif /* PCIDMA */ 1123 1124#ifndef PCIDMA 1125 1126static void ni_ao_fifo_load(struct comedi_device *dev, 1127 struct comedi_subdevice *s, int n) 1128{ 1129 struct ni_private *devpriv = dev->private; 1130 struct comedi_async *async = s->async; 1131 struct comedi_cmd *cmd = &async->cmd; 1132 int chan; 1133 int i; 1134 unsigned short d; 1135 u32 packed_data; 1136 int range; 1137 int err = 1; 1138 1139 chan = async->cur_chan; 1140 for (i = 0; i < n; i++) { 1141 err &= comedi_buf_get(s, &d); 1142 if (err == 0) 1143 break; 1144 1145 range = CR_RANGE(cmd->chanlist[chan]); 1146 1147 if (devpriv->is_6xxx) { 1148 packed_data = d & 0xffff; 1149 /* 6711 only has 16 bit wide ao fifo */ 1150 if (!devpriv->is_6711) { 1151 err &= comedi_buf_get(s, &d); 1152 if (err == 0) 1153 break; 1154 chan++; 1155 i++; 1156 packed_data |= (d << 16) & 0xffff0000; 1157 } 1158 ni_writel(dev, packed_data, DAC_FIFO_Data_611x); 1159 } else { 1160 ni_writew(dev, d, DAC_FIFO_Data); 1161 } 1162 chan++; 1163 chan %= cmd->chanlist_len; 1164 } 1165 async->cur_chan = chan; 1166 if (err == 0) 1167 async->events |= COMEDI_CB_OVERFLOW; 1168} 1169 1170/* 1171 * There's a small problem if the FIFO gets really low and we 1172 * don't have the data to fill it. Basically, if after we fill 1173 * the FIFO with all the data available, the FIFO is _still_ 1174 * less than half full, we never clear the interrupt. If the 1175 * IRQ is in edge mode, we never get another interrupt, because 1176 * this one wasn't cleared. If in level mode, we get flooded 1177 * with interrupts that we can't fulfill, because nothing ever 1178 * gets put into the buffer. 1179 * 1180 * This kind of situation is recoverable, but it is easier to 1181 * just pretend we had a FIFO underrun, since there is a good 1182 * chance it will happen anyway. This is _not_ the case for 1183 * RT code, as RT code might purposely be running close to the 1184 * metal. Needs to be fixed eventually. 1185 */ 1186static int ni_ao_fifo_half_empty(struct comedi_device *dev, 1187 struct comedi_subdevice *s) 1188{ 1189 const struct ni_board_struct *board = dev->board_ptr; 1190 int n; 1191 1192 n = comedi_buf_read_n_available(s); 1193 if (n == 0) { 1194 s->async->events |= COMEDI_CB_OVERFLOW; 1195 return 0; 1196 } 1197 1198 n /= sizeof(short); 1199 if (n > board->ao_fifo_depth / 2) 1200 n = board->ao_fifo_depth / 2; 1201 1202 ni_ao_fifo_load(dev, s, n); 1203 1204 s->async->events |= COMEDI_CB_BLOCK; 1205 1206 return 1; 1207} 1208 1209static int ni_ao_prep_fifo(struct comedi_device *dev, 1210 struct comedi_subdevice *s) 1211{ 1212 const struct ni_board_struct *board = dev->board_ptr; 1213 struct ni_private *devpriv = dev->private; 1214 int n; 1215 1216 /* reset fifo */ 1217 ni_stc_writew(dev, 1, DAC_FIFO_Clear); 1218 if (devpriv->is_6xxx) 1219 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); 1220 1221 /* load some data */ 1222 n = comedi_buf_read_n_available(s); 1223 if (n == 0) 1224 return 0; 1225 1226 n /= sizeof(short); 1227 if (n > board->ao_fifo_depth) 1228 n = board->ao_fifo_depth; 1229 1230 ni_ao_fifo_load(dev, s, n); 1231 1232 return n; 1233} 1234 1235static void ni_ai_fifo_read(struct comedi_device *dev, 1236 struct comedi_subdevice *s, int n) 1237{ 1238 struct ni_private *devpriv = dev->private; 1239 struct comedi_async *async = s->async; 1240 int i; 1241 1242 if (devpriv->is_611x) { 1243 unsigned short data[2]; 1244 u32 dl; 1245 1246 for (i = 0; i < n / 2; i++) { 1247 dl = ni_readl(dev, ADC_FIFO_Data_611x); 1248 /* This may get the hi/lo data in the wrong order */ 1249 data[0] = (dl >> 16) & 0xffff; 1250 data[1] = dl & 0xffff; 1251 cfc_write_array_to_buffer(s, data, sizeof(data)); 1252 } 1253 /* Check if there's a single sample stuck in the FIFO */ 1254 if (n % 2) { 1255 dl = ni_readl(dev, ADC_FIFO_Data_611x); 1256 data[0] = dl & 0xffff; 1257 cfc_write_to_buffer(s, data[0]); 1258 } 1259 } else if (devpriv->is_6143) { 1260 unsigned short data[2]; 1261 u32 dl; 1262 1263 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ 1264 for (i = 0; i < n / 2; i++) { 1265 dl = ni_readl(dev, AIFIFO_Data_6143); 1266 1267 data[0] = (dl >> 16) & 0xffff; 1268 data[1] = dl & 0xffff; 1269 cfc_write_array_to_buffer(s, data, sizeof(data)); 1270 } 1271 if (n % 2) { 1272 /* Assume there is a single sample stuck in the FIFO */ 1273 /* Get stranded sample into FIFO */ 1274 ni_writel(dev, 0x01, AIFIFO_Control_6143); 1275 dl = ni_readl(dev, AIFIFO_Data_6143); 1276 data[0] = (dl >> 16) & 0xffff; 1277 cfc_write_to_buffer(s, data[0]); 1278 } 1279 } else { 1280 if (n > sizeof(devpriv->ai_fifo_buffer) / 1281 sizeof(devpriv->ai_fifo_buffer[0])) { 1282 dev_err(dev->class_dev, 1283 "bug! ai_fifo_buffer too small\n"); 1284 async->events |= COMEDI_CB_ERROR; 1285 return; 1286 } 1287 for (i = 0; i < n; i++) { 1288 devpriv->ai_fifo_buffer[i] = 1289 ni_readw(dev, ADC_FIFO_Data_Register); 1290 } 1291 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 1292 n * 1293 sizeof(devpriv->ai_fifo_buffer[0])); 1294 } 1295} 1296 1297static void ni_handle_fifo_half_full(struct comedi_device *dev) 1298{ 1299 const struct ni_board_struct *board = dev->board_ptr; 1300 struct comedi_subdevice *s = dev->read_subdev; 1301 int n; 1302 1303 n = board->ai_fifo_depth / 2; 1304 1305 ni_ai_fifo_read(dev, s, n); 1306} 1307#endif 1308 1309/* 1310 Empties the AI fifo 1311*/ 1312static void ni_handle_fifo_dregs(struct comedi_device *dev) 1313{ 1314 struct ni_private *devpriv = dev->private; 1315 struct comedi_subdevice *s = dev->read_subdev; 1316 unsigned short data[2]; 1317 u32 dl; 1318 unsigned short fifo_empty; 1319 int i; 1320 1321 if (devpriv->is_611x) { 1322 while ((ni_stc_readw(dev, AI_Status_1_Register) & 1323 AI_FIFO_Empty_St) == 0) { 1324 dl = ni_readl(dev, ADC_FIFO_Data_611x); 1325 1326 /* This may get the hi/lo data in the wrong order */ 1327 data[0] = (dl >> 16); 1328 data[1] = (dl & 0xffff); 1329 cfc_write_array_to_buffer(s, data, sizeof(data)); 1330 } 1331 } else if (devpriv->is_6143) { 1332 i = 0; 1333 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) { 1334 dl = ni_readl(dev, AIFIFO_Data_6143); 1335 1336 /* This may get the hi/lo data in the wrong order */ 1337 data[0] = (dl >> 16); 1338 data[1] = (dl & 0xffff); 1339 cfc_write_array_to_buffer(s, data, sizeof(data)); 1340 i += 2; 1341 } 1342 /* Check if stranded sample is present */ 1343 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { 1344 /* Get stranded sample into FIFO */ 1345 ni_writel(dev, 0x01, AIFIFO_Control_6143); 1346 dl = ni_readl(dev, AIFIFO_Data_6143); 1347 data[0] = (dl >> 16) & 0xffff; 1348 cfc_write_to_buffer(s, data[0]); 1349 } 1350 1351 } else { 1352 fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) & 1353 AI_FIFO_Empty_St; 1354 while (fifo_empty == 0) { 1355 for (i = 0; 1356 i < 1357 sizeof(devpriv->ai_fifo_buffer) / 1358 sizeof(devpriv->ai_fifo_buffer[0]); i++) { 1359 fifo_empty = ni_stc_readw(dev, 1360 AI_Status_1_Register) & 1361 AI_FIFO_Empty_St; 1362 if (fifo_empty) 1363 break; 1364 devpriv->ai_fifo_buffer[i] = 1365 ni_readw(dev, ADC_FIFO_Data_Register); 1366 } 1367 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 1368 i * 1369 sizeof(devpriv-> 1370 ai_fifo_buffer[0])); 1371 } 1372 } 1373} 1374 1375static void get_last_sample_611x(struct comedi_device *dev) 1376{ 1377 struct ni_private *devpriv = dev->private; 1378 struct comedi_subdevice *s = dev->read_subdev; 1379 unsigned short data; 1380 u32 dl; 1381 1382 if (!devpriv->is_611x) 1383 return; 1384 1385 /* Check if there's a single sample stuck in the FIFO */ 1386 if (ni_readb(dev, XXX_Status) & 0x80) { 1387 dl = ni_readl(dev, ADC_FIFO_Data_611x); 1388 data = (dl & 0xffff); 1389 cfc_write_to_buffer(s, data); 1390 } 1391} 1392 1393static void get_last_sample_6143(struct comedi_device *dev) 1394{ 1395 struct ni_private *devpriv = dev->private; 1396 struct comedi_subdevice *s = dev->read_subdev; 1397 unsigned short data; 1398 u32 dl; 1399 1400 if (!devpriv->is_6143) 1401 return; 1402 1403 /* Check if there's a single sample stuck in the FIFO */ 1404 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { 1405 /* Get stranded sample into FIFO */ 1406 ni_writel(dev, 0x01, AIFIFO_Control_6143); 1407 dl = ni_readl(dev, AIFIFO_Data_6143); 1408 1409 /* This may get the hi/lo data in the wrong order */ 1410 data = (dl >> 16) & 0xffff; 1411 cfc_write_to_buffer(s, data); 1412 } 1413} 1414 1415static void shutdown_ai_command(struct comedi_device *dev) 1416{ 1417 struct comedi_subdevice *s = dev->read_subdev; 1418 1419#ifdef PCIDMA 1420 ni_ai_drain_dma(dev); 1421#endif 1422 ni_handle_fifo_dregs(dev); 1423 get_last_sample_611x(dev); 1424 get_last_sample_6143(dev); 1425 1426 s->async->events |= COMEDI_CB_EOA; 1427} 1428 1429static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s) 1430{ 1431 struct ni_private *devpriv = dev->private; 1432 1433 if (devpriv->aimode == AIMODE_SCAN) { 1434#ifdef PCIDMA 1435 static const int timeout = 10; 1436 int i; 1437 1438 for (i = 0; i < timeout; i++) { 1439 ni_sync_ai_dma(dev); 1440 if ((s->async->events & COMEDI_CB_EOS)) 1441 break; 1442 udelay(1); 1443 } 1444#else 1445 ni_handle_fifo_dregs(dev); 1446 s->async->events |= COMEDI_CB_EOS; 1447#endif 1448 } 1449 /* handle special case of single scan using AI_End_On_End_Of_Scan */ 1450 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) 1451 shutdown_ai_command(dev); 1452} 1453 1454static void handle_gpct_interrupt(struct comedi_device *dev, 1455 unsigned short counter_index) 1456{ 1457#ifdef PCIDMA 1458 struct ni_private *devpriv = dev->private; 1459 struct comedi_subdevice *s; 1460 1461 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)]; 1462 1463 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], 1464 s); 1465 cfc_handle_events(dev, s); 1466#endif 1467} 1468 1469static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) 1470{ 1471 unsigned short ack = 0; 1472 1473 if (a_status & AI_SC_TC_St) 1474 ack |= AI_SC_TC_Interrupt_Ack; 1475 if (a_status & AI_START1_St) 1476 ack |= AI_START1_Interrupt_Ack; 1477 if (a_status & AI_START_St) 1478 ack |= AI_START_Interrupt_Ack; 1479 if (a_status & AI_STOP_St) 1480 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */ 1481 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */; 1482 if (ack) 1483 ni_stc_writew(dev, ack, Interrupt_A_Ack_Register); 1484} 1485 1486static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, 1487 unsigned ai_mite_status) 1488{ 1489 struct comedi_subdevice *s = dev->read_subdev; 1490 struct comedi_cmd *cmd = &s->async->cmd; 1491 1492 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */ 1493 if (s->type == COMEDI_SUBD_UNUSED) 1494 return; 1495 1496#ifdef PCIDMA 1497 if (ai_mite_status & CHSR_LINKC) 1498 ni_sync_ai_dma(dev); 1499 1500 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | 1501 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | 1502 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { 1503 dev_err(dev->class_dev, 1504 "unknown mite interrupt (ai_mite_status=%08x)\n", 1505 ai_mite_status); 1506 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1507 /* disable_irq(dev->irq); */ 1508 } 1509#endif 1510 1511 /* test for all uncommon interrupt events at the same time */ 1512 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St | 1513 AI_SC_TC_St | AI_START1_St)) { 1514 if (status == 0xffff) { 1515 dev_err(dev->class_dev, "Card removed?\n"); 1516 /* we probably aren't even running a command now, 1517 * so it's a good idea to be careful. */ 1518 if (comedi_is_subdevice_running(s)) { 1519 s->async->events |= 1520 COMEDI_CB_ERROR | COMEDI_CB_EOA; 1521 cfc_handle_events(dev, s); 1522 } 1523 return; 1524 } 1525 if (status & (AI_Overrun_St | AI_Overflow_St | 1526 AI_SC_TC_Error_St)) { 1527 dev_err(dev->class_dev, "ai error a_status=%04x\n", 1528 status); 1529 1530 shutdown_ai_command(dev); 1531 1532 s->async->events |= COMEDI_CB_ERROR; 1533 if (status & (AI_Overrun_St | AI_Overflow_St)) 1534 s->async->events |= COMEDI_CB_OVERFLOW; 1535 1536 cfc_handle_events(dev, s); 1537 return; 1538 } 1539 if (status & AI_SC_TC_St) { 1540 if (cmd->stop_src == TRIG_COUNT) 1541 shutdown_ai_command(dev); 1542 } 1543 } 1544#ifndef PCIDMA 1545 if (status & AI_FIFO_Half_Full_St) { 1546 int i; 1547 static const int timeout = 10; 1548 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we 1549 *fail to get the fifo less than half full, so loop to be sure.*/ 1550 for (i = 0; i < timeout; ++i) { 1551 ni_handle_fifo_half_full(dev); 1552 if ((ni_stc_readw(dev, AI_Status_1_Register) & 1553 AI_FIFO_Half_Full_St) == 0) 1554 break; 1555 } 1556 } 1557#endif /* !PCIDMA */ 1558 1559 if ((status & AI_STOP_St)) 1560 ni_handle_eos(dev, s); 1561 1562 cfc_handle_events(dev, s); 1563} 1564 1565static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) 1566{ 1567 unsigned short ack = 0; 1568 1569 if (b_status & AO_BC_TC_St) 1570 ack |= AO_BC_TC_Interrupt_Ack; 1571 if (b_status & AO_Overrun_St) 1572 ack |= AO_Error_Interrupt_Ack; 1573 if (b_status & AO_START_St) 1574 ack |= AO_START_Interrupt_Ack; 1575 if (b_status & AO_START1_St) 1576 ack |= AO_START1_Interrupt_Ack; 1577 if (b_status & AO_UC_TC_St) 1578 ack |= AO_UC_TC_Interrupt_Ack; 1579 if (b_status & AO_UI2_TC_St) 1580 ack |= AO_UI2_TC_Interrupt_Ack; 1581 if (b_status & AO_UPDATE_St) 1582 ack |= AO_UPDATE_Interrupt_Ack; 1583 if (ack) 1584 ni_stc_writew(dev, ack, Interrupt_B_Ack_Register); 1585} 1586 1587static void handle_b_interrupt(struct comedi_device *dev, 1588 unsigned short b_status, unsigned ao_mite_status) 1589{ 1590 struct comedi_subdevice *s = dev->write_subdev; 1591 /* unsigned short ack=0; */ 1592 1593#ifdef PCIDMA 1594 /* Currently, mite.c requires us to handle LINKC */ 1595 if (ao_mite_status & CHSR_LINKC) { 1596 struct ni_private *devpriv = dev->private; 1597 1598 mite_handle_b_linkc(devpriv->mite, dev); 1599 } 1600 1601 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | 1602 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | 1603 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { 1604 dev_err(dev->class_dev, 1605 "unknown mite interrupt (ao_mite_status=%08x)\n", 1606 ao_mite_status); 1607 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 1608 } 1609#endif 1610 1611 if (b_status == 0xffff) 1612 return; 1613 if (b_status & AO_Overrun_St) { 1614 dev_err(dev->class_dev, 1615 "AO FIFO underrun status=0x%04x status2=0x%04x\n", 1616 b_status, ni_stc_readw(dev, AO_Status_2_Register)); 1617 s->async->events |= COMEDI_CB_OVERFLOW; 1618 } 1619 1620 if (b_status & AO_BC_TC_St) 1621 s->async->events |= COMEDI_CB_EOA; 1622 1623#ifndef PCIDMA 1624 if (b_status & AO_FIFO_Request_St) { 1625 int ret; 1626 1627 ret = ni_ao_fifo_half_empty(dev, s); 1628 if (!ret) { 1629 dev_err(dev->class_dev, "AO buffer underrun\n"); 1630 ni_set_bits(dev, Interrupt_B_Enable_Register, 1631 AO_FIFO_Interrupt_Enable | 1632 AO_Error_Interrupt_Enable, 0); 1633 s->async->events |= COMEDI_CB_OVERFLOW; 1634 } 1635 } 1636#endif 1637 1638 cfc_handle_events(dev, s); 1639} 1640 1641static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, 1642 void *data, unsigned int num_bytes, 1643 unsigned int chan_index) 1644{ 1645 struct ni_private *devpriv = dev->private; 1646 struct comedi_async *async = s->async; 1647 struct comedi_cmd *cmd = &async->cmd; 1648 unsigned int length = num_bytes / bytes_per_sample(s); 1649 unsigned short *array = data; 1650 unsigned int *larray = data; 1651 unsigned int i; 1652 1653 for (i = 0; i < length; i++) { 1654#ifdef PCIDMA 1655 if (s->subdev_flags & SDF_LSAMPL) 1656 larray[i] = le32_to_cpu(larray[i]); 1657 else 1658 array[i] = le16_to_cpu(array[i]); 1659#endif 1660 if (s->subdev_flags & SDF_LSAMPL) 1661 larray[i] += devpriv->ai_offset[chan_index]; 1662 else 1663 array[i] += devpriv->ai_offset[chan_index]; 1664 chan_index++; 1665 chan_index %= cmd->chanlist_len; 1666 } 1667} 1668 1669#ifdef PCIDMA 1670 1671static int ni_ai_setup_MITE_dma(struct comedi_device *dev) 1672{ 1673 struct ni_private *devpriv = dev->private; 1674 struct comedi_subdevice *s = dev->read_subdev; 1675 int retval; 1676 unsigned long flags; 1677 1678 retval = ni_request_ai_mite_channel(dev); 1679 if (retval) 1680 return retval; 1681 1682 /* write alloc the entire buffer */ 1683 comedi_buf_write_alloc(s, s->async->prealloc_bufsz); 1684 1685 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1686 if (devpriv->ai_mite_chan == NULL) { 1687 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1688 return -EIO; 1689 } 1690 1691 if (devpriv->is_611x || devpriv->is_6143) 1692 mite_prep_dma(devpriv->ai_mite_chan, 32, 16); 1693 else if (devpriv->is_628x) 1694 mite_prep_dma(devpriv->ai_mite_chan, 32, 32); 1695 else 1696 mite_prep_dma(devpriv->ai_mite_chan, 16, 16); 1697 1698 /*start the MITE */ 1699 mite_dma_arm(devpriv->ai_mite_chan); 1700 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1701 1702 return 0; 1703} 1704 1705static int ni_ao_setup_MITE_dma(struct comedi_device *dev) 1706{ 1707 struct ni_private *devpriv = dev->private; 1708 struct comedi_subdevice *s = dev->write_subdev; 1709 int retval; 1710 unsigned long flags; 1711 1712 retval = ni_request_ao_mite_channel(dev); 1713 if (retval) 1714 return retval; 1715 1716 /* read alloc the entire buffer */ 1717 comedi_buf_read_alloc(s, s->async->prealloc_bufsz); 1718 1719 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1720 if (devpriv->ao_mite_chan) { 1721 if (devpriv->is_611x || devpriv->is_6713) { 1722 mite_prep_dma(devpriv->ao_mite_chan, 32, 32); 1723 } else { 1724 /* doing 32 instead of 16 bit wide transfers from memory 1725 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */ 1726 mite_prep_dma(devpriv->ao_mite_chan, 16, 32); 1727 } 1728 mite_dma_arm(devpriv->ao_mite_chan); 1729 } else 1730 retval = -EIO; 1731 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1732 1733 return retval; 1734} 1735 1736#endif /* PCIDMA */ 1737 1738/* 1739 used for both cancel ioctl and board initialization 1740 1741 this is pretty harsh for a cancel, but it works... 1742 */ 1743 1744static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) 1745{ 1746 struct ni_private *devpriv = dev->private; 1747 1748 ni_release_ai_mite_channel(dev); 1749 /* ai configuration */ 1750 ni_stc_writew(dev, AI_Configuration_Start | AI_Reset, 1751 Joint_Reset_Register); 1752 1753 ni_set_bits(dev, Interrupt_A_Enable_Register, 1754 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable | 1755 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable | 1756 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable | 1757 AI_FIFO_Interrupt_Enable, 0); 1758 1759 ni_clear_ai_fifo(dev); 1760 1761 if (!devpriv->is_6143) 1762 ni_writeb(dev, 0, Misc_Command); 1763 1764 ni_stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */ 1765 ni_stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved 1766 /*| AI_Trigger_Once */, 1767 AI_Mode_1_Register); 1768 ni_stc_writew(dev, 0x0000, AI_Mode_2_Register); 1769 /* generate FIFO interrupts on non-empty */ 1770 ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register); 1771 if (devpriv->is_611x) { 1772 ni_stc_writew(dev, 1773 AI_SHIFTIN_Pulse_Width | 1774 AI_SOC_Polarity | 1775 AI_LOCALMUX_CLK_Pulse_Width, 1776 AI_Personal_Register); 1777 ni_stc_writew(dev, 1778 AI_SCAN_IN_PROG_Output_Select(3) | 1779 AI_EXTMUX_CLK_Output_Select(0) | 1780 AI_LOCALMUX_CLK_Output_Select(2) | 1781 AI_SC_TC_Output_Select(3) | 1782 AI_CONVERT_Output_Select 1783 (AI_CONVERT_Output_Enable_High), 1784 AI_Output_Control_Register); 1785 } else if (devpriv->is_6143) { 1786 ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width | 1787 AI_SOC_Polarity | 1788 AI_LOCALMUX_CLK_Pulse_Width, 1789 AI_Personal_Register); 1790 ni_stc_writew(dev, 1791 AI_SCAN_IN_PROG_Output_Select(3) | 1792 AI_EXTMUX_CLK_Output_Select(0) | 1793 AI_LOCALMUX_CLK_Output_Select(2) | 1794 AI_SC_TC_Output_Select(3) | 1795 AI_CONVERT_Output_Select 1796 (AI_CONVERT_Output_Enable_Low), 1797 AI_Output_Control_Register); 1798 } else { 1799 unsigned ai_output_control_bits; 1800 1801 ni_stc_writew(dev, 1802 AI_SHIFTIN_Pulse_Width | 1803 AI_SOC_Polarity | 1804 AI_CONVERT_Pulse_Width | 1805 AI_LOCALMUX_CLK_Pulse_Width, 1806 AI_Personal_Register); 1807 ai_output_control_bits = 1808 AI_SCAN_IN_PROG_Output_Select(3) | 1809 AI_EXTMUX_CLK_Output_Select(0) | 1810 AI_LOCALMUX_CLK_Output_Select(2) | 1811 AI_SC_TC_Output_Select(3); 1812 if (devpriv->is_622x) 1813 ai_output_control_bits |= 1814 AI_CONVERT_Output_Select 1815 (AI_CONVERT_Output_Enable_High); 1816 else 1817 ai_output_control_bits |= 1818 AI_CONVERT_Output_Select 1819 (AI_CONVERT_Output_Enable_Low); 1820 ni_stc_writew(dev, ai_output_control_bits, 1821 AI_Output_Control_Register); 1822 } 1823 /* the following registers should not be changed, because there 1824 * are no backup registers in devpriv. If you want to change 1825 * any of these, add a backup register and other appropriate code: 1826 * AI_Mode_1_Register 1827 * AI_Mode_3_Register 1828 * AI_Personal_Register 1829 * AI_Output_Control_Register 1830 */ 1831 ni_stc_writew(dev, 1832 AI_SC_TC_Error_Confirm | 1833 AI_START_Interrupt_Ack | 1834 AI_START2_Interrupt_Ack | 1835 AI_START1_Interrupt_Ack | 1836 AI_SC_TC_Interrupt_Ack | 1837 AI_Error_Interrupt_Ack | 1838 AI_STOP_Interrupt_Ack, 1839 Interrupt_A_Ack_Register); /* clear interrupts */ 1840 1841 ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); 1842 1843 return 0; 1844} 1845 1846static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s) 1847{ 1848 unsigned long flags; 1849 int count; 1850 1851 /* lock to avoid race with interrupt handler */ 1852 spin_lock_irqsave(&dev->spinlock, flags); 1853#ifndef PCIDMA 1854 ni_handle_fifo_dregs(dev); 1855#else 1856 ni_sync_ai_dma(dev); 1857#endif 1858 count = comedi_buf_n_bytes_ready(s); 1859 spin_unlock_irqrestore(&dev->spinlock, flags); 1860 1861 return count; 1862} 1863 1864static void ni_prime_channelgain_list(struct comedi_device *dev) 1865{ 1866 int i; 1867 1868 ni_stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register); 1869 for (i = 0; i < NI_TIMEOUT; ++i) { 1870 if (!(ni_stc_readw(dev, AI_Status_1_Register) & 1871 AI_FIFO_Empty_St)) { 1872 ni_stc_writew(dev, 1, ADC_FIFO_Clear); 1873 return; 1874 } 1875 udelay(1); 1876 } 1877 dev_err(dev->class_dev, "timeout loading channel/gain list\n"); 1878} 1879 1880static void ni_m_series_load_channelgain_list(struct comedi_device *dev, 1881 unsigned int n_chan, 1882 unsigned int *list) 1883{ 1884 const struct ni_board_struct *board = dev->board_ptr; 1885 struct ni_private *devpriv = dev->private; 1886 unsigned int chan, range, aref; 1887 unsigned int i; 1888 unsigned int dither; 1889 unsigned range_code; 1890 1891 ni_stc_writew(dev, 1, Configuration_Memory_Clear); 1892 1893 if ((list[0] & CR_ALT_SOURCE)) { 1894 unsigned bypass_bits; 1895 1896 chan = CR_CHAN(list[0]); 1897 range = CR_RANGE(list[0]); 1898 range_code = ni_gainlkup[board->gainlkup][range]; 1899 dither = ((list[0] & CR_ALT_FILTER) != 0); 1900 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit; 1901 bypass_bits |= chan; 1902 bypass_bits |= 1903 (devpriv->ai_calib_source) & 1904 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask | 1905 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | 1906 MSeries_AI_Bypass_Mode_Mux_Mask | 1907 MSeries_AO_Bypass_AO_Cal_Sel_Mask); 1908 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code); 1909 if (dither) 1910 bypass_bits |= MSeries_AI_Bypass_Dither_Bit; 1911 /* don't use 2's complement encoding */ 1912 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit; 1913 ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass); 1914 } else { 1915 ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass); 1916 } 1917 for (i = 0; i < n_chan; i++) { 1918 unsigned config_bits = 0; 1919 1920 chan = CR_CHAN(list[i]); 1921 aref = CR_AREF(list[i]); 1922 range = CR_RANGE(list[i]); 1923 dither = ((list[i] & CR_ALT_FILTER) != 0); 1924 1925 range_code = ni_gainlkup[board->gainlkup][range]; 1926 devpriv->ai_offset[i] = 0; 1927 switch (aref) { 1928 case AREF_DIFF: 1929 config_bits |= 1930 MSeries_AI_Config_Channel_Type_Differential_Bits; 1931 break; 1932 case AREF_COMMON: 1933 config_bits |= 1934 MSeries_AI_Config_Channel_Type_Common_Ref_Bits; 1935 break; 1936 case AREF_GROUND: 1937 config_bits |= 1938 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits; 1939 break; 1940 case AREF_OTHER: 1941 break; 1942 } 1943 config_bits |= MSeries_AI_Config_Channel_Bits(chan); 1944 config_bits |= 1945 MSeries_AI_Config_Bank_Bits(board->reg_type, chan); 1946 config_bits |= MSeries_AI_Config_Gain_Bits(range_code); 1947 if (i == n_chan - 1) 1948 config_bits |= MSeries_AI_Config_Last_Channel_Bit; 1949 if (dither) 1950 config_bits |= MSeries_AI_Config_Dither_Bit; 1951 /* don't use 2's complement encoding */ 1952 config_bits |= MSeries_AI_Config_Polarity_Bit; 1953 ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data); 1954 } 1955 ni_prime_channelgain_list(dev); 1956} 1957 1958/* 1959 * Notes on the 6110 and 6111: 1960 * These boards a slightly different than the rest of the series, since 1961 * they have multiple A/D converters. 1962 * From the driver side, the configuration memory is a 1963 * little different. 1964 * Configuration Memory Low: 1965 * bits 15-9: same 1966 * bit 8: unipolar/bipolar (should be 0 for bipolar) 1967 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards 1968 * 1001 gain=0.1 (+/- 50) 1969 * 1010 0.2 1970 * 1011 0.1 1971 * 0001 1 1972 * 0010 2 1973 * 0011 5 1974 * 0100 10 1975 * 0101 20 1976 * 0110 50 1977 * Configuration Memory High: 1978 * bits 12-14: Channel Type 1979 * 001 for differential 1980 * 000 for calibration 1981 * bit 11: coupling (this is not currently handled) 1982 * 1 AC coupling 1983 * 0 DC coupling 1984 * bits 0-2: channel 1985 * valid channels are 0-3 1986 */ 1987static void ni_load_channelgain_list(struct comedi_device *dev, 1988 struct comedi_subdevice *s, 1989 unsigned int n_chan, unsigned int *list) 1990{ 1991 const struct ni_board_struct *board = dev->board_ptr; 1992 struct ni_private *devpriv = dev->private; 1993 unsigned int offset = (s->maxdata + 1) >> 1; 1994 unsigned int chan, range, aref; 1995 unsigned int i; 1996 unsigned int hi, lo; 1997 unsigned int dither; 1998 1999 if (devpriv->is_m_series) { 2000 ni_m_series_load_channelgain_list(dev, n_chan, list); 2001 return; 2002 } 2003 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { 2004 if (devpriv->changain_state 2005 && devpriv->changain_spec == list[0]) { 2006 /* ready to go. */ 2007 return; 2008 } 2009 devpriv->changain_state = 1; 2010 devpriv->changain_spec = list[0]; 2011 } else { 2012 devpriv->changain_state = 0; 2013 } 2014 2015 ni_stc_writew(dev, 1, Configuration_Memory_Clear); 2016 2017 /* Set up Calibration mode if required */ 2018 if (devpriv->is_6143) { 2019 if ((list[0] & CR_ALT_SOURCE) 2020 && !devpriv->ai_calib_source_enabled) { 2021 /* Strobe Relay enable bit */ 2022 ni_writew(dev, devpriv->ai_calib_source | 2023 Calibration_Channel_6143_RelayOn, 2024 Calibration_Channel_6143); 2025 ni_writew(dev, devpriv->ai_calib_source, 2026 Calibration_Channel_6143); 2027 devpriv->ai_calib_source_enabled = 1; 2028 msleep_interruptible(100); /* Allow relays to change */ 2029 } else if (!(list[0] & CR_ALT_SOURCE) 2030 && devpriv->ai_calib_source_enabled) { 2031 /* Strobe Relay disable bit */ 2032 ni_writew(dev, devpriv->ai_calib_source | 2033 Calibration_Channel_6143_RelayOff, 2034 Calibration_Channel_6143); 2035 ni_writew(dev, devpriv->ai_calib_source, 2036 Calibration_Channel_6143); 2037 devpriv->ai_calib_source_enabled = 0; 2038 msleep_interruptible(100); /* Allow relays to change */ 2039 } 2040 } 2041 2042 for (i = 0; i < n_chan; i++) { 2043 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE)) 2044 chan = devpriv->ai_calib_source; 2045 else 2046 chan = CR_CHAN(list[i]); 2047 aref = CR_AREF(list[i]); 2048 range = CR_RANGE(list[i]); 2049 dither = ((list[i] & CR_ALT_FILTER) != 0); 2050 2051 /* fix the external/internal range differences */ 2052 range = ni_gainlkup[board->gainlkup][range]; 2053 if (devpriv->is_611x) 2054 devpriv->ai_offset[i] = offset; 2055 else 2056 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; 2057 2058 hi = 0; 2059 if ((list[i] & CR_ALT_SOURCE)) { 2060 if (devpriv->is_611x) 2061 ni_writew(dev, CR_CHAN(list[i]) & 0x0003, 2062 Calibration_Channel_Select_611x); 2063 } else { 2064 if (devpriv->is_611x) 2065 aref = AREF_DIFF; 2066 else if (devpriv->is_6143) 2067 aref = AREF_OTHER; 2068 switch (aref) { 2069 case AREF_DIFF: 2070 hi |= AI_DIFFERENTIAL; 2071 break; 2072 case AREF_COMMON: 2073 hi |= AI_COMMON; 2074 break; 2075 case AREF_GROUND: 2076 hi |= AI_GROUND; 2077 break; 2078 case AREF_OTHER: 2079 break; 2080 } 2081 } 2082 hi |= AI_CONFIG_CHANNEL(chan); 2083 2084 ni_writew(dev, hi, Configuration_Memory_High); 2085 2086 if (!devpriv->is_6143) { 2087 lo = range; 2088 if (i == n_chan - 1) 2089 lo |= AI_LAST_CHANNEL; 2090 if (dither) 2091 lo |= AI_DITHER; 2092 2093 ni_writew(dev, lo, Configuration_Memory_Low); 2094 } 2095 } 2096 2097 /* prime the channel/gain list */ 2098 if (!devpriv->is_611x && !devpriv->is_6143) 2099 ni_prime_channelgain_list(dev); 2100} 2101 2102static int ni_ai_insn_read(struct comedi_device *dev, 2103 struct comedi_subdevice *s, 2104 struct comedi_insn *insn, 2105 unsigned int *data) 2106{ 2107 struct ni_private *devpriv = dev->private; 2108 unsigned int mask = (s->maxdata + 1) >> 1; 2109 int i, n; 2110 unsigned signbits; 2111 unsigned int d; 2112 unsigned long dl; 2113 2114 ni_load_channelgain_list(dev, s, 1, &insn->chanspec); 2115 2116 ni_clear_ai_fifo(dev); 2117 2118 signbits = devpriv->ai_offset[0]; 2119 if (devpriv->is_611x) { 2120 for (n = 0; n < num_adc_stages_611x; n++) { 2121 ni_stc_writew(dev, AI_CONVERT_Pulse, 2122 AI_Command_1_Register); 2123 udelay(1); 2124 } 2125 for (n = 0; n < insn->n; n++) { 2126 ni_stc_writew(dev, AI_CONVERT_Pulse, 2127 AI_Command_1_Register); 2128 /* The 611x has screwy 32-bit FIFOs. */ 2129 d = 0; 2130 for (i = 0; i < NI_TIMEOUT; i++) { 2131 if (ni_readb(dev, XXX_Status) & 0x80) { 2132 d = ni_readl(dev, ADC_FIFO_Data_611x); 2133 d >>= 16; 2134 d &= 0xffff; 2135 break; 2136 } 2137 if (!(ni_stc_readw(dev, AI_Status_1_Register) & 2138 AI_FIFO_Empty_St)) { 2139 d = ni_readl(dev, ADC_FIFO_Data_611x); 2140 d &= 0xffff; 2141 break; 2142 } 2143 } 2144 if (i == NI_TIMEOUT) { 2145 dev_err(dev->class_dev, "%s timeout\n", 2146 __func__); 2147 return -ETIME; 2148 } 2149 d += signbits; 2150 data[n] = d; 2151 } 2152 } else if (devpriv->is_6143) { 2153 for (n = 0; n < insn->n; n++) { 2154 ni_stc_writew(dev, AI_CONVERT_Pulse, 2155 AI_Command_1_Register); 2156 2157 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ 2158 dl = 0; 2159 for (i = 0; i < NI_TIMEOUT; i++) { 2160 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { 2161 /* Get stranded sample into FIFO */ 2162 ni_writel(dev, 0x01, 2163 AIFIFO_Control_6143); 2164 dl = ni_readl(dev, AIFIFO_Data_6143); 2165 break; 2166 } 2167 } 2168 if (i == NI_TIMEOUT) { 2169 dev_err(dev->class_dev, "%s timeout\n", 2170 __func__); 2171 return -ETIME; 2172 } 2173 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF; 2174 } 2175 } else { 2176 for (n = 0; n < insn->n; n++) { 2177 ni_stc_writew(dev, AI_CONVERT_Pulse, 2178 AI_Command_1_Register); 2179 for (i = 0; i < NI_TIMEOUT; i++) { 2180 if (!(ni_stc_readw(dev, AI_Status_1_Register) & 2181 AI_FIFO_Empty_St)) 2182 break; 2183 } 2184 if (i == NI_TIMEOUT) { 2185 dev_err(dev->class_dev, "%s timeout\n", 2186 __func__); 2187 return -ETIME; 2188 } 2189 if (devpriv->is_m_series) { 2190 dl = ni_readl(dev, M_Offset_AI_FIFO_Data); 2191 dl &= mask; 2192 data[n] = dl; 2193 } else { 2194 d = ni_readw(dev, ADC_FIFO_Data_Register); 2195 d += signbits; /* subtle: needs to be short addition */ 2196 data[n] = d; 2197 } 2198 } 2199 } 2200 return insn->n; 2201} 2202 2203static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, 2204 unsigned int flags) 2205{ 2206 struct ni_private *devpriv = dev->private; 2207 int divider; 2208 2209 switch (flags & CMDF_ROUND_MASK) { 2210 case CMDF_ROUND_NEAREST: 2211 default: 2212 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns; 2213 break; 2214 case CMDF_ROUND_DOWN: 2215 divider = (nanosec) / devpriv->clock_ns; 2216 break; 2217 case CMDF_ROUND_UP: 2218 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns; 2219 break; 2220 } 2221 return divider - 1; 2222} 2223 2224static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer) 2225{ 2226 struct ni_private *devpriv = dev->private; 2227 2228 return devpriv->clock_ns * (timer + 1); 2229} 2230 2231static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev, 2232 unsigned num_channels) 2233{ 2234 const struct ni_board_struct *board = dev->board_ptr; 2235 struct ni_private *devpriv = dev->private; 2236 2237 /* simultaneously-sampled inputs */ 2238 if (devpriv->is_611x || devpriv->is_6143) 2239 return board->ai_speed; 2240 2241 /* multiplexed inputs */ 2242 return board->ai_speed * num_channels; 2243} 2244 2245static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 2246 struct comedi_cmd *cmd) 2247{ 2248 const struct ni_board_struct *board = dev->board_ptr; 2249 struct ni_private *devpriv = dev->private; 2250 int err = 0; 2251 unsigned int tmp; 2252 unsigned int sources; 2253 2254 /* Step 1 : check if triggers are trivially valid */ 2255 2256 if ((cmd->flags & CMDF_WRITE)) 2257 cmd->flags &= ~CMDF_WRITE; 2258 2259 err |= cfc_check_trigger_src(&cmd->start_src, 2260 TRIG_NOW | TRIG_INT | TRIG_EXT); 2261 err |= cfc_check_trigger_src(&cmd->scan_begin_src, 2262 TRIG_TIMER | TRIG_EXT); 2263 2264 sources = TRIG_TIMER | TRIG_EXT; 2265 if (devpriv->is_611x || devpriv->is_6143) 2266 sources |= TRIG_NOW; 2267 err |= cfc_check_trigger_src(&cmd->convert_src, sources); 2268 2269 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 2270 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); 2271 2272 if (err) 2273 return 1; 2274 2275 /* Step 2a : make sure trigger sources are unique */ 2276 2277 err |= cfc_check_trigger_is_unique(cmd->start_src); 2278 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); 2279 err |= cfc_check_trigger_is_unique(cmd->convert_src); 2280 err |= cfc_check_trigger_is_unique(cmd->stop_src); 2281 2282 /* Step 2b : and mutually compatible */ 2283 2284 if (err) 2285 return 2; 2286 2287 /* Step 3: check if arguments are trivially valid */ 2288 2289 switch (cmd->start_src) { 2290 case TRIG_NOW: 2291 case TRIG_INT: 2292 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 2293 break; 2294 case TRIG_EXT: 2295 tmp = CR_CHAN(cmd->start_arg); 2296 2297 if (tmp > 16) 2298 tmp = 16; 2299 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); 2300 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp); 2301 break; 2302 } 2303 2304 if (cmd->scan_begin_src == TRIG_TIMER) { 2305 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 2306 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len)); 2307 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 2308 devpriv->clock_ns * 0xffffff); 2309 } else if (cmd->scan_begin_src == TRIG_EXT) { 2310 /* external trigger */ 2311 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg); 2312 2313 if (tmp > 16) 2314 tmp = 16; 2315 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE)); 2316 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp); 2317 } else { /* TRIG_OTHER */ 2318 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0); 2319 } 2320 2321 if (cmd->convert_src == TRIG_TIMER) { 2322 if (devpriv->is_611x || devpriv->is_6143) { 2323 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); 2324 } else { 2325 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 2326 board->ai_speed); 2327 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 2328 devpriv->clock_ns * 0xffff); 2329 } 2330 } else if (cmd->convert_src == TRIG_EXT) { 2331 /* external trigger */ 2332 unsigned int tmp = CR_CHAN(cmd->convert_arg); 2333 2334 if (tmp > 16) 2335 tmp = 16; 2336 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT)); 2337 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp); 2338 } else if (cmd->convert_src == TRIG_NOW) { 2339 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); 2340 } 2341 2342 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 2343 2344 if (cmd->stop_src == TRIG_COUNT) { 2345 unsigned int max_count = 0x01000000; 2346 2347 if (devpriv->is_611x) 2348 max_count -= num_adc_stages_611x; 2349 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count); 2350 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); 2351 } else { 2352 /* TRIG_NONE */ 2353 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 2354 } 2355 2356 if (err) 2357 return 3; 2358 2359 /* step 4: fix up any arguments */ 2360 2361 if (cmd->scan_begin_src == TRIG_TIMER) { 2362 tmp = cmd->scan_begin_arg; 2363 cmd->scan_begin_arg = 2364 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 2365 cmd->scan_begin_arg, 2366 cmd->flags)); 2367 if (tmp != cmd->scan_begin_arg) 2368 err++; 2369 } 2370 if (cmd->convert_src == TRIG_TIMER) { 2371 if (!devpriv->is_611x && !devpriv->is_6143) { 2372 tmp = cmd->convert_arg; 2373 cmd->convert_arg = 2374 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 2375 cmd->convert_arg, 2376 cmd->flags)); 2377 if (tmp != cmd->convert_arg) 2378 err++; 2379 if (cmd->scan_begin_src == TRIG_TIMER && 2380 cmd->scan_begin_arg < 2381 cmd->convert_arg * cmd->scan_end_arg) { 2382 cmd->scan_begin_arg = 2383 cmd->convert_arg * cmd->scan_end_arg; 2384 err++; 2385 } 2386 } 2387 } 2388 2389 if (err) 2390 return 4; 2391 2392 return 0; 2393} 2394 2395static int ni_ai_inttrig(struct comedi_device *dev, 2396 struct comedi_subdevice *s, 2397 unsigned int trig_num) 2398{ 2399 struct ni_private *devpriv = dev->private; 2400 struct comedi_cmd *cmd = &s->async->cmd; 2401 2402 if (trig_num != cmd->start_arg) 2403 return -EINVAL; 2404 2405 ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, 2406 AI_Command_2_Register); 2407 s->async->inttrig = NULL; 2408 2409 return 1; 2410} 2411 2412static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 2413{ 2414 struct ni_private *devpriv = dev->private; 2415 const struct comedi_cmd *cmd = &s->async->cmd; 2416 int timer; 2417 int mode1 = 0; /* mode1 is needed for both stop and convert */ 2418 int mode2 = 0; 2419 int start_stop_select = 0; 2420 unsigned int stop_count; 2421 int interrupt_a_enable = 0; 2422 2423 if (dev->irq == 0) { 2424 dev_err(dev->class_dev, "cannot run command without an irq\n"); 2425 return -EIO; 2426 } 2427 ni_clear_ai_fifo(dev); 2428 2429 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist); 2430 2431 /* start configuration */ 2432 ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register); 2433 2434 /* disable analog triggering for now, since it 2435 * interferes with the use of pfi0 */ 2436 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable; 2437 ni_stc_writew(dev, devpriv->an_trig_etc_reg, 2438 Analog_Trigger_Etc_Register); 2439 2440 switch (cmd->start_src) { 2441 case TRIG_INT: 2442 case TRIG_NOW: 2443 ni_stc_writew(dev, 2444 AI_START2_Select(0) | 2445 AI_START1_Sync | AI_START1_Edge | 2446 AI_START1_Select(0), 2447 AI_Trigger_Select_Register); 2448 break; 2449 case TRIG_EXT: 2450 { 2451 int chan = CR_CHAN(cmd->start_arg); 2452 unsigned int bits = AI_START2_Select(0) | 2453 AI_START1_Sync | AI_START1_Select(chan + 1); 2454 2455 if (cmd->start_arg & CR_INVERT) 2456 bits |= AI_START1_Polarity; 2457 if (cmd->start_arg & CR_EDGE) 2458 bits |= AI_START1_Edge; 2459 ni_stc_writew(dev, bits, AI_Trigger_Select_Register); 2460 break; 2461 } 2462 } 2463 2464 mode2 &= ~AI_Pre_Trigger; 2465 mode2 &= ~AI_SC_Initial_Load_Source; 2466 mode2 &= ~AI_SC_Reload_Mode; 2467 ni_stc_writew(dev, mode2, AI_Mode_2_Register); 2468 2469 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) { 2470 start_stop_select |= AI_STOP_Polarity; 2471 start_stop_select |= AI_STOP_Select(31); /* logic low */ 2472 start_stop_select |= AI_STOP_Sync; 2473 } else { 2474 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */ 2475 } 2476 ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register); 2477 2478 devpriv->ai_cmd2 = 0; 2479 switch (cmd->stop_src) { 2480 case TRIG_COUNT: 2481 stop_count = cmd->stop_arg - 1; 2482 2483 if (devpriv->is_611x) { 2484 /* have to take 3 stage adc pipeline into account */ 2485 stop_count += num_adc_stages_611x; 2486 } 2487 /* stage number of scans */ 2488 ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers); 2489 2490 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once; 2491 ni_stc_writew(dev, mode1, AI_Mode_1_Register); 2492 /* load SC (Scan Count) */ 2493 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register); 2494 2495 if (stop_count == 0) { 2496 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan; 2497 interrupt_a_enable |= AI_STOP_Interrupt_Enable; 2498 /* this is required to get the last sample for chanlist_len > 1, not sure why */ 2499 if (cmd->chanlist_len > 1) 2500 start_stop_select |= 2501 AI_STOP_Polarity | AI_STOP_Edge; 2502 } 2503 break; 2504 case TRIG_NONE: 2505 /* stage number of scans */ 2506 ni_stc_writel(dev, 0, AI_SC_Load_A_Registers); 2507 2508 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous; 2509 ni_stc_writew(dev, mode1, AI_Mode_1_Register); 2510 2511 /* load SC (Scan Count) */ 2512 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register); 2513 break; 2514 } 2515 2516 switch (cmd->scan_begin_src) { 2517 case TRIG_TIMER: 2518 /* 2519 stop bits for non 611x boards 2520 AI_SI_Special_Trigger_Delay=0 2521 AI_Pre_Trigger=0 2522 AI_START_STOP_Select_Register: 2523 AI_START_Polarity=0 (?) rising edge 2524 AI_START_Edge=1 edge triggered 2525 AI_START_Sync=1 (?) 2526 AI_START_Select=0 SI_TC 2527 AI_STOP_Polarity=0 rising edge 2528 AI_STOP_Edge=0 level 2529 AI_STOP_Sync=1 2530 AI_STOP_Select=19 external pin (configuration mem) 2531 */ 2532 start_stop_select |= AI_START_Edge | AI_START_Sync; 2533 ni_stc_writew(dev, start_stop_select, 2534 AI_START_STOP_Select_Register); 2535 2536 mode2 |= AI_SI_Reload_Mode(0); 2537 /* AI_SI_Initial_Load_Source=A */ 2538 mode2 &= ~AI_SI_Initial_Load_Source; 2539 /* mode2 |= AI_SC_Reload_Mode; */ 2540 ni_stc_writew(dev, mode2, AI_Mode_2_Register); 2541 2542 /* load SI */ 2543 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, 2544 CMDF_ROUND_NEAREST); 2545 ni_stc_writel(dev, timer, AI_SI_Load_A_Registers); 2546 ni_stc_writew(dev, AI_SI_Load, AI_Command_1_Register); 2547 break; 2548 case TRIG_EXT: 2549 if (cmd->scan_begin_arg & CR_EDGE) 2550 start_stop_select |= AI_START_Edge; 2551 /* AI_START_Polarity==1 is falling edge */ 2552 if (cmd->scan_begin_arg & CR_INVERT) 2553 start_stop_select |= AI_START_Polarity; 2554 if (cmd->scan_begin_src != cmd->convert_src || 2555 (cmd->scan_begin_arg & ~CR_EDGE) != 2556 (cmd->convert_arg & ~CR_EDGE)) 2557 start_stop_select |= AI_START_Sync; 2558 start_stop_select |= 2559 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg)); 2560 ni_stc_writew(dev, start_stop_select, 2561 AI_START_STOP_Select_Register); 2562 break; 2563 } 2564 2565 switch (cmd->convert_src) { 2566 case TRIG_TIMER: 2567 case TRIG_NOW: 2568 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW) 2569 timer = 1; 2570 else 2571 timer = ni_ns_to_timer(dev, cmd->convert_arg, 2572 CMDF_ROUND_NEAREST); 2573 /* 0,0 does not work */ 2574 ni_stc_writew(dev, 1, AI_SI2_Load_A_Register); 2575 ni_stc_writew(dev, timer, AI_SI2_Load_B_Register); 2576 2577 /* AI_SI2_Reload_Mode = alternate */ 2578 /* AI_SI2_Initial_Load_Source = A */ 2579 mode2 &= ~AI_SI2_Initial_Load_Source; 2580 mode2 |= AI_SI2_Reload_Mode; 2581 ni_stc_writew(dev, mode2, AI_Mode_2_Register); 2582 2583 /* AI_SI2_Load */ 2584 ni_stc_writew(dev, AI_SI2_Load, AI_Command_1_Register); 2585 2586 mode2 |= AI_SI2_Reload_Mode; /* alternate */ 2587 mode2 |= AI_SI2_Initial_Load_Source; /* B */ 2588 2589 ni_stc_writew(dev, mode2, AI_Mode_2_Register); 2590 break; 2591 case TRIG_EXT: 2592 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg); 2593 if ((cmd->convert_arg & CR_INVERT) == 0) 2594 mode1 |= AI_CONVERT_Source_Polarity; 2595 ni_stc_writew(dev, mode1, AI_Mode_1_Register); 2596 2597 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable; 2598 ni_stc_writew(dev, mode2, AI_Mode_2_Register); 2599 2600 break; 2601 } 2602 2603 if (dev->irq) { 2604 2605 /* interrupt on FIFO, errors, SC_TC */ 2606 interrupt_a_enable |= AI_Error_Interrupt_Enable | 2607 AI_SC_TC_Interrupt_Enable; 2608 2609#ifndef PCIDMA 2610 interrupt_a_enable |= AI_FIFO_Interrupt_Enable; 2611#endif 2612 2613 if (cmd->flags & CMDF_WAKE_EOS 2614 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) { 2615 /* wake on end-of-scan */ 2616 devpriv->aimode = AIMODE_SCAN; 2617 } else { 2618 devpriv->aimode = AIMODE_HALF_FULL; 2619 } 2620 2621 switch (devpriv->aimode) { 2622 case AIMODE_HALF_FULL: 2623 /*generate FIFO interrupts and DMA requests on half-full */ 2624#ifdef PCIDMA 2625 ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E, 2626 AI_Mode_3_Register); 2627#else 2628 ni_stc_writew(dev, AI_FIFO_Mode_HF, 2629 AI_Mode_3_Register); 2630#endif 2631 break; 2632 case AIMODE_SAMPLE: 2633 /*generate FIFO interrupts on non-empty */ 2634 ni_stc_writew(dev, AI_FIFO_Mode_NE, 2635 AI_Mode_3_Register); 2636 break; 2637 case AIMODE_SCAN: 2638#ifdef PCIDMA 2639 ni_stc_writew(dev, AI_FIFO_Mode_NE, 2640 AI_Mode_3_Register); 2641#else 2642 ni_stc_writew(dev, AI_FIFO_Mode_HF, 2643 AI_Mode_3_Register); 2644#endif 2645 interrupt_a_enable |= AI_STOP_Interrupt_Enable; 2646 break; 2647 default: 2648 break; 2649 } 2650 2651 /* clear interrupts */ 2652 ni_stc_writew(dev, 2653 AI_Error_Interrupt_Ack | 2654 AI_STOP_Interrupt_Ack | 2655 AI_START_Interrupt_Ack | 2656 AI_START2_Interrupt_Ack | 2657 AI_START1_Interrupt_Ack | 2658 AI_SC_TC_Interrupt_Ack | 2659 AI_SC_TC_Error_Confirm, 2660 Interrupt_A_Ack_Register); 2661 2662 ni_set_bits(dev, Interrupt_A_Enable_Register, 2663 interrupt_a_enable, 1); 2664 } else { 2665 /* interrupt on nothing */ 2666 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0); 2667 2668 /* XXX start polling if necessary */ 2669 } 2670 2671 /* end configuration */ 2672 ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); 2673 2674 switch (cmd->scan_begin_src) { 2675 case TRIG_TIMER: 2676 ni_stc_writew(dev, 2677 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, 2678 AI_Command_1_Register); 2679 break; 2680 case TRIG_EXT: 2681 /* XXX AI_SI_Arm? */ 2682 ni_stc_writew(dev, 2683 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, 2684 AI_Command_1_Register); 2685 break; 2686 } 2687 2688#ifdef PCIDMA 2689 { 2690 int retval = ni_ai_setup_MITE_dma(dev); 2691 2692 if (retval) 2693 return retval; 2694 } 2695#endif 2696 2697 if (cmd->start_src == TRIG_NOW) { 2698 /* AI_START1_Pulse */ 2699 ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, 2700 AI_Command_2_Register); 2701 s->async->inttrig = NULL; 2702 } else if (cmd->start_src == TRIG_EXT) { 2703 s->async->inttrig = NULL; 2704 } else { /* TRIG_INT */ 2705 s->async->inttrig = ni_ai_inttrig; 2706 } 2707 2708 return 0; 2709} 2710 2711static int ni_ai_insn_config(struct comedi_device *dev, 2712 struct comedi_subdevice *s, 2713 struct comedi_insn *insn, unsigned int *data) 2714{ 2715 struct ni_private *devpriv = dev->private; 2716 2717 if (insn->n < 1) 2718 return -EINVAL; 2719 2720 switch (data[0]) { 2721 case INSN_CONFIG_ALT_SOURCE: 2722 if (devpriv->is_m_series) { 2723 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask | 2724 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | 2725 MSeries_AI_Bypass_Mode_Mux_Mask | 2726 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) { 2727 return -EINVAL; 2728 } 2729 devpriv->ai_calib_source = data[1]; 2730 } else if (devpriv->is_6143) { 2731 unsigned int calib_source; 2732 2733 calib_source = data[1] & 0xf; 2734 2735 devpriv->ai_calib_source = calib_source; 2736 ni_writew(dev, calib_source, Calibration_Channel_6143); 2737 } else { 2738 unsigned int calib_source; 2739 unsigned int calib_source_adjust; 2740 2741 calib_source = data[1] & 0xf; 2742 calib_source_adjust = (data[1] >> 4) & 0xff; 2743 2744 if (calib_source >= 8) 2745 return -EINVAL; 2746 devpriv->ai_calib_source = calib_source; 2747 if (devpriv->is_611x) { 2748 ni_writeb(dev, calib_source_adjust, 2749 Cal_Gain_Select_611x); 2750 } 2751 } 2752 return 2; 2753 default: 2754 break; 2755 } 2756 2757 return -EINVAL; 2758} 2759 2760static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s, 2761 void *data, unsigned int num_bytes, 2762 unsigned int chan_index) 2763{ 2764 struct comedi_cmd *cmd = &s->async->cmd; 2765 unsigned int length = num_bytes / bytes_per_sample(s); 2766 unsigned short *array = data; 2767 unsigned int i; 2768 2769 for (i = 0; i < length; i++) { 2770 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]); 2771 unsigned short val = array[i]; 2772 2773 /* 2774 * Munge data from unsigned to two's complement for 2775 * bipolar ranges. 2776 */ 2777 if (comedi_range_is_bipolar(s, range)) 2778 val = comedi_offset_munge(s, val); 2779#ifdef PCIDMA 2780 val = cpu_to_le16(val); 2781#endif 2782 array[i] = val; 2783 2784 chan_index++; 2785 chan_index %= cmd->chanlist_len; 2786 } 2787} 2788 2789static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, 2790 struct comedi_subdevice *s, 2791 unsigned int chanspec[], 2792 unsigned int n_chans, int timed) 2793{ 2794 struct ni_private *devpriv = dev->private; 2795 unsigned int range; 2796 unsigned int chan; 2797 unsigned int conf; 2798 int i; 2799 int invert = 0; 2800 2801 if (timed) { 2802 for (i = 0; i < s->n_chan; ++i) { 2803 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit; 2804 ni_writeb(dev, devpriv->ao_conf[i], 2805 M_Offset_AO_Config_Bank(i)); 2806 ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i)); 2807 } 2808 } 2809 for (i = 0; i < n_chans; i++) { 2810 const struct comedi_krange *krange; 2811 2812 chan = CR_CHAN(chanspec[i]); 2813 range = CR_RANGE(chanspec[i]); 2814 krange = s->range_table->range + range; 2815 invert = 0; 2816 conf = 0; 2817 switch (krange->max - krange->min) { 2818 case 20000000: 2819 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2820 ni_writeb(dev, 0, 2821 M_Offset_AO_Reference_Attenuation(chan)); 2822 break; 2823 case 10000000: 2824 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2825 ni_writeb(dev, 0, 2826 M_Offset_AO_Reference_Attenuation(chan)); 2827 break; 2828 case 4000000: 2829 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2830 ni_writeb(dev, MSeries_Attenuate_x5_Bit, 2831 M_Offset_AO_Reference_Attenuation(chan)); 2832 break; 2833 case 2000000: 2834 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2835 ni_writeb(dev, MSeries_Attenuate_x5_Bit, 2836 M_Offset_AO_Reference_Attenuation(chan)); 2837 break; 2838 default: 2839 dev_err(dev->class_dev, 2840 "%s: bug! unhandled ao reference voltage\n", 2841 __func__); 2842 break; 2843 } 2844 switch (krange->max + krange->min) { 2845 case 0: 2846 conf |= MSeries_AO_DAC_Offset_0V_Bits; 2847 break; 2848 case 10000000: 2849 conf |= MSeries_AO_DAC_Offset_5V_Bits; 2850 break; 2851 default: 2852 dev_err(dev->class_dev, 2853 "%s: bug! unhandled ao offset voltage\n", 2854 __func__); 2855 break; 2856 } 2857 if (timed) 2858 conf |= MSeries_AO_Update_Timed_Bit; 2859 ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan)); 2860 devpriv->ao_conf[chan] = conf; 2861 ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan)); 2862 } 2863 return invert; 2864} 2865 2866static int ni_old_ao_config_chanlist(struct comedi_device *dev, 2867 struct comedi_subdevice *s, 2868 unsigned int chanspec[], 2869 unsigned int n_chans) 2870{ 2871 struct ni_private *devpriv = dev->private; 2872 unsigned int range; 2873 unsigned int chan; 2874 unsigned int conf; 2875 int i; 2876 int invert = 0; 2877 2878 for (i = 0; i < n_chans; i++) { 2879 chan = CR_CHAN(chanspec[i]); 2880 range = CR_RANGE(chanspec[i]); 2881 conf = AO_Channel(chan); 2882 2883 if (comedi_range_is_bipolar(s, range)) { 2884 conf |= AO_Bipolar; 2885 invert = (s->maxdata + 1) >> 1; 2886 } else { 2887 invert = 0; 2888 } 2889 if (comedi_range_is_external(s, range)) 2890 conf |= AO_Ext_Ref; 2891 2892 /* not all boards can deglitch, but this shouldn't hurt */ 2893 if (chanspec[i] & CR_DEGLITCH) 2894 conf |= AO_Deglitch; 2895 2896 /* analog reference */ 2897 /* AREF_OTHER connects AO ground to AI ground, i think */ 2898 conf |= (CR_AREF(chanspec[i]) == 2899 AREF_OTHER) ? AO_Ground_Ref : 0; 2900 2901 ni_writew(dev, conf, AO_Configuration); 2902 devpriv->ao_conf[chan] = conf; 2903 } 2904 return invert; 2905} 2906 2907static int ni_ao_config_chanlist(struct comedi_device *dev, 2908 struct comedi_subdevice *s, 2909 unsigned int chanspec[], unsigned int n_chans, 2910 int timed) 2911{ 2912 struct ni_private *devpriv = dev->private; 2913 2914 if (devpriv->is_m_series) 2915 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, 2916 timed); 2917 else 2918 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans); 2919} 2920 2921static int ni_ao_insn_write(struct comedi_device *dev, 2922 struct comedi_subdevice *s, 2923 struct comedi_insn *insn, 2924 unsigned int *data) 2925{ 2926 struct ni_private *devpriv = dev->private; 2927 unsigned int chan = CR_CHAN(insn->chanspec); 2928 unsigned int range = CR_RANGE(insn->chanspec); 2929 int reg; 2930 int i; 2931 2932 if (devpriv->is_6xxx) { 2933 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x); 2934 2935 reg = DACx_Direct_Data_671x(chan); 2936 } else if (devpriv->is_m_series) { 2937 reg = M_Offset_DAC_Direct_Data(chan); 2938 } else { 2939 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data; 2940 } 2941 2942 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); 2943 2944 for (i = 0; i < insn->n; i++) { 2945 unsigned int val = data[i]; 2946 2947 s->readback[chan] = val; 2948 2949 if (devpriv->is_6xxx) { 2950 /* 2951 * 6xxx boards have bipolar outputs, munge the 2952 * unsigned comedi values to 2's complement 2953 */ 2954 val = comedi_offset_munge(s, val); 2955 2956 ni_ao_win_outw(dev, val, reg); 2957 } else if (devpriv->is_m_series) { 2958 /* 2959 * M-series boards use offset binary values for 2960 * bipolar and uinpolar outputs 2961 */ 2962 ni_writew(dev, val, reg); 2963 } else { 2964 /* 2965 * Non-M series boards need two's complement values 2966 * for bipolar ranges. 2967 */ 2968 if (comedi_range_is_bipolar(s, range)) 2969 val = comedi_offset_munge(s, val); 2970 2971 ni_writew(dev, val, reg); 2972 } 2973 } 2974 2975 return insn->n; 2976} 2977 2978static int ni_ao_insn_config(struct comedi_device *dev, 2979 struct comedi_subdevice *s, 2980 struct comedi_insn *insn, unsigned int *data) 2981{ 2982 const struct ni_board_struct *board = dev->board_ptr; 2983 struct ni_private *devpriv = dev->private; 2984 2985 switch (data[0]) { 2986 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE: 2987 switch (data[1]) { 2988 case COMEDI_OUTPUT: 2989 data[2] = 1 + board->ao_fifo_depth * sizeof(short); 2990 if (devpriv->mite) 2991 data[2] += devpriv->mite->fifo_size; 2992 break; 2993 case COMEDI_INPUT: 2994 data[2] = 0; 2995 break; 2996 default: 2997 return -EINVAL; 2998 } 2999 return 0; 3000 default: 3001 break; 3002 } 3003 3004 return -EINVAL; 3005} 3006 3007static int ni_ao_inttrig(struct comedi_device *dev, 3008 struct comedi_subdevice *s, 3009 unsigned int trig_num) 3010{ 3011 struct ni_private *devpriv = dev->private; 3012 struct comedi_cmd *cmd = &s->async->cmd; 3013 int ret; 3014 int interrupt_b_bits; 3015 int i; 3016 static const int timeout = 1000; 3017 3018 if (trig_num != cmd->start_arg) 3019 return -EINVAL; 3020 3021 /* Null trig at beginning prevent ao start trigger from executing more than 3022 once per command (and doing things like trying to allocate the ao dma channel 3023 multiple times) */ 3024 s->async->inttrig = NULL; 3025 3026 ni_set_bits(dev, Interrupt_B_Enable_Register, 3027 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0); 3028 interrupt_b_bits = AO_Error_Interrupt_Enable; 3029#ifdef PCIDMA 3030 ni_stc_writew(dev, 1, DAC_FIFO_Clear); 3031 if (devpriv->is_6xxx) 3032 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); 3033 ret = ni_ao_setup_MITE_dma(dev); 3034 if (ret) 3035 return ret; 3036 ret = ni_ao_wait_for_dma_load(dev); 3037 if (ret < 0) 3038 return ret; 3039#else 3040 ret = ni_ao_prep_fifo(dev, s); 3041 if (ret == 0) 3042 return -EPIPE; 3043 3044 interrupt_b_bits |= AO_FIFO_Interrupt_Enable; 3045#endif 3046 3047 ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE, 3048 AO_Mode_3_Register); 3049 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3050 /* wait for DACs to be loaded */ 3051 for (i = 0; i < timeout; i++) { 3052 udelay(1); 3053 if ((ni_stc_readw(dev, Joint_Status_2_Register) & 3054 AO_TMRDACWRs_In_Progress_St) == 0) 3055 break; 3056 } 3057 if (i == timeout) { 3058 dev_err(dev->class_dev, 3059 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n"); 3060 return -EIO; 3061 } 3062 /* 3063 * stc manual says we are need to clear error interrupt after 3064 * AO_TMRDACWRs_In_Progress_St clears 3065 */ 3066 ni_stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register); 3067 3068 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1); 3069 3070 ni_stc_writew(dev, devpriv->ao_cmd1 | 3071 AO_UI_Arm | AO_UC_Arm | AO_BC_Arm | 3072 AO_DAC1_Update_Mode | AO_DAC0_Update_Mode, 3073 AO_Command_1_Register); 3074 3075 ni_stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse, 3076 AO_Command_2_Register); 3077 3078 return 0; 3079} 3080 3081static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3082{ 3083 const struct ni_board_struct *board = dev->board_ptr; 3084 struct ni_private *devpriv = dev->private; 3085 const struct comedi_cmd *cmd = &s->async->cmd; 3086 int bits; 3087 int i; 3088 unsigned trigvar; 3089 3090 if (dev->irq == 0) { 3091 dev_err(dev->class_dev, "cannot run command without an irq\n"); 3092 return -EIO; 3093 } 3094 3095 ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); 3096 3097 ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register); 3098 3099 if (devpriv->is_6xxx) { 3100 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x); 3101 3102 bits = 0; 3103 for (i = 0; i < cmd->chanlist_len; i++) { 3104 int chan; 3105 3106 chan = CR_CHAN(cmd->chanlist[i]); 3107 bits |= 1 << chan; 3108 ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x); 3109 } 3110 ni_ao_win_outw(dev, bits, AO_Timed_611x); 3111 } 3112 3113 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); 3114 3115 if (cmd->stop_src == TRIG_NONE) { 3116 devpriv->ao_mode1 |= AO_Continuous; 3117 devpriv->ao_mode1 &= ~AO_Trigger_Once; 3118 } else { 3119 devpriv->ao_mode1 &= ~AO_Continuous; 3120 devpriv->ao_mode1 |= AO_Trigger_Once; 3121 } 3122 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3123 switch (cmd->start_src) { 3124 case TRIG_INT: 3125 case TRIG_NOW: 3126 devpriv->ao_trigger_select &= 3127 ~(AO_START1_Polarity | AO_START1_Select(-1)); 3128 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync; 3129 ni_stc_writew(dev, devpriv->ao_trigger_select, 3130 AO_Trigger_Select_Register); 3131 break; 3132 case TRIG_EXT: 3133 devpriv->ao_trigger_select = 3134 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1); 3135 if (cmd->start_arg & CR_INVERT) 3136 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ 3137 if (cmd->start_arg & CR_EDGE) 3138 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */ 3139 ni_stc_writew(dev, devpriv->ao_trigger_select, 3140 AO_Trigger_Select_Register); 3141 break; 3142 default: 3143 BUG(); 3144 break; 3145 } 3146 devpriv->ao_mode3 &= ~AO_Trigger_Length; 3147 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3148 3149 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3150 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source; 3151 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3152 if (cmd->stop_src == TRIG_NONE) 3153 ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register); 3154 else 3155 ni_stc_writel(dev, 0, AO_BC_Load_A_Register); 3156 ni_stc_writew(dev, AO_BC_Load, AO_Command_1_Register); 3157 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source; 3158 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3159 switch (cmd->stop_src) { 3160 case TRIG_COUNT: 3161 if (devpriv->is_m_series) { 3162 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */ 3163 ni_stc_writel(dev, cmd->stop_arg - 1, 3164 AO_UC_Load_A_Register); 3165 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3166 } else { 3167 ni_stc_writel(dev, cmd->stop_arg, 3168 AO_UC_Load_A_Register); 3169 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3170 ni_stc_writel(dev, cmd->stop_arg - 1, 3171 AO_UC_Load_A_Register); 3172 } 3173 break; 3174 case TRIG_NONE: 3175 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); 3176 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3177 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); 3178 break; 3179 default: 3180 ni_stc_writel(dev, 0, AO_UC_Load_A_Register); 3181 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3182 ni_stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register); 3183 } 3184 3185 devpriv->ao_mode1 &= 3186 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity | 3187 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity); 3188 switch (cmd->scan_begin_src) { 3189 case TRIG_TIMER: 3190 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable; 3191 trigvar = 3192 ni_ns_to_timer(dev, cmd->scan_begin_arg, 3193 CMDF_ROUND_NEAREST); 3194 ni_stc_writel(dev, 1, AO_UI_Load_A_Register); 3195 ni_stc_writew(dev, AO_UI_Load, AO_Command_1_Register); 3196 ni_stc_writel(dev, trigvar, AO_UI_Load_A_Register); 3197 break; 3198 case TRIG_EXT: 3199 devpriv->ao_mode1 |= 3200 AO_UPDATE_Source_Select(cmd->scan_begin_arg); 3201 if (cmd->scan_begin_arg & CR_INVERT) 3202 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity; 3203 devpriv->ao_cmd2 |= AO_BC_Gate_Enable; 3204 break; 3205 default: 3206 BUG(); 3207 break; 3208 } 3209 ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); 3210 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3211 devpriv->ao_mode2 &= 3212 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source); 3213 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3214 3215 if (cmd->scan_end_arg > 1) { 3216 devpriv->ao_mode1 |= AO_Multiple_Channels; 3217 ni_stc_writew(dev, 3218 AO_Number_Of_Channels(cmd->scan_end_arg - 1) | 3219 AO_UPDATE_Output_Select(AO_Update_Output_High_Z), 3220 AO_Output_Control_Register); 3221 } else { 3222 unsigned bits; 3223 3224 devpriv->ao_mode1 &= ~AO_Multiple_Channels; 3225 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z); 3226 if (devpriv->is_m_series || devpriv->is_6xxx) { 3227 bits |= AO_Number_Of_Channels(0); 3228 } else { 3229 bits |= 3230 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0])); 3231 } 3232 ni_stc_writew(dev, bits, AO_Output_Control_Register); 3233 } 3234 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3235 3236 ni_stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode, 3237 AO_Command_1_Register); 3238 3239 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error; 3240 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3241 3242 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask; 3243#ifdef PCIDMA 3244 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F; 3245#else 3246 devpriv->ao_mode2 |= AO_FIFO_Mode_HF; 3247#endif 3248 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable; 3249 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3250 3251 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width | 3252 AO_TMRDACWR_Pulse_Width; 3253 if (board->ao_fifo_depth) 3254 bits |= AO_FIFO_Enable; 3255 else 3256 bits |= AO_DMA_PIO_Control; 3257#if 0 3258 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281, 3259 verified with bus analyzer. */ 3260 if (devpriv->is_m_series) 3261 bits |= AO_Number_Of_DAC_Packages; 3262#endif 3263 ni_stc_writew(dev, bits, AO_Personal_Register); 3264 /* enable sending of ao dma requests */ 3265 ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register); 3266 3267 ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); 3268 3269 if (cmd->stop_src == TRIG_COUNT) { 3270 ni_stc_writew(dev, AO_BC_TC_Interrupt_Ack, 3271 Interrupt_B_Ack_Register); 3272 ni_set_bits(dev, Interrupt_B_Enable_Register, 3273 AO_BC_TC_Interrupt_Enable, 1); 3274 } 3275 3276 s->async->inttrig = ni_ao_inttrig; 3277 3278 return 0; 3279} 3280 3281static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 3282 struct comedi_cmd *cmd) 3283{ 3284 const struct ni_board_struct *board = dev->board_ptr; 3285 struct ni_private *devpriv = dev->private; 3286 int err = 0; 3287 unsigned int tmp; 3288 3289 /* Step 1 : check if triggers are trivially valid */ 3290 3291 if ((cmd->flags & CMDF_WRITE) == 0) 3292 cmd->flags |= CMDF_WRITE; 3293 3294 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT); 3295 err |= cfc_check_trigger_src(&cmd->scan_begin_src, 3296 TRIG_TIMER | TRIG_EXT); 3297 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW); 3298 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 3299 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); 3300 3301 if (err) 3302 return 1; 3303 3304 /* Step 2a : make sure trigger sources are unique */ 3305 3306 err |= cfc_check_trigger_is_unique(cmd->start_src); 3307 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); 3308 err |= cfc_check_trigger_is_unique(cmd->stop_src); 3309 3310 /* Step 2b : and mutually compatible */ 3311 3312 if (err) 3313 return 2; 3314 3315 /* Step 3: check if arguments are trivially valid */ 3316 3317 switch (cmd->start_src) { 3318 case TRIG_INT: 3319 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 3320 break; 3321 case TRIG_EXT: 3322 tmp = CR_CHAN(cmd->start_arg); 3323 3324 if (tmp > 18) 3325 tmp = 18; 3326 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); 3327 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp); 3328 break; 3329 } 3330 3331 if (cmd->scan_begin_src == TRIG_TIMER) { 3332 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 3333 board->ao_speed); 3334 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 3335 devpriv->clock_ns * 0xffffff); 3336 } 3337 3338 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); 3339 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 3340 3341 if (cmd->stop_src == TRIG_COUNT) 3342 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); 3343 else /* TRIG_NONE */ 3344 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 3345 3346 if (err) 3347 return 3; 3348 3349 /* step 4: fix up any arguments */ 3350 if (cmd->scan_begin_src == TRIG_TIMER) { 3351 tmp = cmd->scan_begin_arg; 3352 cmd->scan_begin_arg = 3353 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 3354 cmd->scan_begin_arg, 3355 cmd->flags)); 3356 if (tmp != cmd->scan_begin_arg) 3357 err++; 3358 } 3359 if (err) 3360 return 4; 3361 3362 return 0; 3363} 3364 3365static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) 3366{ 3367 struct ni_private *devpriv = dev->private; 3368 3369 ni_release_ao_mite_channel(dev); 3370 3371 ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); 3372 ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register); 3373 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0); 3374 ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register); 3375 ni_stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register); 3376 ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width | 3377 AO_TMRDACWR_Pulse_Width, AO_Personal_Register); 3378 ni_stc_writew(dev, 0, AO_Output_Control_Register); 3379 ni_stc_writew(dev, 0, AO_Start_Select_Register); 3380 devpriv->ao_cmd1 = 0; 3381 ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register); 3382 devpriv->ao_cmd2 = 0; 3383 ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); 3384 devpriv->ao_mode1 = 0; 3385 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3386 devpriv->ao_mode2 = 0; 3387 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3388 if (devpriv->is_m_series) 3389 devpriv->ao_mode3 = AO_Last_Gate_Disable; 3390 else 3391 devpriv->ao_mode3 = 0; 3392 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3393 devpriv->ao_trigger_select = 0; 3394 ni_stc_writew(dev, devpriv->ao_trigger_select, 3395 AO_Trigger_Select_Register); 3396 if (devpriv->is_6xxx) { 3397 unsigned immediate_bits = 0; 3398 unsigned i; 3399 3400 for (i = 0; i < s->n_chan; ++i) 3401 immediate_bits |= 1 << i; 3402 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x); 3403 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x); 3404 } 3405 ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); 3406 3407 return 0; 3408} 3409 3410/* digital io */ 3411 3412static int ni_dio_insn_config(struct comedi_device *dev, 3413 struct comedi_subdevice *s, 3414 struct comedi_insn *insn, 3415 unsigned int *data) 3416{ 3417 struct ni_private *devpriv = dev->private; 3418 int ret; 3419 3420 ret = comedi_dio_insn_config(dev, s, insn, data, 0); 3421 if (ret) 3422 return ret; 3423 3424 devpriv->dio_control &= ~DIO_Pins_Dir_Mask; 3425 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits); 3426 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3427 3428 return insn->n; 3429} 3430 3431static int ni_dio_insn_bits(struct comedi_device *dev, 3432 struct comedi_subdevice *s, 3433 struct comedi_insn *insn, 3434 unsigned int *data) 3435{ 3436 struct ni_private *devpriv = dev->private; 3437 3438 /* Make sure we're not using the serial part of the dio */ 3439 if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns) 3440 return -EBUSY; 3441 3442 if (comedi_dio_update_state(s, data)) { 3443 devpriv->dio_output &= ~DIO_Parallel_Data_Mask; 3444 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state); 3445 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); 3446 } 3447 3448 data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register); 3449 3450 return insn->n; 3451} 3452 3453static int ni_m_series_dio_insn_config(struct comedi_device *dev, 3454 struct comedi_subdevice *s, 3455 struct comedi_insn *insn, 3456 unsigned int *data) 3457{ 3458 int ret; 3459 3460 ret = comedi_dio_insn_config(dev, s, insn, data, 0); 3461 if (ret) 3462 return ret; 3463 3464 ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); 3465 3466 return insn->n; 3467} 3468 3469static int ni_m_series_dio_insn_bits(struct comedi_device *dev, 3470 struct comedi_subdevice *s, 3471 struct comedi_insn *insn, 3472 unsigned int *data) 3473{ 3474 if (comedi_dio_update_state(s, data)) 3475 ni_writel(dev, s->state, M_Offset_Static_Digital_Output); 3476 3477 data[1] = ni_readl(dev, M_Offset_Static_Digital_Input); 3478 3479 return insn->n; 3480} 3481 3482static int ni_cdio_check_chanlist(struct comedi_device *dev, 3483 struct comedi_subdevice *s, 3484 struct comedi_cmd *cmd) 3485{ 3486 int i; 3487 3488 for (i = 0; i < cmd->chanlist_len; ++i) { 3489 unsigned int chan = CR_CHAN(cmd->chanlist[i]); 3490 3491 if (chan != i) 3492 return -EINVAL; 3493 } 3494 3495 return 0; 3496} 3497 3498static int ni_cdio_cmdtest(struct comedi_device *dev, 3499 struct comedi_subdevice *s, struct comedi_cmd *cmd) 3500{ 3501 int err = 0; 3502 int tmp; 3503 3504 /* Step 1 : check if triggers are trivially valid */ 3505 3506 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT); 3507 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT); 3508 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW); 3509 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 3510 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE); 3511 3512 if (err) 3513 return 1; 3514 3515 /* Step 2a : make sure trigger sources are unique */ 3516 /* Step 2b : and mutually compatible */ 3517 3518 if (err) 3519 return 2; 3520 3521 /* Step 3: check if arguments are trivially valid */ 3522 3523 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 3524 3525 tmp = cmd->scan_begin_arg; 3526 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT); 3527 if (tmp != cmd->scan_begin_arg) 3528 err |= -EINVAL; 3529 3530 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); 3531 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 3532 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 3533 3534 if (err) 3535 return 3; 3536 3537 /* Step 4: fix up any arguments */ 3538 3539 /* Step 5: check channel list if it exists */ 3540 3541 if (cmd->chanlist && cmd->chanlist_len > 0) 3542 err |= ni_cdio_check_chanlist(dev, s, cmd); 3543 3544 if (err) 3545 return 5; 3546 3547 return 0; 3548} 3549 3550static int ni_cdo_inttrig(struct comedi_device *dev, 3551 struct comedi_subdevice *s, 3552 unsigned int trig_num) 3553{ 3554 struct comedi_cmd *cmd = &s->async->cmd; 3555 const unsigned timeout = 1000; 3556 int retval = 0; 3557 unsigned i; 3558#ifdef PCIDMA 3559 struct ni_private *devpriv = dev->private; 3560 unsigned long flags; 3561#endif 3562 3563 if (trig_num != cmd->start_arg) 3564 return -EINVAL; 3565 3566 s->async->inttrig = NULL; 3567 3568 /* read alloc the entire buffer */ 3569 comedi_buf_read_alloc(s, s->async->prealloc_bufsz); 3570 3571#ifdef PCIDMA 3572 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 3573 if (devpriv->cdo_mite_chan) { 3574 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); 3575 mite_dma_arm(devpriv->cdo_mite_chan); 3576 } else { 3577 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n"); 3578 retval = -EIO; 3579 } 3580 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 3581 if (retval < 0) 3582 return retval; 3583#endif 3584/* 3585* XXX not sure what interrupt C group does 3586* ni_writeb(dev, Interrupt_Group_C_Enable_Bit, 3587* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo 3588*/ 3589 for (i = 0; i < timeout; ++i) { 3590 if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) 3591 break; 3592 udelay(10); 3593 } 3594 if (i == timeout) { 3595 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n"); 3596 s->cancel(dev, s); 3597 return -EIO; 3598 } 3599 ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | 3600 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, 3601 M_Offset_CDIO_Command); 3602 return retval; 3603} 3604 3605static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3606{ 3607 const struct comedi_cmd *cmd = &s->async->cmd; 3608 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; 3609 int retval; 3610 3611 ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command); 3612 switch (cmd->scan_begin_src) { 3613 case TRIG_EXT: 3614 cdo_mode_bits |= 3615 CR_CHAN(cmd->scan_begin_arg) & 3616 CDO_Sample_Source_Select_Mask; 3617 break; 3618 default: 3619 BUG(); 3620 break; 3621 } 3622 if (cmd->scan_begin_arg & CR_INVERT) 3623 cdo_mode_bits |= CDO_Polarity_Bit; 3624 ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode); 3625 if (s->io_bits) { 3626 ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data); 3627 ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command); 3628 ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable); 3629 } else { 3630 dev_err(dev->class_dev, 3631 "attempted to run digital output command with no lines configured as outputs\n"); 3632 return -EIO; 3633 } 3634 retval = ni_request_cdo_mite_channel(dev); 3635 if (retval < 0) 3636 return retval; 3637 3638 s->async->inttrig = ni_cdo_inttrig; 3639 3640 return 0; 3641} 3642 3643static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3644{ 3645 ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | 3646 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | 3647 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, 3648 M_Offset_CDIO_Command); 3649/* 3650* XXX not sure what interrupt C group does ni_writeb(dev, 0, 3651* M_Offset_Interrupt_C_Enable); 3652*/ 3653 ni_writel(dev, 0, M_Offset_CDO_Mask_Enable); 3654 ni_release_cdo_mite_channel(dev); 3655 return 0; 3656} 3657 3658static void handle_cdio_interrupt(struct comedi_device *dev) 3659{ 3660 struct ni_private *devpriv = dev->private; 3661 unsigned cdio_status; 3662 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; 3663#ifdef PCIDMA 3664 unsigned long flags; 3665#endif 3666 3667 if (!devpriv->is_m_series) 3668 return; 3669#ifdef PCIDMA 3670 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 3671 if (devpriv->cdo_mite_chan) { 3672 unsigned cdo_mite_status = 3673 mite_get_status(devpriv->cdo_mite_chan); 3674 if (cdo_mite_status & CHSR_LINKC) { 3675 writel(CHOR_CLRLC, 3676 devpriv->mite->mite_io_addr + 3677 MITE_CHOR(devpriv->cdo_mite_chan->channel)); 3678 } 3679 mite_sync_output_dma(devpriv->cdo_mite_chan, s); 3680 } 3681 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 3682#endif 3683 3684 cdio_status = ni_readl(dev, M_Offset_CDIO_Status); 3685 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) { 3686 /* XXX just guessing this is needed and does something useful */ 3687 ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit, 3688 M_Offset_CDIO_Command); 3689 s->async->events |= COMEDI_CB_OVERFLOW; 3690 } 3691 if (cdio_status & CDO_FIFO_Empty_Bit) { 3692 ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, 3693 M_Offset_CDIO_Command); 3694 /* s->async->events |= COMEDI_CB_EOA; */ 3695 } 3696 cfc_handle_events(dev, s); 3697} 3698 3699static int ni_serial_hw_readwrite8(struct comedi_device *dev, 3700 struct comedi_subdevice *s, 3701 unsigned char data_out, 3702 unsigned char *data_in) 3703{ 3704 struct ni_private *devpriv = dev->private; 3705 unsigned int status1; 3706 int err = 0, count = 20; 3707 3708 devpriv->dio_output &= ~DIO_Serial_Data_Mask; 3709 devpriv->dio_output |= DIO_Serial_Data_Out(data_out); 3710 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); 3711 3712 status1 = ni_stc_readw(dev, Joint_Status_1_Register); 3713 if (status1 & DIO_Serial_IO_In_Progress_St) { 3714 err = -EBUSY; 3715 goto Error; 3716 } 3717 3718 devpriv->dio_control |= DIO_HW_Serial_Start; 3719 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3720 devpriv->dio_control &= ~DIO_HW_Serial_Start; 3721 3722 /* Wait until STC says we're done, but don't loop infinitely. */ 3723 while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) & 3724 DIO_Serial_IO_In_Progress_St) { 3725 /* Delay one bit per loop */ 3726 udelay((devpriv->serial_interval_ns + 999) / 1000); 3727 if (--count < 0) { 3728 dev_err(dev->class_dev, 3729 "%s: SPI serial I/O didn't finish in time!\n", 3730 __func__); 3731 err = -ETIME; 3732 goto Error; 3733 } 3734 } 3735 3736 /* Delay for last bit. This delay is absolutely necessary, because 3737 DIO_Serial_IO_In_Progress_St goes high one bit too early. */ 3738 udelay((devpriv->serial_interval_ns + 999) / 1000); 3739 3740 if (data_in != NULL) 3741 *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register); 3742 3743Error: 3744 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3745 3746 return err; 3747} 3748 3749static int ni_serial_sw_readwrite8(struct comedi_device *dev, 3750 struct comedi_subdevice *s, 3751 unsigned char data_out, 3752 unsigned char *data_in) 3753{ 3754 struct ni_private *devpriv = dev->private; 3755 unsigned char mask, input = 0; 3756 3757 /* Wait for one bit before transfer */ 3758 udelay((devpriv->serial_interval_ns + 999) / 1000); 3759 3760 for (mask = 0x80; mask; mask >>= 1) { 3761 /* Output current bit; note that we cannot touch s->state 3762 because it is a per-subdevice field, and serial is 3763 a separate subdevice from DIO. */ 3764 devpriv->dio_output &= ~DIO_SDOUT; 3765 if (data_out & mask) 3766 devpriv->dio_output |= DIO_SDOUT; 3767 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); 3768 3769 /* Assert SDCLK (active low, inverted), wait for half of 3770 the delay, deassert SDCLK, and wait for the other half. */ 3771 devpriv->dio_control |= DIO_Software_Serial_Control; 3772 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3773 3774 udelay((devpriv->serial_interval_ns + 999) / 2000); 3775 3776 devpriv->dio_control &= ~DIO_Software_Serial_Control; 3777 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3778 3779 udelay((devpriv->serial_interval_ns + 999) / 2000); 3780 3781 /* Input current bit */ 3782 if (ni_stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) 3783 input |= mask; 3784 } 3785 3786 if (data_in) 3787 *data_in = input; 3788 3789 return 0; 3790} 3791 3792static int ni_serial_insn_config(struct comedi_device *dev, 3793 struct comedi_subdevice *s, 3794 struct comedi_insn *insn, 3795 unsigned int *data) 3796{ 3797 struct ni_private *devpriv = dev->private; 3798 int err = insn->n; 3799 unsigned char byte_out, byte_in = 0; 3800 3801 if (insn->n != 2) 3802 return -EINVAL; 3803 3804 switch (data[0]) { 3805 case INSN_CONFIG_SERIAL_CLOCK: 3806 devpriv->serial_hw_mode = 1; 3807 devpriv->dio_control |= DIO_HW_Serial_Enable; 3808 3809 if (data[1] == SERIAL_DISABLED) { 3810 devpriv->serial_hw_mode = 0; 3811 devpriv->dio_control &= ~(DIO_HW_Serial_Enable | 3812 DIO_Software_Serial_Control); 3813 data[1] = SERIAL_DISABLED; 3814 devpriv->serial_interval_ns = data[1]; 3815 } else if (data[1] <= SERIAL_600NS) { 3816 /* Warning: this clock speed is too fast to reliably 3817 control SCXI. */ 3818 devpriv->dio_control &= ~DIO_HW_Serial_Timebase; 3819 devpriv->clock_and_fout |= Slow_Internal_Timebase; 3820 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2; 3821 data[1] = SERIAL_600NS; 3822 devpriv->serial_interval_ns = data[1]; 3823 } else if (data[1] <= SERIAL_1_2US) { 3824 devpriv->dio_control &= ~DIO_HW_Serial_Timebase; 3825 devpriv->clock_and_fout |= Slow_Internal_Timebase | 3826 DIO_Serial_Out_Divide_By_2; 3827 data[1] = SERIAL_1_2US; 3828 devpriv->serial_interval_ns = data[1]; 3829 } else if (data[1] <= SERIAL_10US) { 3830 devpriv->dio_control |= DIO_HW_Serial_Timebase; 3831 devpriv->clock_and_fout |= Slow_Internal_Timebase | 3832 DIO_Serial_Out_Divide_By_2; 3833 /* Note: DIO_Serial_Out_Divide_By_2 only affects 3834 600ns/1.2us. If you turn divide_by_2 off with the 3835 slow clock, you will still get 10us, except then 3836 all your delays are wrong. */ 3837 data[1] = SERIAL_10US; 3838 devpriv->serial_interval_ns = data[1]; 3839 } else { 3840 devpriv->dio_control &= ~(DIO_HW_Serial_Enable | 3841 DIO_Software_Serial_Control); 3842 devpriv->serial_hw_mode = 0; 3843 data[1] = (data[1] / 1000) * 1000; 3844 devpriv->serial_interval_ns = data[1]; 3845 } 3846 3847 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3848 ni_stc_writew(dev, devpriv->clock_and_fout, 3849 Clock_and_FOUT_Register); 3850 return 1; 3851 3852 break; 3853 3854 case INSN_CONFIG_BIDIRECTIONAL_DATA: 3855 3856 if (devpriv->serial_interval_ns == 0) 3857 return -EINVAL; 3858 3859 byte_out = data[1] & 0xFF; 3860 3861 if (devpriv->serial_hw_mode) { 3862 err = ni_serial_hw_readwrite8(dev, s, byte_out, 3863 &byte_in); 3864 } else if (devpriv->serial_interval_ns > 0) { 3865 err = ni_serial_sw_readwrite8(dev, s, byte_out, 3866 &byte_in); 3867 } else { 3868 dev_err(dev->class_dev, "%s: serial disabled!\n", 3869 __func__); 3870 return -EINVAL; 3871 } 3872 if (err < 0) 3873 return err; 3874 data[1] = byte_in & 0xFF; 3875 return insn->n; 3876 3877 break; 3878 default: 3879 return -EINVAL; 3880 } 3881 3882} 3883 3884static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s) 3885{ 3886 int i; 3887 3888 for (i = 0; i < s->n_chan; i++) { 3889 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, 3890 AO_Configuration_2_67xx); 3891 } 3892 ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates); 3893} 3894 3895static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg) 3896{ 3897 unsigned stc_register; 3898 3899 switch (reg) { 3900 case NITIO_G0_AUTO_INC: 3901 stc_register = G_Autoincrement_Register(0); 3902 break; 3903 case NITIO_G1_AUTO_INC: 3904 stc_register = G_Autoincrement_Register(1); 3905 break; 3906 case NITIO_G0_CMD: 3907 stc_register = G_Command_Register(0); 3908 break; 3909 case NITIO_G1_CMD: 3910 stc_register = G_Command_Register(1); 3911 break; 3912 case NITIO_G0_HW_SAVE: 3913 stc_register = G_HW_Save_Register(0); 3914 break; 3915 case NITIO_G1_HW_SAVE: 3916 stc_register = G_HW_Save_Register(1); 3917 break; 3918 case NITIO_G0_SW_SAVE: 3919 stc_register = G_Save_Register(0); 3920 break; 3921 case NITIO_G1_SW_SAVE: 3922 stc_register = G_Save_Register(1); 3923 break; 3924 case NITIO_G0_MODE: 3925 stc_register = G_Mode_Register(0); 3926 break; 3927 case NITIO_G1_MODE: 3928 stc_register = G_Mode_Register(1); 3929 break; 3930 case NITIO_G0_LOADA: 3931 stc_register = G_Load_A_Register(0); 3932 break; 3933 case NITIO_G1_LOADA: 3934 stc_register = G_Load_A_Register(1); 3935 break; 3936 case NITIO_G0_LOADB: 3937 stc_register = G_Load_B_Register(0); 3938 break; 3939 case NITIO_G1_LOADB: 3940 stc_register = G_Load_B_Register(1); 3941 break; 3942 case NITIO_G0_INPUT_SEL: 3943 stc_register = G_Input_Select_Register(0); 3944 break; 3945 case NITIO_G1_INPUT_SEL: 3946 stc_register = G_Input_Select_Register(1); 3947 break; 3948 case NITIO_G01_STATUS: 3949 stc_register = G_Status_Register; 3950 break; 3951 case NITIO_G01_RESET: 3952 stc_register = Joint_Reset_Register; 3953 break; 3954 case NITIO_G01_STATUS1: 3955 stc_register = Joint_Status_1_Register; 3956 break; 3957 case NITIO_G01_STATUS2: 3958 stc_register = Joint_Status_2_Register; 3959 break; 3960 case NITIO_G0_INT_ACK: 3961 stc_register = Interrupt_A_Ack_Register; 3962 break; 3963 case NITIO_G1_INT_ACK: 3964 stc_register = Interrupt_B_Ack_Register; 3965 break; 3966 case NITIO_G0_STATUS: 3967 stc_register = AI_Status_1_Register; 3968 break; 3969 case NITIO_G1_STATUS: 3970 stc_register = AO_Status_1_Register; 3971 break; 3972 case NITIO_G0_INT_ENA: 3973 stc_register = Interrupt_A_Enable_Register; 3974 break; 3975 case NITIO_G1_INT_ENA: 3976 stc_register = Interrupt_B_Enable_Register; 3977 break; 3978 default: 3979 printk("%s: unhandled register 0x%x in switch.\n", 3980 __func__, reg); 3981 BUG(); 3982 return 0; 3983 } 3984 return stc_register; 3985} 3986 3987static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 3988 enum ni_gpct_register reg) 3989{ 3990 struct comedi_device *dev = counter->counter_dev->dev; 3991 unsigned stc_register; 3992 /* bits in the join reset register which are relevant to counters */ 3993 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset; 3994 static const unsigned gpct_interrupt_a_enable_mask = 3995 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable; 3996 static const unsigned gpct_interrupt_b_enable_mask = 3997 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable; 3998 3999 switch (reg) { 4000 /* m-series-only registers */ 4001 case NITIO_G0_CNT_MODE: 4002 ni_writew(dev, bits, M_Offset_G0_Counting_Mode); 4003 break; 4004 case NITIO_G1_CNT_MODE: 4005 ni_writew(dev, bits, M_Offset_G1_Counting_Mode); 4006 break; 4007 case NITIO_G0_GATE2: 4008 ni_writew(dev, bits, M_Offset_G0_Second_Gate); 4009 break; 4010 case NITIO_G1_GATE2: 4011 ni_writew(dev, bits, M_Offset_G1_Second_Gate); 4012 break; 4013 case NITIO_G0_DMA_CFG: 4014 ni_writew(dev, bits, M_Offset_G0_DMA_Config); 4015 break; 4016 case NITIO_G1_DMA_CFG: 4017 ni_writew(dev, bits, M_Offset_G1_DMA_Config); 4018 break; 4019 case NITIO_G0_ABZ: 4020 ni_writew(dev, bits, M_Offset_G0_MSeries_ABZ); 4021 break; 4022 case NITIO_G1_ABZ: 4023 ni_writew(dev, bits, M_Offset_G1_MSeries_ABZ); 4024 break; 4025 4026 /* 32 bit registers */ 4027 case NITIO_G0_LOADA: 4028 case NITIO_G1_LOADA: 4029 case NITIO_G0_LOADB: 4030 case NITIO_G1_LOADB: 4031 stc_register = ni_gpct_to_stc_register(reg); 4032 ni_stc_writel(dev, bits, stc_register); 4033 break; 4034 4035 /* 16 bit registers */ 4036 case NITIO_G0_INT_ENA: 4037 BUG_ON(bits & ~gpct_interrupt_a_enable_mask); 4038 ni_set_bitfield(dev, Interrupt_A_Enable_Register, 4039 gpct_interrupt_a_enable_mask, bits); 4040 break; 4041 case NITIO_G1_INT_ENA: 4042 BUG_ON(bits & ~gpct_interrupt_b_enable_mask); 4043 ni_set_bitfield(dev, Interrupt_B_Enable_Register, 4044 gpct_interrupt_b_enable_mask, bits); 4045 break; 4046 case NITIO_G01_RESET: 4047 BUG_ON(bits & ~gpct_joint_reset_mask); 4048 /* fall-through */ 4049 default: 4050 stc_register = ni_gpct_to_stc_register(reg); 4051 ni_stc_writew(dev, bits, stc_register); 4052 } 4053} 4054 4055static unsigned ni_gpct_read_register(struct ni_gpct *counter, 4056 enum ni_gpct_register reg) 4057{ 4058 struct comedi_device *dev = counter->counter_dev->dev; 4059 unsigned stc_register; 4060 4061 switch (reg) { 4062 /* m-series only registers */ 4063 case NITIO_G0_DMA_STATUS: 4064 return ni_readw(dev, M_Offset_G0_DMA_Status); 4065 case NITIO_G1_DMA_STATUS: 4066 return ni_readw(dev, M_Offset_G1_DMA_Status); 4067 4068 /* 32 bit registers */ 4069 case NITIO_G0_HW_SAVE: 4070 case NITIO_G1_HW_SAVE: 4071 case NITIO_G0_SW_SAVE: 4072 case NITIO_G1_SW_SAVE: 4073 stc_register = ni_gpct_to_stc_register(reg); 4074 return ni_stc_readl(dev, stc_register); 4075 4076 /* 16 bit registers */ 4077 default: 4078 stc_register = ni_gpct_to_stc_register(reg); 4079 return ni_stc_readw(dev, stc_register); 4080 } 4081 return 0; 4082} 4083 4084static int ni_freq_out_insn_read(struct comedi_device *dev, 4085 struct comedi_subdevice *s, 4086 struct comedi_insn *insn, 4087 unsigned int *data) 4088{ 4089 struct ni_private *devpriv = dev->private; 4090 unsigned int val = devpriv->clock_and_fout & FOUT_Divider_mask; 4091 int i; 4092 4093 for (i = 0; i < insn->n; i++) 4094 data[i] = val; 4095 4096 return insn->n; 4097} 4098 4099static int ni_freq_out_insn_write(struct comedi_device *dev, 4100 struct comedi_subdevice *s, 4101 struct comedi_insn *insn, 4102 unsigned int *data) 4103{ 4104 struct ni_private *devpriv = dev->private; 4105 4106 if (insn->n) { 4107 devpriv->clock_and_fout &= ~FOUT_Enable; 4108 ni_stc_writew(dev, devpriv->clock_and_fout, 4109 Clock_and_FOUT_Register); 4110 devpriv->clock_and_fout &= ~FOUT_Divider_mask; 4111 4112 /* use the last data value to set the fout divider */ 4113 devpriv->clock_and_fout |= FOUT_Divider(data[insn->n - 1]); 4114 4115 devpriv->clock_and_fout |= FOUT_Enable; 4116 ni_stc_writew(dev, devpriv->clock_and_fout, 4117 Clock_and_FOUT_Register); 4118 } 4119 return insn->n; 4120} 4121 4122static int ni_freq_out_insn_config(struct comedi_device *dev, 4123 struct comedi_subdevice *s, 4124 struct comedi_insn *insn, 4125 unsigned int *data) 4126{ 4127 struct ni_private *devpriv = dev->private; 4128 4129 switch (data[0]) { 4130 case INSN_CONFIG_SET_CLOCK_SRC: 4131 switch (data[1]) { 4132 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC: 4133 devpriv->clock_and_fout &= ~FOUT_Timebase_Select; 4134 break; 4135 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC: 4136 devpriv->clock_and_fout |= FOUT_Timebase_Select; 4137 break; 4138 default: 4139 return -EINVAL; 4140 } 4141 ni_stc_writew(dev, devpriv->clock_and_fout, 4142 Clock_and_FOUT_Register); 4143 break; 4144 case INSN_CONFIG_GET_CLOCK_SRC: 4145 if (devpriv->clock_and_fout & FOUT_Timebase_Select) { 4146 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC; 4147 data[2] = TIMEBASE_2_NS; 4148 } else { 4149 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC; 4150 data[2] = TIMEBASE_1_NS * 2; 4151 } 4152 break; 4153 default: 4154 return -EINVAL; 4155 } 4156 return insn->n; 4157} 4158 4159static int ni_8255_callback(struct comedi_device *dev, 4160 int dir, int port, int data, unsigned long iobase) 4161{ 4162 if (dir) { 4163 ni_writeb(dev, data, iobase + 2 * port); 4164 return 0; 4165 } 4166 4167 return ni_readb(dev, iobase + 2 * port); 4168} 4169 4170static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data) 4171{ 4172 struct ni_private *devpriv = dev->private; 4173 4174 data[1] = devpriv->pwm_up_count * devpriv->clock_ns; 4175 data[2] = devpriv->pwm_down_count * devpriv->clock_ns; 4176 return 3; 4177} 4178 4179static int ni_m_series_pwm_config(struct comedi_device *dev, 4180 struct comedi_subdevice *s, 4181 struct comedi_insn *insn, 4182 unsigned int *data) 4183{ 4184 struct ni_private *devpriv = dev->private; 4185 unsigned up_count, down_count; 4186 4187 switch (data[0]) { 4188 case INSN_CONFIG_PWM_OUTPUT: 4189 switch (data[1]) { 4190 case CMDF_ROUND_NEAREST: 4191 up_count = 4192 (data[2] + 4193 devpriv->clock_ns / 2) / devpriv->clock_ns; 4194 break; 4195 case CMDF_ROUND_DOWN: 4196 up_count = data[2] / devpriv->clock_ns; 4197 break; 4198 case CMDF_ROUND_UP: 4199 up_count = 4200 (data[2] + devpriv->clock_ns - 4201 1) / devpriv->clock_ns; 4202 break; 4203 default: 4204 return -EINVAL; 4205 } 4206 switch (data[3]) { 4207 case CMDF_ROUND_NEAREST: 4208 down_count = 4209 (data[4] + 4210 devpriv->clock_ns / 2) / devpriv->clock_ns; 4211 break; 4212 case CMDF_ROUND_DOWN: 4213 down_count = data[4] / devpriv->clock_ns; 4214 break; 4215 case CMDF_ROUND_UP: 4216 down_count = 4217 (data[4] + devpriv->clock_ns - 4218 1) / devpriv->clock_ns; 4219 break; 4220 default: 4221 return -EINVAL; 4222 } 4223 if (up_count * devpriv->clock_ns != data[2] || 4224 down_count * devpriv->clock_ns != data[4]) { 4225 data[2] = up_count * devpriv->clock_ns; 4226 data[4] = down_count * devpriv->clock_ns; 4227 return -EAGAIN; 4228 } 4229 ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) | 4230 MSeries_Cal_PWM_Low_Time_Bits(down_count), 4231 M_Offset_Cal_PWM); 4232 devpriv->pwm_up_count = up_count; 4233 devpriv->pwm_down_count = down_count; 4234 return 5; 4235 case INSN_CONFIG_GET_PWM_OUTPUT: 4236 return ni_get_pwm_config(dev, data); 4237 default: 4238 return -EINVAL; 4239 } 4240 return 0; 4241} 4242 4243static int ni_6143_pwm_config(struct comedi_device *dev, 4244 struct comedi_subdevice *s, 4245 struct comedi_insn *insn, 4246 unsigned int *data) 4247{ 4248 struct ni_private *devpriv = dev->private; 4249 unsigned up_count, down_count; 4250 4251 switch (data[0]) { 4252 case INSN_CONFIG_PWM_OUTPUT: 4253 switch (data[1]) { 4254 case CMDF_ROUND_NEAREST: 4255 up_count = 4256 (data[2] + 4257 devpriv->clock_ns / 2) / devpriv->clock_ns; 4258 break; 4259 case CMDF_ROUND_DOWN: 4260 up_count = data[2] / devpriv->clock_ns; 4261 break; 4262 case CMDF_ROUND_UP: 4263 up_count = 4264 (data[2] + devpriv->clock_ns - 4265 1) / devpriv->clock_ns; 4266 break; 4267 default: 4268 return -EINVAL; 4269 } 4270 switch (data[3]) { 4271 case CMDF_ROUND_NEAREST: 4272 down_count = 4273 (data[4] + 4274 devpriv->clock_ns / 2) / devpriv->clock_ns; 4275 break; 4276 case CMDF_ROUND_DOWN: 4277 down_count = data[4] / devpriv->clock_ns; 4278 break; 4279 case CMDF_ROUND_UP: 4280 down_count = 4281 (data[4] + devpriv->clock_ns - 4282 1) / devpriv->clock_ns; 4283 break; 4284 default: 4285 return -EINVAL; 4286 } 4287 if (up_count * devpriv->clock_ns != data[2] || 4288 down_count * devpriv->clock_ns != data[4]) { 4289 data[2] = up_count * devpriv->clock_ns; 4290 data[4] = down_count * devpriv->clock_ns; 4291 return -EAGAIN; 4292 } 4293 ni_writel(dev, up_count, Calibration_HighTime_6143); 4294 devpriv->pwm_up_count = up_count; 4295 ni_writel(dev, down_count, Calibration_LowTime_6143); 4296 devpriv->pwm_down_count = down_count; 4297 return 5; 4298 case INSN_CONFIG_GET_PWM_OUTPUT: 4299 return ni_get_pwm_config(dev, data); 4300 default: 4301 return -EINVAL; 4302 } 4303 return 0; 4304} 4305 4306static int pack_mb88341(int addr, int val, int *bitstring) 4307{ 4308 /* 4309 Fujitsu MB 88341 4310 Note that address bits are reversed. Thanks to 4311 Ingo Keen for noticing this. 4312 4313 Note also that the 88341 expects address values from 4314 1-12, whereas we use channel numbers 0-11. The NI 4315 docs use 1-12, also, so be careful here. 4316 */ 4317 addr++; 4318 *bitstring = ((addr & 0x1) << 11) | 4319 ((addr & 0x2) << 9) | 4320 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff); 4321 return 12; 4322} 4323 4324static int pack_dac8800(int addr, int val, int *bitstring) 4325{ 4326 *bitstring = ((addr & 0x7) << 8) | (val & 0xff); 4327 return 11; 4328} 4329 4330static int pack_dac8043(int addr, int val, int *bitstring) 4331{ 4332 *bitstring = val & 0xfff; 4333 return 12; 4334} 4335 4336static int pack_ad8522(int addr, int val, int *bitstring) 4337{ 4338 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000); 4339 return 16; 4340} 4341 4342static int pack_ad8804(int addr, int val, int *bitstring) 4343{ 4344 *bitstring = ((addr & 0xf) << 8) | (val & 0xff); 4345 return 12; 4346} 4347 4348static int pack_ad8842(int addr, int val, int *bitstring) 4349{ 4350 *bitstring = ((addr + 1) << 8) | (val & 0xff); 4351 return 12; 4352} 4353 4354struct caldac_struct { 4355 int n_chans; 4356 int n_bits; 4357 int (*packbits)(int, int, int *); 4358}; 4359 4360static struct caldac_struct caldacs[] = { 4361 [mb88341] = {12, 8, pack_mb88341}, 4362 [dac8800] = {8, 8, pack_dac8800}, 4363 [dac8043] = {1, 12, pack_dac8043}, 4364 [ad8522] = {2, 12, pack_ad8522}, 4365 [ad8804] = {12, 8, pack_ad8804}, 4366 [ad8842] = {8, 8, pack_ad8842}, 4367 [ad8804_debug] = {16, 8, pack_ad8804}, 4368}; 4369 4370static void ni_write_caldac(struct comedi_device *dev, int addr, int val) 4371{ 4372 const struct ni_board_struct *board = dev->board_ptr; 4373 struct ni_private *devpriv = dev->private; 4374 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0; 4375 int i; 4376 int type; 4377 4378 if (devpriv->caldacs[addr] == val) 4379 return; 4380 devpriv->caldacs[addr] = val; 4381 4382 for (i = 0; i < 3; i++) { 4383 type = board->caldac[i]; 4384 if (type == caldac_none) 4385 break; 4386 if (addr < caldacs[type].n_chans) { 4387 bits = caldacs[type].packbits(addr, val, &bitstring); 4388 loadbit = SerDacLd(i); 4389 break; 4390 } 4391 addr -= caldacs[type].n_chans; 4392 } 4393 4394 for (bit = 1 << (bits - 1); bit; bit >>= 1) { 4395 ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command); 4396 udelay(1); 4397 ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0), 4398 Serial_Command); 4399 udelay(1); 4400 } 4401 ni_writeb(dev, loadbit, Serial_Command); 4402 udelay(1); 4403 ni_writeb(dev, 0, Serial_Command); 4404} 4405 4406static int ni_calib_insn_write(struct comedi_device *dev, 4407 struct comedi_subdevice *s, 4408 struct comedi_insn *insn, 4409 unsigned int *data) 4410{ 4411 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]); 4412 4413 return 1; 4414} 4415 4416static int ni_calib_insn_read(struct comedi_device *dev, 4417 struct comedi_subdevice *s, 4418 struct comedi_insn *insn, 4419 unsigned int *data) 4420{ 4421 struct ni_private *devpriv = dev->private; 4422 4423 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; 4424 4425 return 1; 4426} 4427 4428static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) 4429{ 4430 const struct ni_board_struct *board = dev->board_ptr; 4431 struct ni_private *devpriv = dev->private; 4432 int i, j; 4433 int n_dacs; 4434 int n_chans = 0; 4435 int n_bits; 4436 int diffbits = 0; 4437 int type; 4438 int chan; 4439 4440 type = board->caldac[0]; 4441 if (type == caldac_none) 4442 return; 4443 n_bits = caldacs[type].n_bits; 4444 for (i = 0; i < 3; i++) { 4445 type = board->caldac[i]; 4446 if (type == caldac_none) 4447 break; 4448 if (caldacs[type].n_bits != n_bits) 4449 diffbits = 1; 4450 n_chans += caldacs[type].n_chans; 4451 } 4452 n_dacs = i; 4453 s->n_chan = n_chans; 4454 4455 if (diffbits) { 4456 unsigned int *maxdata_list; 4457 4458 if (n_chans > MAX_N_CALDACS) 4459 dev_err(dev->class_dev, 4460 "BUG! MAX_N_CALDACS too small\n"); 4461 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list; 4462 chan = 0; 4463 for (i = 0; i < n_dacs; i++) { 4464 type = board->caldac[i]; 4465 for (j = 0; j < caldacs[type].n_chans; j++) { 4466 maxdata_list[chan] = 4467 (1 << caldacs[type].n_bits) - 1; 4468 chan++; 4469 } 4470 } 4471 4472 for (chan = 0; chan < s->n_chan; chan++) 4473 ni_write_caldac(dev, i, s->maxdata_list[i] / 2); 4474 } else { 4475 type = board->caldac[0]; 4476 s->maxdata = (1 << caldacs[type].n_bits) - 1; 4477 4478 for (chan = 0; chan < s->n_chan; chan++) 4479 ni_write_caldac(dev, i, s->maxdata / 2); 4480 } 4481} 4482 4483static int ni_read_eeprom(struct comedi_device *dev, int addr) 4484{ 4485 int bit; 4486 int bitstring; 4487 4488 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); 4489 ni_writeb(dev, 0x04, Serial_Command); 4490 for (bit = 0x8000; bit; bit >>= 1) { 4491 ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0), 4492 Serial_Command); 4493 ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0), 4494 Serial_Command); 4495 } 4496 bitstring = 0; 4497 for (bit = 0x80; bit; bit >>= 1) { 4498 ni_writeb(dev, 0x04, Serial_Command); 4499 ni_writeb(dev, 0x05, Serial_Command); 4500 bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0); 4501 } 4502 ni_writeb(dev, 0x00, Serial_Command); 4503 4504 return bitstring; 4505} 4506 4507static int ni_eeprom_insn_read(struct comedi_device *dev, 4508 struct comedi_subdevice *s, 4509 struct comedi_insn *insn, 4510 unsigned int *data) 4511{ 4512 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); 4513 4514 return 1; 4515} 4516 4517static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, 4518 struct comedi_subdevice *s, 4519 struct comedi_insn *insn, 4520 unsigned int *data) 4521{ 4522 struct ni_private *devpriv = dev->private; 4523 4524 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; 4525 4526 return 1; 4527} 4528 4529static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, 4530 unsigned chan) 4531{ 4532 /* pre-m-series boards have fixed signals on pfi pins */ 4533 switch (chan) { 4534 case 0: 4535 return NI_PFI_OUTPUT_AI_START1; 4536 case 1: 4537 return NI_PFI_OUTPUT_AI_START2; 4538 case 2: 4539 return NI_PFI_OUTPUT_AI_CONVERT; 4540 case 3: 4541 return NI_PFI_OUTPUT_G_SRC1; 4542 case 4: 4543 return NI_PFI_OUTPUT_G_GATE1; 4544 case 5: 4545 return NI_PFI_OUTPUT_AO_UPDATE_N; 4546 case 6: 4547 return NI_PFI_OUTPUT_AO_START1; 4548 case 7: 4549 return NI_PFI_OUTPUT_AI_START_PULSE; 4550 case 8: 4551 return NI_PFI_OUTPUT_G_SRC0; 4552 case 9: 4553 return NI_PFI_OUTPUT_G_GATE0; 4554 default: 4555 dev_err(dev->class_dev, 4556 "%s: bug, unhandled case in switch.\n", __func__); 4557 break; 4558 } 4559 return 0; 4560} 4561 4562static int ni_old_set_pfi_routing(struct comedi_device *dev, 4563 unsigned chan, unsigned source) 4564{ 4565 /* pre-m-series boards have fixed signals on pfi pins */ 4566 if (source != ni_old_get_pfi_routing(dev, chan)) 4567 return -EINVAL; 4568 return 2; 4569} 4570 4571static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, 4572 unsigned chan) 4573{ 4574 struct ni_private *devpriv = dev->private; 4575 const unsigned array_offset = chan / 3; 4576 4577 return MSeries_PFI_Output_Select_Source(chan, 4578 devpriv->pfi_output_select_reg[array_offset]); 4579} 4580 4581static int ni_m_series_set_pfi_routing(struct comedi_device *dev, 4582 unsigned chan, unsigned source) 4583{ 4584 struct ni_private *devpriv = dev->private; 4585 unsigned pfi_reg_index; 4586 unsigned array_offset; 4587 4588 if ((source & 0x1f) != source) 4589 return -EINVAL; 4590 pfi_reg_index = 1 + chan / 3; 4591 array_offset = pfi_reg_index - 1; 4592 devpriv->pfi_output_select_reg[array_offset] &= 4593 ~MSeries_PFI_Output_Select_Mask(chan); 4594 devpriv->pfi_output_select_reg[array_offset] |= 4595 MSeries_PFI_Output_Select_Bits(chan, source); 4596 ni_writew(dev, devpriv->pfi_output_select_reg[array_offset], 4597 M_Offset_PFI_Output_Select(pfi_reg_index)); 4598 return 2; 4599} 4600 4601static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) 4602{ 4603 struct ni_private *devpriv = dev->private; 4604 4605 return (devpriv->is_m_series) 4606 ? ni_m_series_get_pfi_routing(dev, chan) 4607 : ni_old_get_pfi_routing(dev, chan); 4608} 4609 4610static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, 4611 unsigned source) 4612{ 4613 struct ni_private *devpriv = dev->private; 4614 4615 return (devpriv->is_m_series) 4616 ? ni_m_series_set_pfi_routing(dev, chan, source) 4617 : ni_old_set_pfi_routing(dev, chan, source); 4618} 4619 4620static int ni_config_filter(struct comedi_device *dev, 4621 unsigned pfi_channel, 4622 enum ni_pfi_filter_select filter) 4623{ 4624 struct ni_private *devpriv = dev->private; 4625 unsigned bits; 4626 4627 if (!devpriv->is_m_series) 4628 return -ENOTSUPP; 4629 4630 bits = ni_readl(dev, M_Offset_PFI_Filter); 4631 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel); 4632 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter); 4633 ni_writel(dev, bits, M_Offset_PFI_Filter); 4634 return 0; 4635} 4636 4637static int ni_pfi_insn_config(struct comedi_device *dev, 4638 struct comedi_subdevice *s, 4639 struct comedi_insn *insn, 4640 unsigned int *data) 4641{ 4642 struct ni_private *devpriv = dev->private; 4643 unsigned int chan; 4644 4645 if (insn->n < 1) 4646 return -EINVAL; 4647 4648 chan = CR_CHAN(insn->chanspec); 4649 4650 switch (data[0]) { 4651 case COMEDI_OUTPUT: 4652 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1); 4653 break; 4654 case COMEDI_INPUT: 4655 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0); 4656 break; 4657 case INSN_CONFIG_DIO_QUERY: 4658 data[1] = 4659 (devpriv->io_bidirection_pin_reg & (1 << chan)) ? 4660 COMEDI_OUTPUT : COMEDI_INPUT; 4661 return 0; 4662 case INSN_CONFIG_SET_ROUTING: 4663 return ni_set_pfi_routing(dev, chan, data[1]); 4664 case INSN_CONFIG_GET_ROUTING: 4665 data[1] = ni_get_pfi_routing(dev, chan); 4666 break; 4667 case INSN_CONFIG_FILTER: 4668 return ni_config_filter(dev, chan, data[1]); 4669 default: 4670 return -EINVAL; 4671 } 4672 return 0; 4673} 4674 4675static int ni_pfi_insn_bits(struct comedi_device *dev, 4676 struct comedi_subdevice *s, 4677 struct comedi_insn *insn, 4678 unsigned int *data) 4679{ 4680 struct ni_private *devpriv = dev->private; 4681 4682 if (!devpriv->is_m_series) 4683 return -ENOTSUPP; 4684 4685 if (comedi_dio_update_state(s, data)) 4686 ni_writew(dev, s->state, M_Offset_PFI_DO); 4687 4688 data[1] = ni_readw(dev, M_Offset_PFI_DI); 4689 4690 return insn->n; 4691} 4692 4693static int cs5529_wait_for_idle(struct comedi_device *dev) 4694{ 4695 unsigned short status; 4696 const int timeout = HZ; 4697 int i; 4698 4699 for (i = 0; i < timeout; i++) { 4700 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); 4701 if ((status & CSS_ADC_BUSY) == 0) 4702 break; 4703 set_current_state(TASK_INTERRUPTIBLE); 4704 if (schedule_timeout(1)) 4705 return -EIO; 4706 } 4707 if (i == timeout) { 4708 dev_err(dev->class_dev, "%s timeout\n", __func__); 4709 return -ETIME; 4710 } 4711 return 0; 4712} 4713 4714static void cs5529_command(struct comedi_device *dev, unsigned short value) 4715{ 4716 static const int timeout = 100; 4717 int i; 4718 4719 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx); 4720 /* give time for command to start being serially clocked into cs5529. 4721 * this insures that the CSS_ADC_BUSY bit will get properly 4722 * set before we exit this function. 4723 */ 4724 for (i = 0; i < timeout; i++) { 4725 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY)) 4726 break; 4727 udelay(1); 4728 } 4729 if (i == timeout) 4730 dev_err(dev->class_dev, 4731 "possible problem - never saw adc go busy?\n"); 4732} 4733 4734static int cs5529_do_conversion(struct comedi_device *dev, 4735 unsigned short *data) 4736{ 4737 int retval; 4738 unsigned short status; 4739 4740 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION); 4741 retval = cs5529_wait_for_idle(dev); 4742 if (retval) { 4743 dev_err(dev->class_dev, 4744 "timeout or signal in cs5529_do_conversion()\n"); 4745 return -ETIME; 4746 } 4747 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); 4748 if (status & CSS_OSC_DETECT) { 4749 dev_err(dev->class_dev, 4750 "cs5529 conversion error, status CSS_OSC_DETECT\n"); 4751 return -EIO; 4752 } 4753 if (status & CSS_OVERRANGE) { 4754 dev_err(dev->class_dev, 4755 "cs5529 conversion error, overrange (ignoring)\n"); 4756 } 4757 if (data) { 4758 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx); 4759 /* cs5529 returns 16 bit signed data in bipolar mode */ 4760 *data ^= (1 << 15); 4761 } 4762 return 0; 4763} 4764 4765static int cs5529_ai_insn_read(struct comedi_device *dev, 4766 struct comedi_subdevice *s, 4767 struct comedi_insn *insn, 4768 unsigned int *data) 4769{ 4770 int n, retval; 4771 unsigned short sample; 4772 unsigned int channel_select; 4773 const unsigned int INTERNAL_REF = 0x1000; 4774 4775 /* Set calibration adc source. Docs lie, reference select bits 8 to 11 4776 * do nothing. bit 12 seems to chooses internal reference voltage, bit 4777 * 13 causes the adc input to go overrange (maybe reads external reference?) */ 4778 if (insn->chanspec & CR_ALT_SOURCE) 4779 channel_select = INTERNAL_REF; 4780 else 4781 channel_select = CR_CHAN(insn->chanspec); 4782 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx); 4783 4784 for (n = 0; n < insn->n; n++) { 4785 retval = cs5529_do_conversion(dev, &sample); 4786 if (retval < 0) 4787 return retval; 4788 data[n] = sample; 4789 } 4790 return insn->n; 4791} 4792 4793static void cs5529_config_write(struct comedi_device *dev, unsigned int value, 4794 unsigned int reg_select_bits) 4795{ 4796 ni_ao_win_outw(dev, ((value >> 16) & 0xff), 4797 CAL_ADC_Config_Data_High_Word_67xx); 4798 ni_ao_win_outw(dev, (value & 0xffff), 4799 CAL_ADC_Config_Data_Low_Word_67xx); 4800 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; 4801 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits); 4802 if (cs5529_wait_for_idle(dev)) 4803 dev_err(dev->class_dev, 4804 "timeout or signal in %s\n", __func__); 4805} 4806 4807static int init_cs5529(struct comedi_device *dev) 4808{ 4809 unsigned int config_bits = 4810 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES; 4811 4812#if 1 4813 /* do self-calibration */ 4814 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, 4815 CSCMD_CONFIG_REGISTER); 4816 /* need to force a conversion for calibration to run */ 4817 cs5529_do_conversion(dev, NULL); 4818#else 4819 /* force gain calibration to 1 */ 4820 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER); 4821 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, 4822 CSCMD_CONFIG_REGISTER); 4823 if (cs5529_wait_for_idle(dev)) 4824 dev_err(dev->class_dev, 4825 "timeout or signal in %s\n", __func__); 4826#endif 4827 return 0; 4828} 4829 4830/* 4831 * Find best multiplier/divider to try and get the PLL running at 80 MHz 4832 * given an arbitrary frequency input clock. 4833 */ 4834static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, 4835 unsigned *freq_divider, 4836 unsigned *freq_multiplier, 4837 unsigned *actual_period_ns) 4838{ 4839 unsigned div; 4840 unsigned best_div = 1; 4841 static const unsigned max_div = 0x10; 4842 unsigned mult; 4843 unsigned best_mult = 1; 4844 static const unsigned max_mult = 0x100; 4845 static const unsigned pico_per_nano = 1000; 4846 4847 const unsigned reference_picosec = reference_period_ns * pico_per_nano; 4848 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to 4849 * 20 MHz for most timing clocks */ 4850 static const unsigned target_picosec = 12500; 4851 static const unsigned fudge_factor_80_to_20Mhz = 4; 4852 int best_period_picosec = 0; 4853 4854 for (div = 1; div <= max_div; ++div) { 4855 for (mult = 1; mult <= max_mult; ++mult) { 4856 unsigned new_period_ps = 4857 (reference_picosec * div) / mult; 4858 if (abs(new_period_ps - target_picosec) < 4859 abs(best_period_picosec - target_picosec)) { 4860 best_period_picosec = new_period_ps; 4861 best_div = div; 4862 best_mult = mult; 4863 } 4864 } 4865 } 4866 if (best_period_picosec == 0) 4867 return -EIO; 4868 4869 *freq_divider = best_div; 4870 *freq_multiplier = best_mult; 4871 *actual_period_ns = 4872 (best_period_picosec * fudge_factor_80_to_20Mhz + 4873 (pico_per_nano / 2)) / pico_per_nano; 4874 return 0; 4875} 4876 4877static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, 4878 unsigned source, unsigned period_ns) 4879{ 4880 struct ni_private *devpriv = dev->private; 4881 static const unsigned min_period_ns = 50; 4882 static const unsigned max_period_ns = 1000; 4883 static const unsigned timeout = 1000; 4884 unsigned pll_control_bits; 4885 unsigned freq_divider; 4886 unsigned freq_multiplier; 4887 unsigned i; 4888 int retval; 4889 4890 if (source == NI_MIO_PLL_PXI10_CLOCK) 4891 period_ns = 100; 4892 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */ 4893 if (period_ns < min_period_ns || period_ns > max_period_ns) { 4894 dev_err(dev->class_dev, 4895 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n", 4896 __func__, min_period_ns, max_period_ns); 4897 return -EINVAL; 4898 } 4899 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; 4900 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, 4901 RTSI_Trig_Direction_Register); 4902 pll_control_bits = 4903 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; 4904 devpriv->clock_and_fout2 |= 4905 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit; 4906 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask; 4907 switch (source) { 4908 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: 4909 devpriv->clock_and_fout2 |= 4910 MSeries_PLL_In_Source_Select_Star_Trigger_Bits; 4911 break; 4912 case NI_MIO_PLL_PXI10_CLOCK: 4913 /* pxi clock is 10MHz */ 4914 devpriv->clock_and_fout2 |= 4915 MSeries_PLL_In_Source_Select_PXI_Clock10; 4916 break; 4917 default: 4918 { 4919 unsigned rtsi_channel; 4920 static const unsigned max_rtsi_channel = 7; 4921 4922 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; 4923 ++rtsi_channel) { 4924 if (source == 4925 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) { 4926 devpriv->clock_and_fout2 |= 4927 MSeries_PLL_In_Source_Select_RTSI_Bits 4928 (rtsi_channel); 4929 break; 4930 } 4931 } 4932 if (rtsi_channel > max_rtsi_channel) 4933 return -EINVAL; 4934 } 4935 break; 4936 } 4937 retval = ni_mseries_get_pll_parameters(period_ns, 4938 &freq_divider, 4939 &freq_multiplier, 4940 &devpriv->clock_ns); 4941 if (retval < 0) { 4942 dev_err(dev->class_dev, 4943 "%s: bug, failed to find pll parameters\n", __func__); 4944 return retval; 4945 } 4946 4947 ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); 4948 pll_control_bits |= 4949 MSeries_PLL_Divisor_Bits(freq_divider) | 4950 MSeries_PLL_Multiplier_Bits(freq_multiplier); 4951 4952 ni_writew(dev, pll_control_bits, M_Offset_PLL_Control); 4953 devpriv->clock_source = source; 4954 /* it seems to typically take a few hundred microseconds for PLL to lock */ 4955 for (i = 0; i < timeout; ++i) { 4956 if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) 4957 break; 4958 udelay(1); 4959 } 4960 if (i == timeout) { 4961 dev_err(dev->class_dev, 4962 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n", 4963 __func__, source, period_ns); 4964 return -ETIMEDOUT; 4965 } 4966 return 3; 4967} 4968 4969static int ni_set_master_clock(struct comedi_device *dev, 4970 unsigned source, unsigned period_ns) 4971{ 4972 struct ni_private *devpriv = dev->private; 4973 4974 if (source == NI_MIO_INTERNAL_CLOCK) { 4975 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; 4976 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, 4977 RTSI_Trig_Direction_Register); 4978 devpriv->clock_ns = TIMEBASE_1_NS; 4979 if (devpriv->is_m_series) { 4980 devpriv->clock_and_fout2 &= 4981 ~(MSeries_Timebase1_Select_Bit | 4982 MSeries_Timebase3_Select_Bit); 4983 ni_writew(dev, devpriv->clock_and_fout2, 4984 M_Offset_Clock_and_Fout2); 4985 ni_writew(dev, 0, M_Offset_PLL_Control); 4986 } 4987 devpriv->clock_source = source; 4988 } else { 4989 if (devpriv->is_m_series) { 4990 return ni_mseries_set_pll_master_clock(dev, source, 4991 period_ns); 4992 } else { 4993 if (source == NI_MIO_RTSI_CLOCK) { 4994 devpriv->rtsi_trig_direction_reg |= 4995 Use_RTSI_Clock_Bit; 4996 ni_stc_writew(dev, 4997 devpriv->rtsi_trig_direction_reg, 4998 RTSI_Trig_Direction_Register); 4999 if (period_ns == 0) { 5000 dev_err(dev->class_dev, 5001 "%s: we don't handle an unspecified clock period correctly yet, returning error\n", 5002 __func__); 5003 return -EINVAL; 5004 } 5005 devpriv->clock_ns = period_ns; 5006 devpriv->clock_source = source; 5007 } else 5008 return -EINVAL; 5009 } 5010 } 5011 return 3; 5012} 5013 5014static unsigned num_configurable_rtsi_channels(struct comedi_device *dev) 5015{ 5016 struct ni_private *devpriv = dev->private; 5017 5018 return (devpriv->is_m_series) ? 8 : 7; 5019} 5020 5021static int ni_valid_rtsi_output_source(struct comedi_device *dev, 5022 unsigned chan, unsigned source) 5023{ 5024 struct ni_private *devpriv = dev->private; 5025 5026 if (chan >= num_configurable_rtsi_channels(dev)) { 5027 if (chan == old_RTSI_clock_channel) { 5028 if (source == NI_RTSI_OUTPUT_RTSI_OSC) 5029 return 1; 5030 5031 dev_err(dev->class_dev, 5032 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n", 5033 __func__, chan, old_RTSI_clock_channel); 5034 return 0; 5035 } 5036 return 0; 5037 } 5038 switch (source) { 5039 case NI_RTSI_OUTPUT_ADR_START1: 5040 case NI_RTSI_OUTPUT_ADR_START2: 5041 case NI_RTSI_OUTPUT_SCLKG: 5042 case NI_RTSI_OUTPUT_DACUPDN: 5043 case NI_RTSI_OUTPUT_DA_START1: 5044 case NI_RTSI_OUTPUT_G_SRC0: 5045 case NI_RTSI_OUTPUT_G_GATE0: 5046 case NI_RTSI_OUTPUT_RGOUT0: 5047 case NI_RTSI_OUTPUT_RTSI_BRD_0: 5048 return 1; 5049 case NI_RTSI_OUTPUT_RTSI_OSC: 5050 return (devpriv->is_m_series) ? 1 : 0; 5051 default: 5052 return 0; 5053 } 5054} 5055 5056static int ni_set_rtsi_routing(struct comedi_device *dev, 5057 unsigned chan, unsigned source) 5058{ 5059 struct ni_private *devpriv = dev->private; 5060 5061 if (ni_valid_rtsi_output_source(dev, chan, source) == 0) 5062 return -EINVAL; 5063 if (chan < 4) { 5064 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan); 5065 devpriv->rtsi_trig_a_output_reg |= 5066 RTSI_Trig_Output_Bits(chan, source); 5067 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, 5068 RTSI_Trig_A_Output_Register); 5069 } else if (chan < 8) { 5070 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan); 5071 devpriv->rtsi_trig_b_output_reg |= 5072 RTSI_Trig_Output_Bits(chan, source); 5073 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, 5074 RTSI_Trig_B_Output_Register); 5075 } 5076 return 2; 5077} 5078 5079static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan) 5080{ 5081 struct ni_private *devpriv = dev->private; 5082 5083 if (chan < 4) { 5084 return RTSI_Trig_Output_Source(chan, 5085 devpriv->rtsi_trig_a_output_reg); 5086 } else if (chan < num_configurable_rtsi_channels(dev)) { 5087 return RTSI_Trig_Output_Source(chan, 5088 devpriv->rtsi_trig_b_output_reg); 5089 } else { 5090 if (chan == old_RTSI_clock_channel) 5091 return NI_RTSI_OUTPUT_RTSI_OSC; 5092 dev_err(dev->class_dev, "%s: bug! should never get here?\n", 5093 __func__); 5094 return 0; 5095 } 5096} 5097 5098static int ni_rtsi_insn_config(struct comedi_device *dev, 5099 struct comedi_subdevice *s, 5100 struct comedi_insn *insn, 5101 unsigned int *data) 5102{ 5103 struct ni_private *devpriv = dev->private; 5104 unsigned int chan = CR_CHAN(insn->chanspec); 5105 5106 switch (data[0]) { 5107 case INSN_CONFIG_DIO_OUTPUT: 5108 if (chan < num_configurable_rtsi_channels(dev)) { 5109 devpriv->rtsi_trig_direction_reg |= 5110 RTSI_Output_Bit(chan, devpriv->is_m_series); 5111 } else if (chan == old_RTSI_clock_channel) { 5112 devpriv->rtsi_trig_direction_reg |= 5113 Drive_RTSI_Clock_Bit; 5114 } 5115 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5116 RTSI_Trig_Direction_Register); 5117 break; 5118 case INSN_CONFIG_DIO_INPUT: 5119 if (chan < num_configurable_rtsi_channels(dev)) { 5120 devpriv->rtsi_trig_direction_reg &= 5121 ~RTSI_Output_Bit(chan, devpriv->is_m_series); 5122 } else if (chan == old_RTSI_clock_channel) { 5123 devpriv->rtsi_trig_direction_reg &= 5124 ~Drive_RTSI_Clock_Bit; 5125 } 5126 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5127 RTSI_Trig_Direction_Register); 5128 break; 5129 case INSN_CONFIG_DIO_QUERY: 5130 if (chan < num_configurable_rtsi_channels(dev)) { 5131 data[1] = 5132 (devpriv->rtsi_trig_direction_reg & 5133 RTSI_Output_Bit(chan, devpriv->is_m_series)) 5134 ? INSN_CONFIG_DIO_OUTPUT 5135 : INSN_CONFIG_DIO_INPUT; 5136 } else if (chan == old_RTSI_clock_channel) { 5137 data[1] = 5138 (devpriv->rtsi_trig_direction_reg & 5139 Drive_RTSI_Clock_Bit) 5140 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT; 5141 } 5142 return 2; 5143 case INSN_CONFIG_SET_CLOCK_SRC: 5144 return ni_set_master_clock(dev, data[1], data[2]); 5145 case INSN_CONFIG_GET_CLOCK_SRC: 5146 data[1] = devpriv->clock_source; 5147 data[2] = devpriv->clock_ns; 5148 return 3; 5149 case INSN_CONFIG_SET_ROUTING: 5150 return ni_set_rtsi_routing(dev, chan, data[1]); 5151 case INSN_CONFIG_GET_ROUTING: 5152 data[1] = ni_get_rtsi_routing(dev, chan); 5153 return 2; 5154 default: 5155 return -EINVAL; 5156 } 5157 return 1; 5158} 5159 5160static int ni_rtsi_insn_bits(struct comedi_device *dev, 5161 struct comedi_subdevice *s, 5162 struct comedi_insn *insn, 5163 unsigned int *data) 5164{ 5165 data[1] = 0; 5166 5167 return insn->n; 5168} 5169 5170static void ni_rtsi_init(struct comedi_device *dev) 5171{ 5172 struct ni_private *devpriv = dev->private; 5173 5174 /* Initialises the RTSI bus signal switch to a default state */ 5175 5176 /* Set clock mode to internal */ 5177 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit; 5178 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) 5179 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n"); 5180 /* default internal lines routing to RTSI bus lines */ 5181 devpriv->rtsi_trig_a_output_reg = 5182 RTSI_Trig_Output_Bits(0, 5183 NI_RTSI_OUTPUT_ADR_START1) | 5184 RTSI_Trig_Output_Bits(1, 5185 NI_RTSI_OUTPUT_ADR_START2) | 5186 RTSI_Trig_Output_Bits(2, 5187 NI_RTSI_OUTPUT_SCLKG) | 5188 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN); 5189 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, 5190 RTSI_Trig_A_Output_Register); 5191 devpriv->rtsi_trig_b_output_reg = 5192 RTSI_Trig_Output_Bits(4, 5193 NI_RTSI_OUTPUT_DA_START1) | 5194 RTSI_Trig_Output_Bits(5, 5195 NI_RTSI_OUTPUT_G_SRC0) | 5196 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0); 5197 if (devpriv->is_m_series) 5198 devpriv->rtsi_trig_b_output_reg |= 5199 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC); 5200 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, 5201 RTSI_Trig_B_Output_Register); 5202 5203/* 5204* Sets the source and direction of the 4 on board lines 5205* ni_stc_writew(dev, 0x0000, RTSI_Board_Register); 5206*/ 5207} 5208 5209#ifdef PCIDMA 5210static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 5211{ 5212 struct ni_gpct *counter = s->private; 5213 int retval; 5214 5215 retval = ni_request_gpct_mite_channel(dev, counter->counter_index, 5216 COMEDI_INPUT); 5217 if (retval) { 5218 dev_err(dev->class_dev, 5219 "no dma channel available for use by counter\n"); 5220 return retval; 5221 } 5222 ni_tio_acknowledge(counter); 5223 ni_e_series_enable_second_irq(dev, counter->counter_index, 1); 5224 5225 return ni_tio_cmd(dev, s); 5226} 5227 5228static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 5229{ 5230 struct ni_gpct *counter = s->private; 5231 int retval; 5232 5233 retval = ni_tio_cancel(counter); 5234 ni_e_series_enable_second_irq(dev, counter->counter_index, 0); 5235 ni_release_gpct_mite_channel(dev, counter->counter_index); 5236 return retval; 5237} 5238#endif 5239 5240#if 0 5241/* 5242 * Read the GPCTs current value. 5243 */ 5244static int GPCT_G_Watch(struct comedi_device *dev, int chan) 5245{ 5246 unsigned int hi1, hi2, lo; 5247 5248 devpriv->gpct_command[chan] &= ~G_Save_Trace; 5249 ni_stc_writew(dev, devpriv->gpct_command[chan], 5250 G_Command_Register(chan)); 5251 5252 devpriv->gpct_command[chan] |= G_Save_Trace; 5253 ni_stc_writew(dev, devpriv->gpct_command[chan], 5254 G_Command_Register(chan)); 5255 5256 /* This procedure is used because the two registers cannot 5257 * be read atomically. */ 5258 do { 5259 hi1 = ni_stc_readw(dev, G_Save_Register_High(chan)); 5260 lo = ni_stc_readw(dev, G_Save_Register_Low(chan)); 5261 hi2 = ni_stc_readw(dev, G_Save_Register_High(chan)); 5262 } while (hi1 != hi2); 5263 5264 return (hi1 << 16) | lo; 5265} 5266 5267static void GPCT_Reset(struct comedi_device *dev, int chan) 5268{ 5269 int temp_ack_reg = 0; 5270 5271 devpriv->gpct_cur_operation[chan] = GPCT_RESET; 5272 5273 switch (chan) { 5274 case 0: 5275 ni_stc_writew(dev, G0_Reset, Joint_Reset_Register); 5276 ni_set_bits(dev, Interrupt_A_Enable_Register, 5277 G0_TC_Interrupt_Enable, 0); 5278 ni_set_bits(dev, Interrupt_A_Enable_Register, 5279 G0_Gate_Interrupt_Enable, 0); 5280 temp_ack_reg |= G0_Gate_Error_Confirm; 5281 temp_ack_reg |= G0_TC_Error_Confirm; 5282 temp_ack_reg |= G0_TC_Interrupt_Ack; 5283 temp_ack_reg |= G0_Gate_Interrupt_Ack; 5284 ni_stc_writew(dev, temp_ack_reg, Interrupt_A_Ack_Register); 5285 5286 /* problem...this interferes with the other ctr... */ 5287 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable; 5288 ni_stc_writew(dev, devpriv->an_trig_etc_reg, 5289 Analog_Trigger_Etc_Register); 5290 break; 5291 case 1: 5292 ni_stc_writew(dev, G1_Reset, Joint_Reset_Register); 5293 ni_set_bits(dev, Interrupt_B_Enable_Register, 5294 G1_TC_Interrupt_Enable, 0); 5295 ni_set_bits(dev, Interrupt_B_Enable_Register, 5296 G0_Gate_Interrupt_Enable, 0); 5297 temp_ack_reg |= G1_Gate_Error_Confirm; 5298 temp_ack_reg |= G1_TC_Error_Confirm; 5299 temp_ack_reg |= G1_TC_Interrupt_Ack; 5300 temp_ack_reg |= G1_Gate_Interrupt_Ack; 5301 ni_stc_writew(dev, temp_ack_reg, Interrupt_B_Ack_Register); 5302 5303 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable; 5304 ni_stc_writew(dev, devpriv->an_trig_etc_reg, 5305 Analog_Trigger_Etc_Register); 5306 break; 5307 } 5308 5309 devpriv->gpct_mode[chan] = 0; 5310 devpriv->gpct_input_select[chan] = 0; 5311 devpriv->gpct_command[chan] = 0; 5312 5313 devpriv->gpct_command[chan] |= G_Synchronized_Gate; 5314 5315 ni_stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan)); 5316 ni_stc_writew(dev, devpriv->gpct_input_select[chan], 5317 G_Input_Select_Register(chan)); 5318 ni_stc_writew(dev, 0, G_Autoincrement_Register(chan)); 5319} 5320#endif 5321 5322static irqreturn_t ni_E_interrupt(int irq, void *d) 5323{ 5324 struct comedi_device *dev = d; 5325 unsigned short a_status; 5326 unsigned short b_status; 5327 unsigned int ai_mite_status = 0; 5328 unsigned int ao_mite_status = 0; 5329 unsigned long flags; 5330#ifdef PCIDMA 5331 struct ni_private *devpriv = dev->private; 5332 struct mite_struct *mite = devpriv->mite; 5333#endif 5334 5335 if (!dev->attached) 5336 return IRQ_NONE; 5337 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */ 5338 5339 /* lock to avoid race with comedi_poll */ 5340 spin_lock_irqsave(&dev->spinlock, flags); 5341 a_status = ni_stc_readw(dev, AI_Status_1_Register); 5342 b_status = ni_stc_readw(dev, AO_Status_1_Register); 5343#ifdef PCIDMA 5344 if (mite) { 5345 struct ni_private *devpriv = dev->private; 5346 unsigned long flags_too; 5347 5348 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); 5349 if (devpriv->ai_mite_chan) { 5350 ai_mite_status = mite_get_status(devpriv->ai_mite_chan); 5351 if (ai_mite_status & CHSR_LINKC) 5352 writel(CHOR_CLRLC, 5353 devpriv->mite->mite_io_addr + 5354 MITE_CHOR(devpriv-> 5355 ai_mite_chan->channel)); 5356 } 5357 if (devpriv->ao_mite_chan) { 5358 ao_mite_status = mite_get_status(devpriv->ao_mite_chan); 5359 if (ao_mite_status & CHSR_LINKC) 5360 writel(CHOR_CLRLC, 5361 mite->mite_io_addr + 5362 MITE_CHOR(devpriv-> 5363 ao_mite_chan->channel)); 5364 } 5365 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); 5366 } 5367#endif 5368 ack_a_interrupt(dev, a_status); 5369 ack_b_interrupt(dev, b_status); 5370 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT)) 5371 handle_a_interrupt(dev, a_status, ai_mite_status); 5372 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT)) 5373 handle_b_interrupt(dev, b_status, ao_mite_status); 5374 handle_gpct_interrupt(dev, 0); 5375 handle_gpct_interrupt(dev, 1); 5376 handle_cdio_interrupt(dev); 5377 5378 spin_unlock_irqrestore(&dev->spinlock, flags); 5379 return IRQ_HANDLED; 5380} 5381 5382static int ni_alloc_private(struct comedi_device *dev) 5383{ 5384 struct ni_private *devpriv; 5385 5386 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); 5387 if (!devpriv) 5388 return -ENOMEM; 5389 5390 spin_lock_init(&devpriv->window_lock); 5391 spin_lock_init(&devpriv->soft_reg_copy_lock); 5392 spin_lock_init(&devpriv->mite_channel_lock); 5393 5394 return 0; 5395} 5396 5397static int ni_E_init(struct comedi_device *dev, 5398 unsigned interrupt_pin, unsigned irq_polarity) 5399{ 5400 const struct ni_board_struct *board = dev->board_ptr; 5401 struct ni_private *devpriv = dev->private; 5402 struct comedi_subdevice *s; 5403 int ret; 5404 int i; 5405 5406 if (board->n_aochan > MAX_N_AO_CHAN) { 5407 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n"); 5408 return -EINVAL; 5409 } 5410 5411 /* initialize clock dividers */ 5412 devpriv->clock_and_fout = Slow_Internal_Time_Divide_By_2 | 5413 Slow_Internal_Timebase | 5414 Clock_To_Board_Divide_By_2 | 5415 Clock_To_Board; 5416 if (!devpriv->is_6xxx) { 5417 /* BEAM is this needed for PCI-6143 ?? */ 5418 devpriv->clock_and_fout |= (AI_Output_Divide_By_2 | 5419 AO_Output_Divide_By_2); 5420 } 5421 ni_stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register); 5422 5423 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES); 5424 if (ret) 5425 return ret; 5426 5427 /* Analog Input subdevice */ 5428 s = &dev->subdevices[NI_AI_SUBDEV]; 5429 if (board->n_adchan) { 5430 s->type = COMEDI_SUBD_AI; 5431 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER; 5432 if (!devpriv->is_611x) 5433 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; 5434 if (board->ai_maxdata > 0xffff) 5435 s->subdev_flags |= SDF_LSAMPL; 5436 if (devpriv->is_m_series) 5437 s->subdev_flags |= SDF_SOFT_CALIBRATED; 5438 s->n_chan = board->n_adchan; 5439 s->maxdata = board->ai_maxdata; 5440 s->range_table = ni_range_lkup[board->gainlkup]; 5441 s->insn_read = ni_ai_insn_read; 5442 s->insn_config = ni_ai_insn_config; 5443 if (dev->irq) { 5444 dev->read_subdev = s; 5445 s->subdev_flags |= SDF_CMD_READ; 5446 s->len_chanlist = 512; 5447 s->do_cmdtest = ni_ai_cmdtest; 5448 s->do_cmd = ni_ai_cmd; 5449 s->cancel = ni_ai_reset; 5450 s->poll = ni_ai_poll; 5451 s->munge = ni_ai_munge; 5452 5453 if (devpriv->mite) 5454 s->async_dma_dir = DMA_FROM_DEVICE; 5455 } 5456 5457 /* reset the analog input configuration */ 5458 ni_ai_reset(dev, s); 5459 } else { 5460 s->type = COMEDI_SUBD_UNUSED; 5461 } 5462 5463 /* Analog Output subdevice */ 5464 s = &dev->subdevices[NI_AO_SUBDEV]; 5465 if (board->n_aochan) { 5466 s->type = COMEDI_SUBD_AO; 5467 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; 5468 if (devpriv->is_m_series) 5469 s->subdev_flags |= SDF_SOFT_CALIBRATED; 5470 s->n_chan = board->n_aochan; 5471 s->maxdata = board->ao_maxdata; 5472 s->range_table = board->ao_range_table; 5473 s->insn_config = ni_ao_insn_config; 5474 s->insn_write = ni_ao_insn_write; 5475 s->insn_read = comedi_readback_insn_read; 5476 5477 ret = comedi_alloc_subdev_readback(s); 5478 if (ret) 5479 return ret; 5480 5481 /* 5482 * Along with the IRQ we need either a FIFO or DMA for 5483 * async command support. 5484 */ 5485 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) { 5486 dev->write_subdev = s; 5487 s->subdev_flags |= SDF_CMD_WRITE; 5488 s->len_chanlist = s->n_chan; 5489 s->do_cmdtest = ni_ao_cmdtest; 5490 s->do_cmd = ni_ao_cmd; 5491 s->cancel = ni_ao_reset; 5492 if (!devpriv->is_m_series) 5493 s->munge = ni_ao_munge; 5494 5495 if (devpriv->mite) 5496 s->async_dma_dir = DMA_TO_DEVICE; 5497 } 5498 5499 if (devpriv->is_67xx) 5500 init_ao_67xx(dev, s); 5501 5502 /* reset the analog output configuration */ 5503 ni_ao_reset(dev, s); 5504 } else { 5505 s->type = COMEDI_SUBD_UNUSED; 5506 } 5507 5508 /* Digital I/O subdevice */ 5509 s = &dev->subdevices[NI_DIO_SUBDEV]; 5510 s->type = COMEDI_SUBD_DIO; 5511 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 5512 s->n_chan = board->has_32dio_chan ? 32 : 8; 5513 s->maxdata = 1; 5514 s->range_table = &range_digital; 5515 if (devpriv->is_m_series) { 5516 s->subdev_flags |= SDF_LSAMPL; 5517 s->insn_bits = ni_m_series_dio_insn_bits; 5518 s->insn_config = ni_m_series_dio_insn_config; 5519 if (dev->irq) { 5520 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */; 5521 s->len_chanlist = s->n_chan; 5522 s->do_cmdtest = ni_cdio_cmdtest; 5523 s->do_cmd = ni_cdio_cmd; 5524 s->cancel = ni_cdio_cancel; 5525 5526 /* M-series boards use DMA */ 5527 s->async_dma_dir = DMA_BIDIRECTIONAL; 5528 } 5529 5530 /* reset DIO and set all channels to inputs */ 5531 ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit, 5532 M_Offset_CDIO_Command); 5533 ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); 5534 } else { 5535 s->insn_bits = ni_dio_insn_bits; 5536 s->insn_config = ni_dio_insn_config; 5537 5538 /* set all channels to inputs */ 5539 devpriv->dio_control = DIO_Pins_Dir(s->io_bits); 5540 ni_writew(dev, devpriv->dio_control, DIO_Control_Register); 5541 } 5542 5543 /* 8255 device */ 5544 s = &dev->subdevices[NI_8255_DIO_SUBDEV]; 5545 if (board->has_8255) { 5546 ret = subdev_8255_init(dev, s, ni_8255_callback, Port_A); 5547 if (ret) 5548 return ret; 5549 } else { 5550 s->type = COMEDI_SUBD_UNUSED; 5551 } 5552 5553 /* formerly general purpose counter/timer device, but no longer used */ 5554 s = &dev->subdevices[NI_UNUSED_SUBDEV]; 5555 s->type = COMEDI_SUBD_UNUSED; 5556 5557 /* Calibration subdevice */ 5558 s = &dev->subdevices[NI_CALIBRATION_SUBDEV]; 5559 s->type = COMEDI_SUBD_CALIB; 5560 s->subdev_flags = SDF_INTERNAL; 5561 s->n_chan = 1; 5562 s->maxdata = 0; 5563 if (devpriv->is_m_series) { 5564 /* internal PWM output used for AI nonlinearity calibration */ 5565 s->insn_config = ni_m_series_pwm_config; 5566 5567 ni_writel(dev, 0x0, M_Offset_Cal_PWM); 5568 } else if (devpriv->is_6143) { 5569 /* internal PWM output used for AI nonlinearity calibration */ 5570 s->insn_config = ni_6143_pwm_config; 5571 } else { 5572 s->subdev_flags |= SDF_WRITABLE; 5573 s->insn_read = ni_calib_insn_read; 5574 s->insn_write = ni_calib_insn_write; 5575 5576 /* setup the caldacs and find the real n_chan and maxdata */ 5577 caldac_setup(dev, s); 5578 } 5579 5580 /* EEPROM subdevice */ 5581 s = &dev->subdevices[NI_EEPROM_SUBDEV]; 5582 s->type = COMEDI_SUBD_MEMORY; 5583 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 5584 s->maxdata = 0xff; 5585 if (devpriv->is_m_series) { 5586 s->n_chan = M_SERIES_EEPROM_SIZE; 5587 s->insn_read = ni_m_series_eeprom_insn_read; 5588 } else { 5589 s->n_chan = 512; 5590 s->insn_read = ni_eeprom_insn_read; 5591 } 5592 5593 /* Digital I/O (PFI) subdevice */ 5594 s = &dev->subdevices[NI_PFI_DIO_SUBDEV]; 5595 s->type = COMEDI_SUBD_DIO; 5596 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 5597 s->maxdata = 1; 5598 if (devpriv->is_m_series) { 5599 s->n_chan = 16; 5600 s->insn_bits = ni_pfi_insn_bits; 5601 5602 ni_writew(dev, s->state, M_Offset_PFI_DO); 5603 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { 5604 ni_writew(dev, devpriv->pfi_output_select_reg[i], 5605 M_Offset_PFI_Output_Select(i + 1)); 5606 } 5607 } else { 5608 s->n_chan = 10; 5609 } 5610 s->insn_config = ni_pfi_insn_config; 5611 5612 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0); 5613 5614 /* cs5529 calibration adc */ 5615 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV]; 5616 if (devpriv->is_67xx) { 5617 s->type = COMEDI_SUBD_AI; 5618 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; 5619 /* one channel for each analog output channel */ 5620 s->n_chan = board->n_aochan; 5621 s->maxdata = (1 << 16) - 1; 5622 s->range_table = &range_unknown; /* XXX */ 5623 s->insn_read = cs5529_ai_insn_read; 5624 s->insn_config = NULL; 5625 init_cs5529(dev); 5626 } else { 5627 s->type = COMEDI_SUBD_UNUSED; 5628 } 5629 5630 /* Serial */ 5631 s = &dev->subdevices[NI_SERIAL_SUBDEV]; 5632 s->type = COMEDI_SUBD_SERIAL; 5633 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 5634 s->n_chan = 1; 5635 s->maxdata = 0xff; 5636 s->insn_config = ni_serial_insn_config; 5637 devpriv->serial_interval_ns = 0; 5638 devpriv->serial_hw_mode = 0; 5639 5640 /* RTSI */ 5641 s = &dev->subdevices[NI_RTSI_SUBDEV]; 5642 s->type = COMEDI_SUBD_DIO; 5643 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 5644 s->n_chan = 8; 5645 s->maxdata = 1; 5646 s->insn_bits = ni_rtsi_insn_bits; 5647 s->insn_config = ni_rtsi_insn_config; 5648 ni_rtsi_init(dev); 5649 5650 /* allocate and initialize the gpct counter device */ 5651 devpriv->counter_dev = ni_gpct_device_construct(dev, 5652 ni_gpct_write_register, 5653 ni_gpct_read_register, 5654 (devpriv->is_m_series) 5655 ? ni_gpct_variant_m_series 5656 : ni_gpct_variant_e_series, 5657 NUM_GPCT); 5658 if (!devpriv->counter_dev) 5659 return -ENOMEM; 5660 5661 /* Counter (gpct) subdevices */ 5662 for (i = 0; i < NUM_GPCT; ++i) { 5663 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i]; 5664 5665 /* setup and initialize the counter */ 5666 gpct->chip_index = 0; 5667 gpct->counter_index = i; 5668 ni_tio_init_counter(gpct); 5669 5670 s = &dev->subdevices[NI_GPCT_SUBDEV(i)]; 5671 s->type = COMEDI_SUBD_COUNTER; 5672 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL; 5673 s->n_chan = 3; 5674 s->maxdata = (devpriv->is_m_series) ? 0xffffffff 5675 : 0x00ffffff; 5676 s->insn_read = ni_tio_insn_read; 5677 s->insn_write = ni_tio_insn_read; 5678 s->insn_config = ni_tio_insn_config; 5679#ifdef PCIDMA 5680 if (dev->irq && devpriv->mite) { 5681 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */; 5682 s->len_chanlist = 1; 5683 s->do_cmdtest = ni_tio_cmdtest; 5684 s->do_cmd = ni_gpct_cmd; 5685 s->cancel = ni_gpct_cancel; 5686 5687 s->async_dma_dir = DMA_BIDIRECTIONAL; 5688 } 5689#endif 5690 s->private = gpct; 5691 } 5692 5693 /* Frequency output subdevice */ 5694 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV]; 5695 s->type = COMEDI_SUBD_COUNTER; 5696 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 5697 s->n_chan = 1; 5698 s->maxdata = 0xf; 5699 s->insn_read = ni_freq_out_insn_read; 5700 s->insn_write = ni_freq_out_insn_write; 5701 s->insn_config = ni_freq_out_insn_config; 5702 5703 if (dev->irq) { 5704 ni_stc_writew(dev, 5705 (irq_polarity ? Interrupt_Output_Polarity : 0) | 5706 (Interrupt_Output_On_3_Pins & 0) | 5707 Interrupt_A_Enable | Interrupt_B_Enable | 5708 Interrupt_A_Output_Select(interrupt_pin) | 5709 Interrupt_B_Output_Select(interrupt_pin), 5710 Interrupt_Control_Register); 5711 } 5712 5713 /* DMA setup */ 5714 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select); 5715 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select); 5716 5717 if (devpriv->is_6xxx) { 5718 ni_writeb(dev, 0, Magic_611x); 5719 } else if (devpriv->is_m_series) { 5720 int channel; 5721 5722 for (channel = 0; channel < board->n_aochan; ++channel) { 5723 ni_writeb(dev, 0xf, 5724 M_Offset_AO_Waveform_Order(channel)); 5725 ni_writeb(dev, 0x0, 5726 M_Offset_AO_Reference_Attenuation(channel)); 5727 } 5728 ni_writeb(dev, 0x0, M_Offset_AO_Calibration); 5729 } 5730 5731 return 0; 5732} 5733 5734static void mio_common_detach(struct comedi_device *dev) 5735{ 5736 struct ni_private *devpriv = dev->private; 5737 5738 if (devpriv) { 5739 if (devpriv->counter_dev) 5740 ni_gpct_device_destroy(devpriv->counter_dev); 5741 } 5742} 5743