1/* 2 * ADE7758 Poly Phase Multifunction Energy Metering IC driver 3 * 4 * Copyright 2010-2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9#include <linux/interrupt.h> 10#include <linux/irq.h> 11#include <linux/delay.h> 12#include <linux/mutex.h> 13#include <linux/device.h> 14#include <linux/kernel.h> 15#include <linux/spi/spi.h> 16#include <linux/slab.h> 17#include <linux/sysfs.h> 18#include <linux/list.h> 19#include <linux/module.h> 20 21#include <linux/iio/iio.h> 22#include <linux/iio/sysfs.h> 23#include <linux/iio/buffer.h> 24#include "meter.h" 25#include "ade7758.h" 26 27int ade7758_spi_write_reg_8(struct device *dev, 28 u8 reg_address, 29 u8 val) 30{ 31 int ret; 32 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 33 struct ade7758_state *st = iio_priv(indio_dev); 34 35 mutex_lock(&st->buf_lock); 36 st->tx[0] = ADE7758_WRITE_REG(reg_address); 37 st->tx[1] = val; 38 39 ret = spi_write(st->us, st->tx, 2); 40 mutex_unlock(&st->buf_lock); 41 42 return ret; 43} 44 45static int ade7758_spi_write_reg_16(struct device *dev, 46 u8 reg_address, 47 u16 value) 48{ 49 int ret; 50 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 51 struct ade7758_state *st = iio_priv(indio_dev); 52 struct spi_transfer xfers[] = { 53 { 54 .tx_buf = st->tx, 55 .bits_per_word = 8, 56 .len = 3, 57 } 58 }; 59 60 mutex_lock(&st->buf_lock); 61 st->tx[0] = ADE7758_WRITE_REG(reg_address); 62 st->tx[1] = (value >> 8) & 0xFF; 63 st->tx[2] = value & 0xFF; 64 65 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); 66 mutex_unlock(&st->buf_lock); 67 68 return ret; 69} 70 71static int ade7758_spi_write_reg_24(struct device *dev, 72 u8 reg_address, 73 u32 value) 74{ 75 int ret; 76 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 77 struct ade7758_state *st = iio_priv(indio_dev); 78 struct spi_transfer xfers[] = { 79 { 80 .tx_buf = st->tx, 81 .bits_per_word = 8, 82 .len = 4, 83 } 84 }; 85 86 mutex_lock(&st->buf_lock); 87 st->tx[0] = ADE7758_WRITE_REG(reg_address); 88 st->tx[1] = (value >> 16) & 0xFF; 89 st->tx[2] = (value >> 8) & 0xFF; 90 st->tx[3] = value & 0xFF; 91 92 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); 93 mutex_unlock(&st->buf_lock); 94 95 return ret; 96} 97 98int ade7758_spi_read_reg_8(struct device *dev, 99 u8 reg_address, 100 u8 *val) 101{ 102 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 103 struct ade7758_state *st = iio_priv(indio_dev); 104 int ret; 105 struct spi_transfer xfers[] = { 106 { 107 .tx_buf = st->tx, 108 .bits_per_word = 8, 109 .len = 1, 110 .delay_usecs = 4, 111 }, 112 { 113 .tx_buf = &st->tx[1], 114 .rx_buf = st->rx, 115 .bits_per_word = 8, 116 .len = 1, 117 }, 118 }; 119 120 mutex_lock(&st->buf_lock); 121 st->tx[0] = ADE7758_READ_REG(reg_address); 122 st->tx[1] = 0; 123 124 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); 125 if (ret) { 126 dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X", 127 reg_address); 128 goto error_ret; 129 } 130 *val = st->rx[0]; 131 132error_ret: 133 mutex_unlock(&st->buf_lock); 134 return ret; 135} 136 137static int ade7758_spi_read_reg_16(struct device *dev, 138 u8 reg_address, 139 u16 *val) 140{ 141 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 142 struct ade7758_state *st = iio_priv(indio_dev); 143 int ret; 144 struct spi_transfer xfers[] = { 145 { 146 .tx_buf = st->tx, 147 .bits_per_word = 8, 148 .len = 1, 149 .delay_usecs = 4, 150 }, 151 { 152 .tx_buf = &st->tx[1], 153 .rx_buf = st->rx, 154 .bits_per_word = 8, 155 .len = 2, 156 }, 157 }; 158 159 160 mutex_lock(&st->buf_lock); 161 st->tx[0] = ADE7758_READ_REG(reg_address); 162 st->tx[1] = 0; 163 st->tx[2] = 0; 164 165 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); 166 if (ret) { 167 dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X", 168 reg_address); 169 goto error_ret; 170 } 171 172 *val = (st->rx[0] << 8) | st->rx[1]; 173 174error_ret: 175 mutex_unlock(&st->buf_lock); 176 return ret; 177} 178 179static int ade7758_spi_read_reg_24(struct device *dev, 180 u8 reg_address, 181 u32 *val) 182{ 183 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 184 struct ade7758_state *st = iio_priv(indio_dev); 185 int ret; 186 struct spi_transfer xfers[] = { 187 { 188 .tx_buf = st->tx, 189 .bits_per_word = 8, 190 .len = 1, 191 .delay_usecs = 4, 192 }, 193 { 194 .tx_buf = &st->tx[1], 195 .rx_buf = st->rx, 196 .bits_per_word = 8, 197 .len = 3, 198 }, 199 }; 200 201 mutex_lock(&st->buf_lock); 202 st->tx[0] = ADE7758_READ_REG(reg_address); 203 st->tx[1] = 0; 204 st->tx[2] = 0; 205 st->tx[3] = 0; 206 207 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); 208 if (ret) { 209 dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X", 210 reg_address); 211 goto error_ret; 212 } 213 *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2]; 214 215error_ret: 216 mutex_unlock(&st->buf_lock); 217 return ret; 218} 219 220static ssize_t ade7758_read_8bit(struct device *dev, 221 struct device_attribute *attr, 222 char *buf) 223{ 224 int ret; 225 u8 val = 0; 226 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 227 228 ret = ade7758_spi_read_reg_8(dev, this_attr->address, &val); 229 if (ret) 230 return ret; 231 232 return sprintf(buf, "%u\n", val); 233} 234 235static ssize_t ade7758_read_16bit(struct device *dev, 236 struct device_attribute *attr, 237 char *buf) 238{ 239 int ret; 240 u16 val = 0; 241 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 242 243 ret = ade7758_spi_read_reg_16(dev, this_attr->address, &val); 244 if (ret) 245 return ret; 246 247 return sprintf(buf, "%u\n", val); 248} 249 250static ssize_t ade7758_read_24bit(struct device *dev, 251 struct device_attribute *attr, 252 char *buf) 253{ 254 int ret; 255 u32 val = 0; 256 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 257 258 ret = ade7758_spi_read_reg_24(dev, this_attr->address, &val); 259 if (ret) 260 return ret; 261 262 return sprintf(buf, "%u\n", val & 0xFFFFFF); 263} 264 265static ssize_t ade7758_write_8bit(struct device *dev, 266 struct device_attribute *attr, 267 const char *buf, 268 size_t len) 269{ 270 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 271 int ret; 272 u8 val; 273 274 ret = kstrtou8(buf, 10, &val); 275 if (ret) 276 goto error_ret; 277 ret = ade7758_spi_write_reg_8(dev, this_attr->address, val); 278 279error_ret: 280 return ret ? ret : len; 281} 282 283static ssize_t ade7758_write_16bit(struct device *dev, 284 struct device_attribute *attr, 285 const char *buf, 286 size_t len) 287{ 288 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 289 int ret; 290 u16 val; 291 292 ret = kstrtou16(buf, 10, &val); 293 if (ret) 294 goto error_ret; 295 ret = ade7758_spi_write_reg_16(dev, this_attr->address, val); 296 297error_ret: 298 return ret ? ret : len; 299} 300 301static int ade7758_reset(struct device *dev) 302{ 303 int ret; 304 u8 val; 305 306 ade7758_spi_read_reg_8(dev, 307 ADE7758_OPMODE, 308 &val); 309 val |= 1 << 6; /* Software Chip Reset */ 310 ret = ade7758_spi_write_reg_8(dev, 311 ADE7758_OPMODE, 312 val); 313 314 return ret; 315} 316 317static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO, 318 ade7758_read_8bit, 319 ade7758_write_8bit, 320 ADE7758_VPEAK); 321static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO, 322 ade7758_read_8bit, 323 ade7758_write_8bit, 324 ADE7758_VPEAK); 325static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO, 326 ade7758_read_8bit, 327 ade7758_write_8bit, 328 ADE7758_APHCAL); 329static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO, 330 ade7758_read_8bit, 331 ade7758_write_8bit, 332 ADE7758_BPHCAL); 333static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO, 334 ade7758_read_8bit, 335 ade7758_write_8bit, 336 ADE7758_CPHCAL); 337static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO, 338 ade7758_read_8bit, 339 ade7758_write_8bit, 340 ADE7758_WDIV); 341static IIO_DEV_ATTR_VADIV(S_IWUSR | S_IRUGO, 342 ade7758_read_8bit, 343 ade7758_write_8bit, 344 ADE7758_VADIV); 345static IIO_DEV_ATTR_AIRMS(S_IRUGO, 346 ade7758_read_24bit, 347 NULL, 348 ADE7758_AIRMS); 349static IIO_DEV_ATTR_BIRMS(S_IRUGO, 350 ade7758_read_24bit, 351 NULL, 352 ADE7758_BIRMS); 353static IIO_DEV_ATTR_CIRMS(S_IRUGO, 354 ade7758_read_24bit, 355 NULL, 356 ADE7758_CIRMS); 357static IIO_DEV_ATTR_AVRMS(S_IRUGO, 358 ade7758_read_24bit, 359 NULL, 360 ADE7758_AVRMS); 361static IIO_DEV_ATTR_BVRMS(S_IRUGO, 362 ade7758_read_24bit, 363 NULL, 364 ADE7758_BVRMS); 365static IIO_DEV_ATTR_CVRMS(S_IRUGO, 366 ade7758_read_24bit, 367 NULL, 368 ADE7758_CVRMS); 369static IIO_DEV_ATTR_AIRMSOS(S_IWUSR | S_IRUGO, 370 ade7758_read_16bit, 371 ade7758_write_16bit, 372 ADE7758_AIRMSOS); 373static IIO_DEV_ATTR_BIRMSOS(S_IWUSR | S_IRUGO, 374 ade7758_read_16bit, 375 ade7758_write_16bit, 376 ADE7758_BIRMSOS); 377static IIO_DEV_ATTR_CIRMSOS(S_IWUSR | S_IRUGO, 378 ade7758_read_16bit, 379 ade7758_write_16bit, 380 ADE7758_CIRMSOS); 381static IIO_DEV_ATTR_AVRMSOS(S_IWUSR | S_IRUGO, 382 ade7758_read_16bit, 383 ade7758_write_16bit, 384 ADE7758_AVRMSOS); 385static IIO_DEV_ATTR_BVRMSOS(S_IWUSR | S_IRUGO, 386 ade7758_read_16bit, 387 ade7758_write_16bit, 388 ADE7758_BVRMSOS); 389static IIO_DEV_ATTR_CVRMSOS(S_IWUSR | S_IRUGO, 390 ade7758_read_16bit, 391 ade7758_write_16bit, 392 ADE7758_CVRMSOS); 393static IIO_DEV_ATTR_AIGAIN(S_IWUSR | S_IRUGO, 394 ade7758_read_16bit, 395 ade7758_write_16bit, 396 ADE7758_AIGAIN); 397static IIO_DEV_ATTR_BIGAIN(S_IWUSR | S_IRUGO, 398 ade7758_read_16bit, 399 ade7758_write_16bit, 400 ADE7758_BIGAIN); 401static IIO_DEV_ATTR_CIGAIN(S_IWUSR | S_IRUGO, 402 ade7758_read_16bit, 403 ade7758_write_16bit, 404 ADE7758_CIGAIN); 405static IIO_DEV_ATTR_AVRMSGAIN(S_IWUSR | S_IRUGO, 406 ade7758_read_16bit, 407 ade7758_write_16bit, 408 ADE7758_AVRMSGAIN); 409static IIO_DEV_ATTR_BVRMSGAIN(S_IWUSR | S_IRUGO, 410 ade7758_read_16bit, 411 ade7758_write_16bit, 412 ADE7758_BVRMSGAIN); 413static IIO_DEV_ATTR_CVRMSGAIN(S_IWUSR | S_IRUGO, 414 ade7758_read_16bit, 415 ade7758_write_16bit, 416 ADE7758_CVRMSGAIN); 417 418int ade7758_set_irq(struct device *dev, bool enable) 419{ 420 int ret; 421 u32 irqen; 422 423 ret = ade7758_spi_read_reg_24(dev, ADE7758_MASK, &irqen); 424 if (ret) 425 goto error_ret; 426 427 if (enable) 428 irqen |= 1 << 16; /* Enables an interrupt when a data is 429 present in the waveform register */ 430 else 431 irqen &= ~(1 << 16); 432 433 ret = ade7758_spi_write_reg_24(dev, ADE7758_MASK, irqen); 434 if (ret) 435 goto error_ret; 436 437error_ret: 438 return ret; 439} 440 441/* Power down the device */ 442static int ade7758_stop_device(struct device *dev) 443{ 444 int ret; 445 u8 val; 446 447 ade7758_spi_read_reg_8(dev, 448 ADE7758_OPMODE, 449 &val); 450 val |= 7 << 3; /* ADE7758 powered down */ 451 ret = ade7758_spi_write_reg_8(dev, 452 ADE7758_OPMODE, 453 val); 454 455 return ret; 456} 457 458static int ade7758_initial_setup(struct iio_dev *indio_dev) 459{ 460 struct ade7758_state *st = iio_priv(indio_dev); 461 struct device *dev = &indio_dev->dev; 462 int ret; 463 464 /* use low spi speed for init */ 465 st->us->mode = SPI_MODE_1; 466 spi_setup(st->us); 467 468 /* Disable IRQ */ 469 ret = ade7758_set_irq(dev, false); 470 if (ret) { 471 dev_err(dev, "disable irq failed"); 472 goto err_ret; 473 } 474 475 ade7758_reset(dev); 476 msleep(ADE7758_STARTUP_DELAY); 477 478err_ret: 479 return ret; 480} 481 482static ssize_t ade7758_read_frequency(struct device *dev, 483 struct device_attribute *attr, 484 char *buf) 485{ 486 int ret, len = 0; 487 u8 t; 488 int sps; 489 490 ret = ade7758_spi_read_reg_8(dev, 491 ADE7758_WAVMODE, 492 &t); 493 if (ret) 494 return ret; 495 496 t = (t >> 5) & 0x3; 497 sps = 26040 / (1 << t); 498 499 len = sprintf(buf, "%d SPS\n", sps); 500 return len; 501} 502 503static ssize_t ade7758_write_frequency(struct device *dev, 504 struct device_attribute *attr, 505 const char *buf, 506 size_t len) 507{ 508 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 509 u16 val; 510 int ret; 511 u8 reg, t; 512 513 ret = kstrtou16(buf, 10, &val); 514 if (ret) 515 return ret; 516 517 mutex_lock(&indio_dev->mlock); 518 519 switch (val) { 520 case 26040: 521 t = 0; 522 break; 523 case 13020: 524 t = 1; 525 break; 526 case 6510: 527 t = 2; 528 break; 529 case 3255: 530 t = 3; 531 break; 532 default: 533 ret = -EINVAL; 534 goto out; 535 } 536 537 ret = ade7758_spi_read_reg_8(dev, 538 ADE7758_WAVMODE, 539 ®); 540 if (ret) 541 goto out; 542 543 reg &= ~(5 << 3); 544 reg |= t << 5; 545 546 ret = ade7758_spi_write_reg_8(dev, 547 ADE7758_WAVMODE, 548 reg); 549 550out: 551 mutex_unlock(&indio_dev->mlock); 552 553 return ret ? ret : len; 554} 555 556static IIO_DEV_ATTR_TEMP_RAW(ade7758_read_8bit); 557static IIO_CONST_ATTR(in_temp_offset, "129 C"); 558static IIO_CONST_ATTR(in_temp_scale, "4 C"); 559 560static IIO_DEV_ATTR_AWATTHR(ade7758_read_16bit, 561 ADE7758_AWATTHR); 562static IIO_DEV_ATTR_BWATTHR(ade7758_read_16bit, 563 ADE7758_BWATTHR); 564static IIO_DEV_ATTR_CWATTHR(ade7758_read_16bit, 565 ADE7758_CWATTHR); 566static IIO_DEV_ATTR_AVARHR(ade7758_read_16bit, 567 ADE7758_AVARHR); 568static IIO_DEV_ATTR_BVARHR(ade7758_read_16bit, 569 ADE7758_BVARHR); 570static IIO_DEV_ATTR_CVARHR(ade7758_read_16bit, 571 ADE7758_CVARHR); 572static IIO_DEV_ATTR_AVAHR(ade7758_read_16bit, 573 ADE7758_AVAHR); 574static IIO_DEV_ATTR_BVAHR(ade7758_read_16bit, 575 ADE7758_BVAHR); 576static IIO_DEV_ATTR_CVAHR(ade7758_read_16bit, 577 ADE7758_CVAHR); 578 579static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, 580 ade7758_read_frequency, 581 ade7758_write_frequency); 582 583static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26040 13020 6510 3255"); 584 585static struct attribute *ade7758_attributes[] = { 586 &iio_dev_attr_in_temp_raw.dev_attr.attr, 587 &iio_const_attr_in_temp_offset.dev_attr.attr, 588 &iio_const_attr_in_temp_scale.dev_attr.attr, 589 &iio_dev_attr_sampling_frequency.dev_attr.attr, 590 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 591 &iio_dev_attr_awatthr.dev_attr.attr, 592 &iio_dev_attr_bwatthr.dev_attr.attr, 593 &iio_dev_attr_cwatthr.dev_attr.attr, 594 &iio_dev_attr_avarhr.dev_attr.attr, 595 &iio_dev_attr_bvarhr.dev_attr.attr, 596 &iio_dev_attr_cvarhr.dev_attr.attr, 597 &iio_dev_attr_avahr.dev_attr.attr, 598 &iio_dev_attr_bvahr.dev_attr.attr, 599 &iio_dev_attr_cvahr.dev_attr.attr, 600 &iio_dev_attr_vpeak.dev_attr.attr, 601 &iio_dev_attr_ipeak.dev_attr.attr, 602 &iio_dev_attr_aphcal.dev_attr.attr, 603 &iio_dev_attr_bphcal.dev_attr.attr, 604 &iio_dev_attr_cphcal.dev_attr.attr, 605 &iio_dev_attr_wdiv.dev_attr.attr, 606 &iio_dev_attr_vadiv.dev_attr.attr, 607 &iio_dev_attr_airms.dev_attr.attr, 608 &iio_dev_attr_birms.dev_attr.attr, 609 &iio_dev_attr_cirms.dev_attr.attr, 610 &iio_dev_attr_avrms.dev_attr.attr, 611 &iio_dev_attr_bvrms.dev_attr.attr, 612 &iio_dev_attr_cvrms.dev_attr.attr, 613 &iio_dev_attr_aigain.dev_attr.attr, 614 &iio_dev_attr_bigain.dev_attr.attr, 615 &iio_dev_attr_cigain.dev_attr.attr, 616 &iio_dev_attr_avrmsgain.dev_attr.attr, 617 &iio_dev_attr_bvrmsgain.dev_attr.attr, 618 &iio_dev_attr_cvrmsgain.dev_attr.attr, 619 &iio_dev_attr_airmsos.dev_attr.attr, 620 &iio_dev_attr_birmsos.dev_attr.attr, 621 &iio_dev_attr_cirmsos.dev_attr.attr, 622 &iio_dev_attr_avrmsos.dev_attr.attr, 623 &iio_dev_attr_bvrmsos.dev_attr.attr, 624 &iio_dev_attr_cvrmsos.dev_attr.attr, 625 NULL, 626}; 627 628static const struct attribute_group ade7758_attribute_group = { 629 .attrs = ade7758_attributes, 630}; 631 632static const struct iio_chan_spec ade7758_channels[] = { 633 { 634 .type = IIO_VOLTAGE, 635 .indexed = 1, 636 .channel = 0, 637 .address = AD7758_WT(AD7758_PHASE_A, AD7758_VOLTAGE), 638 .scan_index = 0, 639 .scan_type = { 640 .sign = 's', 641 .realbits = 24, 642 .storagebits = 32, 643 }, 644 }, { 645 .type = IIO_CURRENT, 646 .indexed = 1, 647 .channel = 0, 648 .address = AD7758_WT(AD7758_PHASE_A, AD7758_CURRENT), 649 .scan_index = 1, 650 .scan_type = { 651 .sign = 's', 652 .realbits = 24, 653 .storagebits = 32, 654 }, 655 }, { 656 .type = IIO_POWER, 657 .indexed = 1, 658 .channel = 0, 659 .extend_name = "apparent", 660 .address = AD7758_WT(AD7758_PHASE_A, AD7758_APP_PWR), 661 .scan_index = 2, 662 .scan_type = { 663 .sign = 's', 664 .realbits = 24, 665 .storagebits = 32, 666 }, 667 }, { 668 .type = IIO_POWER, 669 .indexed = 1, 670 .channel = 0, 671 .extend_name = "active", 672 .address = AD7758_WT(AD7758_PHASE_A, AD7758_ACT_PWR), 673 .scan_index = 3, 674 .scan_type = { 675 .sign = 's', 676 .realbits = 24, 677 .storagebits = 32, 678 }, 679 }, { 680 .type = IIO_POWER, 681 .indexed = 1, 682 .channel = 0, 683 .extend_name = "reactive", 684 .address = AD7758_WT(AD7758_PHASE_A, AD7758_REACT_PWR), 685 .scan_index = 4, 686 .scan_type = { 687 .sign = 's', 688 .realbits = 24, 689 .storagebits = 32, 690 }, 691 }, { 692 .type = IIO_VOLTAGE, 693 .indexed = 1, 694 .channel = 1, 695 .address = AD7758_WT(AD7758_PHASE_B, AD7758_VOLTAGE), 696 .scan_index = 5, 697 .scan_type = { 698 .sign = 's', 699 .realbits = 24, 700 .storagebits = 32, 701 }, 702 }, { 703 .type = IIO_CURRENT, 704 .indexed = 1, 705 .channel = 1, 706 .address = AD7758_WT(AD7758_PHASE_B, AD7758_CURRENT), 707 .scan_index = 6, 708 .scan_type = { 709 .sign = 's', 710 .realbits = 24, 711 .storagebits = 32, 712 }, 713 }, { 714 .type = IIO_POWER, 715 .indexed = 1, 716 .channel = 1, 717 .extend_name = "apparent", 718 .address = AD7758_WT(AD7758_PHASE_B, AD7758_APP_PWR), 719 .scan_index = 7, 720 .scan_type = { 721 .sign = 's', 722 .realbits = 24, 723 .storagebits = 32, 724 }, 725 }, { 726 .type = IIO_POWER, 727 .indexed = 1, 728 .channel = 1, 729 .extend_name = "active", 730 .address = AD7758_WT(AD7758_PHASE_B, AD7758_ACT_PWR), 731 .scan_index = 8, 732 .scan_type = { 733 .sign = 's', 734 .realbits = 24, 735 .storagebits = 32, 736 }, 737 }, { 738 .type = IIO_POWER, 739 .indexed = 1, 740 .channel = 1, 741 .extend_name = "reactive", 742 .address = AD7758_WT(AD7758_PHASE_B, AD7758_REACT_PWR), 743 .scan_index = 9, 744 .scan_type = { 745 .sign = 's', 746 .realbits = 24, 747 .storagebits = 32, 748 }, 749 }, { 750 .type = IIO_VOLTAGE, 751 .indexed = 1, 752 .channel = 2, 753 .address = AD7758_WT(AD7758_PHASE_C, AD7758_VOLTAGE), 754 .scan_index = 10, 755 .scan_type = { 756 .sign = 's', 757 .realbits = 24, 758 .storagebits = 32, 759 }, 760 }, { 761 .type = IIO_CURRENT, 762 .indexed = 1, 763 .channel = 2, 764 .address = AD7758_WT(AD7758_PHASE_C, AD7758_CURRENT), 765 .scan_index = 11, 766 .scan_type = { 767 .sign = 's', 768 .realbits = 24, 769 .storagebits = 32, 770 }, 771 }, { 772 .type = IIO_POWER, 773 .indexed = 1, 774 .channel = 2, 775 .extend_name = "apparent", 776 .address = AD7758_WT(AD7758_PHASE_C, AD7758_APP_PWR), 777 .scan_index = 12, 778 .scan_type = { 779 .sign = 's', 780 .realbits = 24, 781 .storagebits = 32, 782 }, 783 }, { 784 .type = IIO_POWER, 785 .indexed = 1, 786 .channel = 2, 787 .extend_name = "active", 788 .address = AD7758_WT(AD7758_PHASE_C, AD7758_ACT_PWR), 789 .scan_index = 13, 790 .scan_type = { 791 .sign = 's', 792 .realbits = 24, 793 .storagebits = 32, 794 }, 795 }, { 796 .type = IIO_POWER, 797 .indexed = 1, 798 .channel = 2, 799 .extend_name = "reactive", 800 .address = AD7758_WT(AD7758_PHASE_C, AD7758_REACT_PWR), 801 .scan_index = 14, 802 .scan_type = { 803 .sign = 's', 804 .realbits = 24, 805 .storagebits = 32, 806 }, 807 }, 808 IIO_CHAN_SOFT_TIMESTAMP(15), 809}; 810 811static const struct iio_info ade7758_info = { 812 .attrs = &ade7758_attribute_group, 813 .driver_module = THIS_MODULE, 814}; 815 816static int ade7758_probe(struct spi_device *spi) 817{ 818 int ret; 819 struct ade7758_state *st; 820 struct iio_dev *indio_dev; 821 822 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 823 if (!indio_dev) 824 return -ENOMEM; 825 826 st = iio_priv(indio_dev); 827 /* this is only used for removal purposes */ 828 spi_set_drvdata(spi, indio_dev); 829 830 /* Allocate the comms buffers */ 831 st->rx = kcalloc(ADE7758_MAX_RX, sizeof(*st->rx), GFP_KERNEL); 832 if (!st->rx) 833 return -ENOMEM; 834 st->tx = kcalloc(ADE7758_MAX_TX, sizeof(*st->tx), GFP_KERNEL); 835 if (st->tx == NULL) { 836 ret = -ENOMEM; 837 goto error_free_rx; 838 } 839 st->us = spi; 840 mutex_init(&st->buf_lock); 841 842 indio_dev->name = spi->dev.driver->name; 843 indio_dev->dev.parent = &spi->dev; 844 indio_dev->info = &ade7758_info; 845 indio_dev->modes = INDIO_DIRECT_MODE; 846 indio_dev->channels = ade7758_channels; 847 indio_dev->num_channels = ARRAY_SIZE(ade7758_channels); 848 849 ret = ade7758_configure_ring(indio_dev); 850 if (ret) 851 goto error_free_tx; 852 853 ret = iio_buffer_register(indio_dev, 854 &ade7758_channels[0], 855 ARRAY_SIZE(ade7758_channels)); 856 if (ret) { 857 dev_err(&spi->dev, "failed to initialize the ring\n"); 858 goto error_unreg_ring_funcs; 859 } 860 861 /* Get the device into a sane initial state */ 862 ret = ade7758_initial_setup(indio_dev); 863 if (ret) 864 goto error_uninitialize_ring; 865 866 if (spi->irq) { 867 ret = ade7758_probe_trigger(indio_dev); 868 if (ret) 869 goto error_uninitialize_ring; 870 } 871 872 ret = iio_device_register(indio_dev); 873 if (ret) 874 goto error_remove_trigger; 875 876 return 0; 877 878error_remove_trigger: 879 if (spi->irq) 880 ade7758_remove_trigger(indio_dev); 881error_uninitialize_ring: 882 ade7758_uninitialize_ring(indio_dev); 883error_unreg_ring_funcs: 884 ade7758_unconfigure_ring(indio_dev); 885error_free_tx: 886 kfree(st->tx); 887error_free_rx: 888 kfree(st->rx); 889 return ret; 890} 891 892static int ade7758_remove(struct spi_device *spi) 893{ 894 struct iio_dev *indio_dev = spi_get_drvdata(spi); 895 struct ade7758_state *st = iio_priv(indio_dev); 896 897 iio_device_unregister(indio_dev); 898 ade7758_stop_device(&indio_dev->dev); 899 ade7758_remove_trigger(indio_dev); 900 ade7758_uninitialize_ring(indio_dev); 901 ade7758_unconfigure_ring(indio_dev); 902 kfree(st->tx); 903 kfree(st->rx); 904 905 return 0; 906} 907 908static const struct spi_device_id ade7758_id[] = { 909 {"ade7758", 0}, 910 {} 911}; 912MODULE_DEVICE_TABLE(spi, ade7758_id); 913 914static struct spi_driver ade7758_driver = { 915 .driver = { 916 .name = "ade7758", 917 .owner = THIS_MODULE, 918 }, 919 .probe = ade7758_probe, 920 .remove = ade7758_remove, 921 .id_table = ade7758_id, 922}; 923module_spi_driver(ade7758_driver); 924 925MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); 926MODULE_DESCRIPTION("Analog Devices ADE7758 Polyphase Multifunction Energy Metering IC Driver"); 927MODULE_LICENSE("GPL v2"); 928