1/* 2 * Octeon HCD hardware register definitions. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Some parts of the code were originally released under BSD license: 9 * 10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 11 * reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions are 15 * met: 16 * 17 * * Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 20 * * Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials provided 23 * with the distribution. 24 * 25 * * Neither the name of Cavium Networks nor the names of 26 * its contributors may be used to endorse or promote products 27 * derived from this software without specific prior written 28 * permission. 29 * 30 * This Software, including technical data, may be subject to U.S. export 31 * control laws, including the U.S. Export Administration Act and its associated 32 * regulations, and may be subject to export or import regulations in other 33 * countries. 34 * 35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION 39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 45 */ 46 47#ifndef __OCTEON_HCD_H__ 48#define __OCTEON_HCD_H__ 49 50#define CVMX_USBCXBASE 0x00016F0010000000ull 51#define CVMX_USBCXREG1(reg, bid) \ 52 (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ 53 ((bid) & 1) * 0x100000000000ull) 54#define CVMX_USBCXREG2(reg, bid, off) \ 55 (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ 56 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32) 57 58#define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid) 59#define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid) 60#define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid) 61#define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid) 62#define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid) 63#define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid) 64#define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid) 65#define CVMX_USBCX_GRSTCTL(bid) CVMX_USBCXREG1(0x010, bid) 66#define CVMX_USBCX_GRXFSIZ(bid) CVMX_USBCXREG1(0x024, bid) 67#define CVMX_USBCX_GRXSTSPH(bid) CVMX_USBCXREG1(0x020, bid) 68#define CVMX_USBCX_GUSBCFG(bid) CVMX_USBCXREG1(0x00c, bid) 69#define CVMX_USBCX_HAINT(bid) CVMX_USBCXREG1(0x414, bid) 70#define CVMX_USBCX_HAINTMSK(bid) CVMX_USBCXREG1(0x418, bid) 71#define CVMX_USBCX_HCCHARX(off, bid) CVMX_USBCXREG2(0x500, bid, off) 72#define CVMX_USBCX_HCFG(bid) CVMX_USBCXREG1(0x400, bid) 73#define CVMX_USBCX_HCINTMSKX(off, bid) CVMX_USBCXREG2(0x50c, bid, off) 74#define CVMX_USBCX_HCINTX(off, bid) CVMX_USBCXREG2(0x508, bid, off) 75#define CVMX_USBCX_HCSPLTX(off, bid) CVMX_USBCXREG2(0x504, bid, off) 76#define CVMX_USBCX_HCTSIZX(off, bid) CVMX_USBCXREG2(0x510, bid, off) 77#define CVMX_USBCX_HFIR(bid) CVMX_USBCXREG1(0x404, bid) 78#define CVMX_USBCX_HFNUM(bid) CVMX_USBCXREG1(0x408, bid) 79#define CVMX_USBCX_HPRT(bid) CVMX_USBCXREG1(0x440, bid) 80#define CVMX_USBCX_HPTXFSIZ(bid) CVMX_USBCXREG1(0x100, bid) 81#define CVMX_USBCX_HPTXSTS(bid) CVMX_USBCXREG1(0x410, bid) 82 83#define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull) 84#define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull) 85 86#define CVMX_USBNXREG1(reg, bid) \ 87 (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid)) 88#define CVMX_USBNXREG2(reg, bid) \ 89 (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid)) 90 91#define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid) 92#define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid) 93#define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid) 94#define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid) 95 96/** 97 * cvmx_usbc#_gahbcfg 98 * 99 * Core AHB Configuration Register (GAHBCFG) 100 * 101 * This register can be used to configure the core after power-on or a change in 102 * mode of operation. This register mainly contains AHB system-related 103 * configuration parameters. The AHB is the processor interface to the O2P USB 104 * core. In general, software need not know about this interface except to 105 * program the values as specified. 106 * 107 * The application must program this register as part of the O2P USB core 108 * initialization. Do not change this register after the initial programming. 109 */ 110union cvmx_usbcx_gahbcfg { 111 uint32_t u32; 112 /** 113 * struct cvmx_usbcx_gahbcfg_s 114 * @ptxfemplvl: Periodic TxFIFO Empty Level (PTxFEmpLvl) 115 * Software should set this bit to 0x1. 116 * Indicates when the Periodic TxFIFO Empty Interrupt bit in the 117 * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This 118 * bit is used only in Slave mode. 119 * * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic 120 * TxFIFO is half empty 121 * * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic 122 * TxFIFO is completely empty 123 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) 124 * Software should set this bit to 0x1. 125 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in 126 * the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. 127 * This bit is used only in Slave mode. 128 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non- 129 * Periodic TxFIFO is half empty 130 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non- 131 * Periodic TxFIFO is completely empty 132 * @dmaen: DMA Enable (DMAEn) 133 * * 1'b0: Core operates in Slave mode 134 * * 1'b1: Core operates in a DMA mode 135 * @hbstlen: Burst Length/Type (HBstLen) 136 * This field has not effect and should be left as 0x0. 137 * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk) 138 * Software should set this field to 0x1. 139 * The application uses this bit to mask or unmask the interrupt 140 * line assertion to itself. Irrespective of this bit's setting, 141 * the interrupt status registers are updated by the core. 142 * * 1'b0: Mask the interrupt assertion to the application. 143 * * 1'b1: Unmask the interrupt assertion to the application. 144 */ 145 struct cvmx_usbcx_gahbcfg_s { 146 uint32_t reserved_9_31 : 23; 147 uint32_t ptxfemplvl : 1; 148 uint32_t nptxfemplvl : 1; 149 uint32_t reserved_6_6 : 1; 150 uint32_t dmaen : 1; 151 uint32_t hbstlen : 4; 152 uint32_t glblintrmsk : 1; 153 } s; 154}; 155 156/** 157 * cvmx_usbc#_ghwcfg3 158 * 159 * User HW Config3 Register (GHWCFG3) 160 * 161 * This register contains the configuration options of the O2P USB core. 162 */ 163union cvmx_usbcx_ghwcfg3 { 164 uint32_t u32; 165 /** 166 * struct cvmx_usbcx_ghwcfg3_s 167 * @dfifodepth: DFIFO Depth (DfifoDepth) 168 * This value is in terms of 32-bit words. 169 * * Minimum value is 32 170 * * Maximum value is 32768 171 * @ahbphysync: AHB and PHY Synchronous (AhbPhySync) 172 * Indicates whether AHB and PHY clocks are synchronous to 173 * each other. 174 * * 1'b0: No 175 * * 1'b1: Yes 176 * This bit is tied to 1. 177 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType) 178 * * 1'b0: Asynchronous reset is used in the core 179 * * 1'b1: Synchronous reset is used in the core 180 * @optfeature: Optional Features Removed (OptFeature) 181 * Indicates whether the User ID register, GPIO interface ports, 182 * and SOF toggle and counter ports were removed for gate count 183 * optimization. 184 * @vendor_control_interface_support: Vendor Control Interface Support 185 * * 1'b0: Vendor Control Interface is not available on the core. 186 * * 1'b1: Vendor Control Interface is available. 187 * @i2c_selection: I2C Selection 188 * * 1'b0: I2C Interface is not available on the core. 189 * * 1'b1: I2C Interface is available on the core. 190 * @otgen: OTG Function Enabled (OtgEn) 191 * The application uses this bit to indicate the O2P USB core's 192 * OTG capabilities. 193 * * 1'b0: Not OTG capable 194 * * 1'b1: OTG Capable 195 * @pktsizewidth: Width of Packet Size Counters (PktSizeWidth) 196 * * 3'b000: 4 bits 197 * * 3'b001: 5 bits 198 * * 3'b010: 6 bits 199 * * 3'b011: 7 bits 200 * * 3'b100: 8 bits 201 * * 3'b101: 9 bits 202 * * 3'b110: 10 bits 203 * * Others: Reserved 204 * @xfersizewidth: Width of Transfer Size Counters (XferSizeWidth) 205 * * 4'b0000: 11 bits 206 * * 4'b0001: 12 bits 207 * - ... 208 * * 4'b1000: 19 bits 209 * * Others: Reserved 210 */ 211 struct cvmx_usbcx_ghwcfg3_s { 212 uint32_t dfifodepth : 16; 213 uint32_t reserved_13_15 : 3; 214 uint32_t ahbphysync : 1; 215 uint32_t rsttype : 1; 216 uint32_t optfeature : 1; 217 uint32_t vendor_control_interface_support : 1; 218 uint32_t i2c_selection : 1; 219 uint32_t otgen : 1; 220 uint32_t pktsizewidth : 3; 221 uint32_t xfersizewidth : 4; 222 } s; 223}; 224 225/** 226 * cvmx_usbc#_gintmsk 227 * 228 * Core Interrupt Mask Register (GINTMSK) 229 * 230 * This register works with the Core Interrupt register to interrupt the 231 * application. When an interrupt bit is masked, the interrupt associated with 232 * that bit will not be generated. However, the Core Interrupt (GINTSTS) 233 * register bit corresponding to that interrupt will still be set. 234 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1 235 */ 236union cvmx_usbcx_gintmsk { 237 uint32_t u32; 238 /** 239 * struct cvmx_usbcx_gintmsk_s 240 * @wkupintmsk: Resume/Remote Wakeup Detected Interrupt Mask 241 * (WkUpIntMsk) 242 * @sessreqintmsk: Session Request/New Session Detected Interrupt Mask 243 * (SessReqIntMsk) 244 * @disconnintmsk: Disconnect Detected Interrupt Mask (DisconnIntMsk) 245 * @conidstschngmsk: Connector ID Status Change Mask (ConIDStsChngMsk) 246 * @ptxfempmsk: Periodic TxFIFO Empty Mask (PTxFEmpMsk) 247 * @hchintmsk: Host Channels Interrupt Mask (HChIntMsk) 248 * @prtintmsk: Host Port Interrupt Mask (PrtIntMsk) 249 * @fetsuspmsk: Data Fetch Suspended Mask (FetSuspMsk) 250 * @incomplpmsk: Incomplete Periodic Transfer Mask (incomplPMsk) 251 * Incomplete Isochronous OUT Transfer Mask 252 * (incompISOOUTMsk) 253 * @incompisoinmsk: Incomplete Isochronous IN Transfer Mask 254 * (incompISOINMsk) 255 * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk) 256 * @inepintmsk: IN Endpoints Interrupt Mask (INEPIntMsk) 257 * @epmismsk: Endpoint Mismatch Interrupt Mask (EPMisMsk) 258 * @eopfmsk: End of Periodic Frame Interrupt Mask (EOPFMsk) 259 * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask 260 * (ISOOutDropMsk) 261 * @enumdonemsk: Enumeration Done Mask (EnumDoneMsk) 262 * @usbrstmsk: USB Reset Mask (USBRstMsk) 263 * @usbsuspmsk: USB Suspend Mask (USBSuspMsk) 264 * @erlysuspmsk: Early Suspend Mask (ErlySuspMsk) 265 * @i2cint: I2C Interrupt Mask (I2CINT) 266 * @ulpickintmsk: ULPI Carkit Interrupt Mask (ULPICKINTMsk) 267 * I2C Carkit Interrupt Mask (I2CCKINTMsk) 268 * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk) 269 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask 270 * (GINNakEffMsk) 271 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) 272 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk) 273 * @sofmsk: Start of (micro)Frame Mask (SofMsk) 274 * @otgintmsk: OTG Interrupt Mask (OTGIntMsk) 275 * @modemismsk: Mode Mismatch Interrupt Mask (ModeMisMsk) 276 */ 277 struct cvmx_usbcx_gintmsk_s { 278 uint32_t wkupintmsk : 1; 279 uint32_t sessreqintmsk : 1; 280 uint32_t disconnintmsk : 1; 281 uint32_t conidstschngmsk : 1; 282 uint32_t reserved_27_27 : 1; 283 uint32_t ptxfempmsk : 1; 284 uint32_t hchintmsk : 1; 285 uint32_t prtintmsk : 1; 286 uint32_t reserved_23_23 : 1; 287 uint32_t fetsuspmsk : 1; 288 uint32_t incomplpmsk : 1; 289 uint32_t incompisoinmsk : 1; 290 uint32_t oepintmsk : 1; 291 uint32_t inepintmsk : 1; 292 uint32_t epmismsk : 1; 293 uint32_t reserved_16_16 : 1; 294 uint32_t eopfmsk : 1; 295 uint32_t isooutdropmsk : 1; 296 uint32_t enumdonemsk : 1; 297 uint32_t usbrstmsk : 1; 298 uint32_t usbsuspmsk : 1; 299 uint32_t erlysuspmsk : 1; 300 uint32_t i2cint : 1; 301 uint32_t ulpickintmsk : 1; 302 uint32_t goutnakeffmsk : 1; 303 uint32_t ginnakeffmsk : 1; 304 uint32_t nptxfempmsk : 1; 305 uint32_t rxflvlmsk : 1; 306 uint32_t sofmsk : 1; 307 uint32_t otgintmsk : 1; 308 uint32_t modemismsk : 1; 309 uint32_t reserved_0_0 : 1; 310 } s; 311}; 312 313/** 314 * cvmx_usbc#_gintsts 315 * 316 * Core Interrupt Register (GINTSTS) 317 * 318 * This register interrupts the application for system-level events in the 319 * current mode of operation (Device mode or Host mode). It is shown in 320 * Interrupt. Some of the bits in this register are valid only in Host mode, 321 * while others are valid in Device mode only. This register also indicates the 322 * current mode of operation. In order to clear the interrupt status bits of 323 * type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status 324 * interrupts are read only; once software reads from or writes to the FIFO 325 * while servicing these interrupts, FIFO interrupt conditions are cleared 326 * automatically. 327 */ 328union cvmx_usbcx_gintsts { 329 uint32_t u32; 330 /** 331 * struct cvmx_usbcx_gintsts_s 332 * @wkupint: Resume/Remote Wakeup Detected Interrupt (WkUpInt) 333 * In Device mode, this interrupt is asserted when a resume is 334 * detected on the USB. In Host mode, this interrupt is asserted 335 * when a remote wakeup is detected on the USB. 336 * For more information on how to use this interrupt, see "Partial 337 * Power-Down and Clock Gating Programming Model" on 338 * page 353. 339 * @sessreqint: Session Request/New Session Detected Interrupt 340 * (SessReqInt) 341 * In Host mode, this interrupt is asserted when a session request 342 * is detected from the device. In Device mode, this interrupt is 343 * asserted when the utmiotg_bvalid signal goes high. 344 * For more information on how to use this interrupt, see "Partial 345 * Power-Down and Clock Gating Programming Model" on 346 * page 353. 347 * @disconnint: Disconnect Detected Interrupt (DisconnInt) 348 * Asserted when a device disconnect is detected. 349 * @conidstschng: Connector ID Status Change (ConIDStsChng) 350 * The core sets this bit when there is a change in connector ID 351 * status. 352 * @ptxfemp: Periodic TxFIFO Empty (PTxFEmp) 353 * Asserted when the Periodic Transmit FIFO is either half or 354 * completely empty and there is space for at least one entry to be 355 * written in the Periodic Request Queue. The half or completely 356 * empty status is determined by the Periodic TxFIFO Empty Level 357 * bit in the Core AHB Configuration register 358 * (GAHBCFG.PTxFEmpLvl). 359 * @hchint: Host Channels Interrupt (HChInt) 360 * The core sets this bit to indicate that an interrupt is pending 361 * on one of the channels of the core (in Host mode). The 362 * application must read the Host All Channels Interrupt (HAINT) 363 * register to determine the exact number of the channel on which 364 * the interrupt occurred, and then read the corresponding Host 365 * Channel-n Interrupt (HCINTn) register to determine the exact 366 * cause of the interrupt. The application must clear the 367 * appropriate status bit in the HCINTn register to clear this bit. 368 * @prtint: Host Port Interrupt (PrtInt) 369 * The core sets this bit to indicate a change in port status of 370 * one of the O2P USB core ports in Host mode. The application must 371 * read the Host Port Control and Status (HPRT) register to 372 * determine the exact event that caused this interrupt. The 373 * application must clear the appropriate status bit in the Host 374 * Port Control and Status register to clear this bit. 375 * @fetsusp: Data Fetch Suspended (FetSusp) 376 * This interrupt is valid only in DMA mode. This interrupt 377 * indicates that the core has stopped fetching data for IN 378 * endpoints due to the unavailability of TxFIFO space or Request 379 * Queue space. This interrupt is used by the application for an 380 * endpoint mismatch algorithm. 381 * @incomplp: Incomplete Periodic Transfer (incomplP) 382 * In Host mode, the core sets this interrupt bit when there are 383 * incomplete periodic transactions still pending which are 384 * scheduled for the current microframe. 385 * Incomplete Isochronous OUT Transfer (incompISOOUT) 386 * The Device mode, the core sets this interrupt to indicate that 387 * there is at least one isochronous OUT endpoint on which the 388 * transfer is not completed in the current microframe. This 389 * interrupt is asserted along with the End of Periodic Frame 390 * Interrupt (EOPF) bit in this register. 391 * @incompisoin: Incomplete Isochronous IN Transfer (incompISOIN) 392 * The core sets this interrupt to indicate that there is at least 393 * one isochronous IN endpoint on which the transfer is not 394 * completed in the current microframe. This interrupt is asserted 395 * along with the End of Periodic Frame Interrupt (EOPF) bit in 396 * this register. 397 * @oepint: OUT Endpoints Interrupt (OEPInt) 398 * The core sets this bit to indicate that an interrupt is pending 399 * on one of the OUT endpoints of the core (in Device mode). The 400 * application must read the Device All Endpoints Interrupt 401 * (DAINT) register to determine the exact number of the OUT 402 * endpoint on which the interrupt occurred, and then read the 403 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) 404 * register to determine the exact cause of the interrupt. The 405 * application must clear the appropriate status bit in the 406 * corresponding DOEPINTn register to clear this bit. 407 * @iepint: IN Endpoints Interrupt (IEPInt) 408 * The core sets this bit to indicate that an interrupt is pending 409 * on one of the IN endpoints of the core (in Device mode). The 410 * application must read the Device All Endpoints Interrupt 411 * (DAINT) register to determine the exact number of the IN 412 * endpoint on which the interrupt occurred, and then read the 413 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn) 414 * register to determine the exact cause of the interrupt. The 415 * application must clear the appropriate status bit in the 416 * corresponding DIEPINTn register to clear this bit. 417 * @epmis: Endpoint Mismatch Interrupt (EPMis) 418 * Indicates that an IN token has been received for a non-periodic 419 * endpoint, but the data for another endpoint is present in the 420 * top of the Non-Periodic Transmit FIFO and the IN endpoint 421 * mismatch count programmed by the application has expired. 422 * @eopf: End of Periodic Frame Interrupt (EOPF) 423 * Indicates that the period specified in the Periodic Frame 424 * Interval field of the Device Configuration register 425 * (DCFG.PerFrInt) has been reached in the current microframe. 426 * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) 427 * The core sets this bit when it fails to write an isochronous OUT 428 * packet into the RxFIFO because the RxFIFO doesn't have 429 * enough space to accommodate a maximum packet size packet 430 * for the isochronous OUT endpoint. 431 * @enumdone: Enumeration Done (EnumDone) 432 * The core sets this bit to indicate that speed enumeration is 433 * complete. The application must read the Device Status (DSTS) 434 * register to obtain the enumerated speed. 435 * @usbrst: USB Reset (USBRst) 436 * The core sets this bit to indicate that a reset is detected on 437 * the USB. 438 * @usbsusp: USB Suspend (USBSusp) 439 * The core sets this bit to indicate that a suspend was detected 440 * on the USB. The core enters the Suspended state when there 441 * is no activity on the phy_line_state_i signal for an extended 442 * period of time. 443 * @erlysusp: Early Suspend (ErlySusp) 444 * The core sets this bit to indicate that an Idle state has been 445 * detected on the USB for 3 ms. 446 * @i2cint: I2C Interrupt (I2CINT) 447 * This bit is always 0x0. 448 * @ulpickint: ULPI Carkit Interrupt (ULPICKINT) 449 * This bit is always 0x0. 450 * @goutnakeff: Global OUT NAK Effective (GOUTNakEff) 451 * Indicates that the Set Global OUT NAK bit in the Device Control 452 * register (DCTL.SGOUTNak), set by the application, has taken 453 * effect in the core. This bit can be cleared by writing the Clear 454 * Global OUT NAK bit in the Device Control register 455 * (DCTL.CGOUTNak). 456 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff) 457 * Indicates that the Set Global Non-Periodic IN NAK bit in the 458 * Device Control register (DCTL.SGNPInNak), set by the 459 * application, has taken effect in the core. That is, the core has 460 * sampled the Global IN NAK bit set by the application. This bit 461 * can be cleared by clearing the Clear Global Non-Periodic IN 462 * NAK bit in the Device Control register (DCTL.CGNPInNak). 463 * This interrupt does not necessarily mean that a NAK handshake 464 * is sent out on the USB. The STALL bit takes precedence over 465 * the NAK bit. 466 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp) 467 * This interrupt is asserted when the Non-Periodic TxFIFO is 468 * either half or completely empty, and there is space for at least 469 * one entry to be written to the Non-Periodic Transmit Request 470 * Queue. The half or completely empty status is determined by 471 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB 472 * Configuration register (GAHBCFG.NPTxFEmpLvl). 473 * @rxflvl: RxFIFO Non-Empty (RxFLvl) 474 * Indicates that there is at least one packet pending to be read 475 * from the RxFIFO. 476 * @sof: Start of (micro)Frame (Sof) 477 * In Host mode, the core sets this bit to indicate that an SOF 478 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the 479 * USB. The application must write a 1 to this bit to clear the 480 * interrupt. 481 * In Device mode, in the core sets this bit to indicate that an 482 * SOF token has been received on the USB. The application can read 483 * the Device Status register to get the current (micro)frame 484 * number. This interrupt is seen only when the core is operating 485 * at either HS or FS. 486 * @otgint: OTG Interrupt (OTGInt) 487 * The core sets this bit to indicate an OTG protocol event. The 488 * application must read the OTG Interrupt Status (GOTGINT) 489 * register to determine the exact event that caused this 490 * interrupt. The application must clear the appropriate status bit 491 * in the GOTGINT register to clear this bit. 492 * @modemis: Mode Mismatch Interrupt (ModeMis) 493 * The core sets this bit when the application is trying to access: 494 * * A Host mode register, when the core is operating in Device 495 * mode 496 * * A Device mode register, when the core is operating in Host 497 * mode 498 * The register access is completed on the AHB with an OKAY 499 * response, but is ignored by the core internally and doesn't 500 * affect the operation of the core. 501 * @curmod: Current Mode of Operation (CurMod) 502 * Indicates the current mode of operation. 503 * * 1'b0: Device mode 504 * * 1'b1: Host mode 505 */ 506 struct cvmx_usbcx_gintsts_s { 507 uint32_t wkupint : 1; 508 uint32_t sessreqint : 1; 509 uint32_t disconnint : 1; 510 uint32_t conidstschng : 1; 511 uint32_t reserved_27_27 : 1; 512 uint32_t ptxfemp : 1; 513 uint32_t hchint : 1; 514 uint32_t prtint : 1; 515 uint32_t reserved_23_23 : 1; 516 uint32_t fetsusp : 1; 517 uint32_t incomplp : 1; 518 uint32_t incompisoin : 1; 519 uint32_t oepint : 1; 520 uint32_t iepint : 1; 521 uint32_t epmis : 1; 522 uint32_t reserved_16_16 : 1; 523 uint32_t eopf : 1; 524 uint32_t isooutdrop : 1; 525 uint32_t enumdone : 1; 526 uint32_t usbrst : 1; 527 uint32_t usbsusp : 1; 528 uint32_t erlysusp : 1; 529 uint32_t i2cint : 1; 530 uint32_t ulpickint : 1; 531 uint32_t goutnakeff : 1; 532 uint32_t ginnakeff : 1; 533 uint32_t nptxfemp : 1; 534 uint32_t rxflvl : 1; 535 uint32_t sof : 1; 536 uint32_t otgint : 1; 537 uint32_t modemis : 1; 538 uint32_t curmod : 1; 539 } s; 540}; 541 542/** 543 * cvmx_usbc#_gnptxfsiz 544 * 545 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ) 546 * 547 * The application can program the RAM size and the memory start address for the 548 * Non-Periodic TxFIFO. 549 */ 550union cvmx_usbcx_gnptxfsiz { 551 uint32_t u32; 552 /** 553 * struct cvmx_usbcx_gnptxfsiz_s 554 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep) 555 * This value is in terms of 32-bit words. 556 * Minimum value is 16 557 * Maximum value is 32768 558 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr) 559 * This field contains the memory start address for Non-Periodic 560 * Transmit FIFO RAM. 561 */ 562 struct cvmx_usbcx_gnptxfsiz_s { 563 uint32_t nptxfdep : 16; 564 uint32_t nptxfstaddr : 16; 565 } s; 566}; 567 568/** 569 * cvmx_usbc#_gnptxsts 570 * 571 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS) 572 * 573 * This read-only register contains the free space information for the 574 * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue. 575 */ 576union cvmx_usbcx_gnptxsts { 577 uint32_t u32; 578 /** 579 * struct cvmx_usbcx_gnptxsts_s 580 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop) 581 * Entry in the Non-Periodic Tx Request Queue that is currently 582 * being processed by the MAC. 583 * * Bits [30:27]: Channel/endpoint number 584 * * Bits [26:25]: 585 * - 2'b00: IN/OUT token 586 * - 2'b01: Zero-length transmit packet (device IN/host OUT) 587 * - 2'b10: PING/CSPLIT token 588 * - 2'b11: Channel halt command 589 * * Bit [24]: Terminate (last entry for selected channel/endpoint) 590 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available 591 * (NPTxQSpcAvail) 592 * Indicates the amount of free space available in the Non- 593 * Periodic Transmit Request Queue. This queue holds both IN 594 * and OUT requests in Host mode. Device mode has only IN 595 * requests. 596 * * 8'h0: Non-Periodic Transmit Request Queue is full 597 * * 8'h1: 1 location available 598 * * 8'h2: 2 locations available 599 * * n: n locations available (0..8) 600 * * Others: Reserved 601 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail) 602 * Indicates the amount of free space available in the Non- 603 * Periodic TxFIFO. 604 * Values are in terms of 32-bit words. 605 * * 16'h0: Non-Periodic TxFIFO is full 606 * * 16'h1: 1 word available 607 * * 16'h2: 2 words available 608 * * 16'hn: n words available (where 0..32768) 609 * * 16'h8000: 32768 words available 610 * * Others: Reserved 611 */ 612 struct cvmx_usbcx_gnptxsts_s { 613 uint32_t reserved_31_31 : 1; 614 uint32_t nptxqtop : 7; 615 uint32_t nptxqspcavail : 8; 616 uint32_t nptxfspcavail : 16; 617 } s; 618}; 619 620/** 621 * cvmx_usbc#_grstctl 622 * 623 * Core Reset Register (GRSTCTL) 624 * 625 * The application uses this register to reset various hardware features inside 626 * the core. 627 */ 628union cvmx_usbcx_grstctl { 629 uint32_t u32; 630 /** 631 * struct cvmx_usbcx_grstctl_s 632 * @ahbidle: AHB Master Idle (AHBIdle) 633 * Indicates that the AHB Master State Machine is in the IDLE 634 * condition. 635 * @dmareq: DMA Request Signal (DMAReq) 636 * Indicates that the DMA request is in progress. Used for debug. 637 * @txfnum: TxFIFO Number (TxFNum) 638 * This is the FIFO number that must be flushed using the TxFIFO 639 * Flush bit. This field must not be changed until the core clears 640 * the TxFIFO Flush bit. 641 * * 5'h0: Non-Periodic TxFIFO flush 642 * * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic 643 * TxFIFO flush in Host mode 644 * * 5'h2: Periodic TxFIFO 2 flush in Device mode 645 * - ... 646 * * 5'hF: Periodic TxFIFO 15 flush in Device mode 647 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the 648 * core 649 * @txfflsh: TxFIFO Flush (TxFFlsh) 650 * This bit selectively flushes a single or all transmit FIFOs, but 651 * cannot do so if the core is in the midst of a transaction. 652 * The application must only write this bit after checking that the 653 * core is neither writing to the TxFIFO nor reading from the 654 * TxFIFO. 655 * The application must wait until the core clears this bit before 656 * performing any operations. This bit takes 8 clocks (of phy_clk 657 * or hclk, whichever is slower) to clear. 658 * @rxfflsh: RxFIFO Flush (RxFFlsh) 659 * The application can flush the entire RxFIFO using this bit, but 660 * must first ensure that the core is not in the middle of a 661 * transaction. 662 * The application must only write to this bit after checking that 663 * the core is neither reading from the RxFIFO nor writing to the 664 * RxFIFO. 665 * The application must wait until the bit is cleared before 666 * performing any other operations. This bit will take 8 clocks 667 * (slowest of PHY or AHB clock) to clear. 668 * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh) 669 * The application writes this bit to flush the IN Token Sequence 670 * Learning Queue. 671 * @frmcntrrst: Host Frame Counter Reset (FrmCntrRst) 672 * The application writes this bit to reset the (micro)frame number 673 * counter inside the core. When the (micro)frame counter is reset, 674 * the subsequent SOF sent out by the core will have a 675 * (micro)frame number of 0. 676 * @hsftrst: HClk Soft Reset (HSftRst) 677 * The application uses this bit to flush the control logic in the 678 * AHB Clock domain. Only AHB Clock Domain pipelines are reset. 679 * * FIFOs are not flushed with this bit. 680 * * All state machines in the AHB clock domain are reset to the 681 * Idle state after terminating the transactions on the AHB, 682 * following the protocol. 683 * * CSR control bits used by the AHB clock domain state 684 * machines are cleared. 685 * * To clear this interrupt, status mask bits that control the 686 * interrupt status and are generated by the AHB clock domain 687 * state machine are cleared. 688 * * Because interrupt status bits are not cleared, the application 689 * can get the status of any core events that occurred after it set 690 * this bit. 691 * This is a self-clearing bit that the core clears after all 692 * necessary logic is reset in the core. This may take several 693 * clocks, depending on the core's current state. 694 * @csftrst: Core Soft Reset (CSftRst) 695 * Resets the hclk and phy_clock domains as follows: 696 * * Clears the interrupts and all the CSR registers except the 697 * following register bits: 698 * - PCGCCTL.RstPdwnModule 699 * - PCGCCTL.GateHclk 700 * - PCGCCTL.PwrClmp 701 * - PCGCCTL.StopPPhyLPwrClkSelclk 702 * - GUSBCFG.PhyLPwrClkSel 703 * - GUSBCFG.DDRSel 704 * - GUSBCFG.PHYSel 705 * - GUSBCFG.FSIntf 706 * - GUSBCFG.ULPI_UTMI_Sel 707 * - GUSBCFG.PHYIf 708 * - HCFG.FSLSPclkSel 709 * - DCFG.DevSpd 710 * * All module state machines (except the AHB Slave Unit) are 711 * reset to the IDLE state, and all the transmit FIFOs and the 712 * receive FIFO are flushed. 713 * * Any transactions on the AHB Master are terminated as soon 714 * as possible, after gracefully completing the last data phase of 715 * an AHB transfer. Any transactions on the USB are terminated 716 * immediately. 717 * The application can write to this bit any time it wants to reset 718 * the core. This is a self-clearing bit and the core clears this 719 * bit after all the necessary logic is reset in the core, which 720 * may take several clocks, depending on the current state of the 721 * core. Once this bit is cleared software should wait at least 3 722 * PHY clocks before doing any access to the PHY domain 723 * (synchronization delay). Software should also should check that 724 * bit 31 of this register is 1 (AHB Master is IDLE) before 725 * starting any operation. 726 * Typically software reset is used during software development 727 * and also when you dynamically change the PHY selection bits 728 * in the USB configuration registers listed above. When you 729 * change the PHY, the corresponding clock for the PHY is 730 * selected and used in the PHY domain. Once a new clock is 731 * selected, the PHY domain has to be reset for proper operation. 732 */ 733 struct cvmx_usbcx_grstctl_s { 734 uint32_t ahbidle : 1; 735 uint32_t dmareq : 1; 736 uint32_t reserved_11_29 : 19; 737 uint32_t txfnum : 5; 738 uint32_t txfflsh : 1; 739 uint32_t rxfflsh : 1; 740 uint32_t intknqflsh : 1; 741 uint32_t frmcntrrst : 1; 742 uint32_t hsftrst : 1; 743 uint32_t csftrst : 1; 744 } s; 745}; 746 747/** 748 * cvmx_usbc#_grxfsiz 749 * 750 * Receive FIFO Size Register (GRXFSIZ) 751 * 752 * The application can program the RAM size that must be allocated to the 753 * RxFIFO. 754 */ 755union cvmx_usbcx_grxfsiz { 756 uint32_t u32; 757 /** 758 * struct cvmx_usbcx_grxfsiz_s 759 * @rxfdep: RxFIFO Depth (RxFDep) 760 * This value is in terms of 32-bit words. 761 * * Minimum value is 16 762 * * Maximum value is 32768 763 */ 764 struct cvmx_usbcx_grxfsiz_s { 765 uint32_t reserved_16_31 : 16; 766 uint32_t rxfdep : 16; 767 } s; 768}; 769 770/** 771 * cvmx_usbc#_grxstsph 772 * 773 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH) 774 * 775 * A read to the Receive Status Read and Pop register returns and additionally 776 * pops the top data entry out of the RxFIFO. 777 * This Description is only valid when the core is in Host Mode. For Device Mode 778 * use USBC_GRXSTSPD instead. 779 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the 780 * same offset in the O2P USB core. The offset difference shown in this 781 * document is for software clarity and is actually ignored by the 782 * hardware. 783 */ 784union cvmx_usbcx_grxstsph { 785 uint32_t u32; 786 /** 787 * struct cvmx_usbcx_grxstsph_s 788 * @pktsts: Packet Status (PktSts) 789 * Indicates the status of the received packet 790 * * 4'b0010: IN data packet received 791 * * 4'b0011: IN transfer completed (triggers an interrupt) 792 * * 4'b0101: Data toggle error (triggers an interrupt) 793 * * 4'b0111: Channel halted (triggers an interrupt) 794 * * Others: Reserved 795 * @dpid: Data PID (DPID) 796 * * 2'b00: DATA0 797 * * 2'b10: DATA1 798 * * 2'b01: DATA2 799 * * 2'b11: MDATA 800 * @bcnt: Byte Count (BCnt) 801 * Indicates the byte count of the received IN data packet 802 * @chnum: Channel Number (ChNum) 803 * Indicates the channel number to which the current received 804 * packet belongs. 805 */ 806 struct cvmx_usbcx_grxstsph_s { 807 uint32_t reserved_21_31 : 11; 808 uint32_t pktsts : 4; 809 uint32_t dpid : 2; 810 uint32_t bcnt : 11; 811 uint32_t chnum : 4; 812 } s; 813}; 814 815/** 816 * cvmx_usbc#_gusbcfg 817 * 818 * Core USB Configuration Register (GUSBCFG) 819 * 820 * This register can be used to configure the core after power-on or a changing 821 * to Host mode or Device mode. It contains USB and USB-PHY related 822 * configuration parameters. The application must program this register before 823 * starting any transactions on either the AHB or the USB. Do not make changes 824 * to this register after the initial programming. 825 */ 826union cvmx_usbcx_gusbcfg { 827 uint32_t u32; 828 /** 829 * struct cvmx_usbcx_gusbcfg_s 830 * @otgi2csel: UTMIFS or I2C Interface Select (OtgI2CSel) 831 * This bit is always 0x0. 832 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel) 833 * Software should set this bit to 0x0. 834 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In 835 * FS and LS modes, the PHY can usually operate on a 48-MHz 836 * clock to save power. 837 * * 1'b0: 480-MHz Internal PLL clock 838 * * 1'b1: 48-MHz External Clock 839 * In 480 MHz mode, the UTMI interface operates at either 60 or 840 * 30-MHz, depending upon whether 8- or 16-bit data width is 841 * selected. In 48-MHz mode, the UTMI interface operates at 48 842 * MHz in FS mode and at either 48 or 6 MHz in LS mode 843 * (depending on the PHY vendor). 844 * This bit drives the utmi_fsls_low_power core output signal, and 845 * is valid only for UTMI+ PHYs. 846 * @usbtrdtim: USB Turnaround Time (USBTrdTim) 847 * Sets the turnaround time in PHY clocks. 848 * Specifies the response time for a MAC request to the Packet 849 * FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). 850 * This must be programmed to 0x5. 851 * @hnpcap: HNP-Capable (HNPCap) 852 * This bit is always 0x0. 853 * @srpcap: SRP-Capable (SRPCap) 854 * This bit is always 0x0. 855 * @ddrsel: ULPI DDR Select (DDRSel) 856 * Software should set this bit to 0x0. 857 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial 858 * Software should set this bit to 0x0. 859 * @fsintf: Full-Speed Serial Interface Select (FSIntf) 860 * Software should set this bit to 0x0. 861 * @ulpi_utmi_sel: ULPI or UTMI+ Select (ULPI_UTMI_Sel) 862 * This bit is always 0x0. 863 * @phyif: PHY Interface (PHYIf) 864 * This bit is always 0x1. 865 * @toutcal: HS/FS Timeout Calibration (TOutCal) 866 * The number of PHY clocks that the application programs in this 867 * field is added to the high-speed/full-speed interpacket timeout 868 * duration in the core to account for any additional delays 869 * introduced by the PHY. This may be required, since the delay 870 * introduced by the PHY in generating the linestate condition may 871 * vary from one PHY to another. 872 * The USB standard timeout value for high-speed operation is 873 * 736 to 816 (inclusive) bit times. The USB standard timeout 874 * value for full-speed operation is 16 to 18 (inclusive) bit 875 * times. The application must program this field based on the 876 * speed of enumeration. The number of bit times added per PHY 877 * clock are: 878 * High-speed operation: 879 * * One 30-MHz PHY clock = 16 bit times 880 * * One 60-MHz PHY clock = 8 bit times 881 * Full-speed operation: 882 * * One 30-MHz PHY clock = 0.4 bit times 883 * * One 60-MHz PHY clock = 0.2 bit times 884 * * One 48-MHz PHY clock = 0.25 bit times 885 */ 886 struct cvmx_usbcx_gusbcfg_s { 887 uint32_t reserved_17_31 : 15; 888 uint32_t otgi2csel : 1; 889 uint32_t phylpwrclksel : 1; 890 uint32_t reserved_14_14 : 1; 891 uint32_t usbtrdtim : 4; 892 uint32_t hnpcap : 1; 893 uint32_t srpcap : 1; 894 uint32_t ddrsel : 1; 895 uint32_t physel : 1; 896 uint32_t fsintf : 1; 897 uint32_t ulpi_utmi_sel : 1; 898 uint32_t phyif : 1; 899 uint32_t toutcal : 3; 900 } s; 901}; 902 903/** 904 * cvmx_usbc#_haint 905 * 906 * Host All Channels Interrupt Register (HAINT) 907 * 908 * When a significant event occurs on a channel, the Host All Channels Interrupt 909 * register interrupts the application using the Host Channels Interrupt bit of 910 * the Core Interrupt register (GINTSTS.HChInt). This is shown in Interrupt. 911 * There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in 912 * this register are set and cleared when the application sets and clears bits 913 * in the corresponding Host Channel-n Interrupt register. 914 */ 915union cvmx_usbcx_haint { 916 uint32_t u32; 917 /** 918 * struct cvmx_usbcx_haint_s 919 * @haint: Channel Interrupts (HAINT) 920 * One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 921 */ 922 struct cvmx_usbcx_haint_s { 923 uint32_t reserved_16_31 : 16; 924 uint32_t haint : 16; 925 } s; 926}; 927 928/** 929 * cvmx_usbc#_haintmsk 930 * 931 * Host All Channels Interrupt Mask Register (HAINTMSK) 932 * 933 * The Host All Channel Interrupt Mask register works with the Host All Channel 934 * Interrupt register to interrupt the application when an event occurs on a 935 * channel. There is one interrupt mask bit per channel, up to a maximum of 16 936 * bits. 937 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 938 */ 939union cvmx_usbcx_haintmsk { 940 uint32_t u32; 941 /** 942 * struct cvmx_usbcx_haintmsk_s 943 * @haintmsk: Channel Interrupt Mask (HAINTMsk) 944 * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 945 */ 946 struct cvmx_usbcx_haintmsk_s { 947 uint32_t reserved_16_31 : 16; 948 uint32_t haintmsk : 16; 949 } s; 950}; 951 952/** 953 * cvmx_usbc#_hcchar# 954 * 955 * Host Channel-n Characteristics Register (HCCHAR) 956 * 957 */ 958union cvmx_usbcx_hccharx { 959 uint32_t u32; 960 /** 961 * struct cvmx_usbcx_hccharx_s 962 * @chena: Channel Enable (ChEna) 963 * This field is set by the application and cleared by the OTG 964 * host. 965 * * 1'b0: Channel disabled 966 * * 1'b1: Channel enabled 967 * @chdis: Channel Disable (ChDis) 968 * The application sets this bit to stop transmitting/receiving 969 * data on a channel, even before the transfer for that channel is 970 * complete. The application must wait for the Channel Disabled 971 * interrupt before treating the channel as disabled. 972 * @oddfrm: Odd Frame (OddFrm) 973 * This field is set (reset) by the application to indicate that 974 * the OTG host must perform a transfer in an odd (micro)frame. 975 * This field is applicable for only periodic (isochronous and 976 * interrupt) transactions. 977 * * 1'b0: Even (micro)frame 978 * * 1'b1: Odd (micro)frame 979 * @devaddr: Device Address (DevAddr) 980 * This field selects the specific device serving as the data 981 * source or sink. 982 * @ec: Multi Count (MC) / Error Count (EC) 983 * When the Split Enable bit of the Host Channel-n Split Control 984 * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates 985 * to the host the number of transactions that should be executed 986 * per microframe for this endpoint. 987 * * 2'b00: Reserved. This field yields undefined results. 988 * * 2'b01: 1 transaction 989 * * 2'b10: 2 transactions to be issued for this endpoint per 990 * microframe 991 * * 2'b11: 3 transactions to be issued for this endpoint per 992 * microframe 993 * When HCSPLTn.SpltEna is set (1'b1), this field indicates the 994 * number of immediate retries to be performed for a periodic split 995 * transactions on transaction errors. This field must be set to at 996 * least 2'b01. 997 * @eptype: Endpoint Type (EPType) 998 * Indicates the transfer type selected. 999 * * 2'b00: Control 1000 * * 2'b01: Isochronous 1001 * * 2'b10: Bulk 1002 * * 2'b11: Interrupt 1003 * @lspddev: Low-Speed Device (LSpdDev) 1004 * This field is set by the application to indicate that this 1005 * channel is communicating to a low-speed device. 1006 * @epdir: Endpoint Direction (EPDir) 1007 * Indicates whether the transaction is IN or OUT. 1008 * * 1'b0: OUT 1009 * * 1'b1: IN 1010 * @epnum: Endpoint Number (EPNum) 1011 * Indicates the endpoint number on the device serving as the 1012 * data source or sink. 1013 * @mps: Maximum Packet Size (MPS) 1014 * Indicates the maximum packet size of the associated endpoint. 1015 */ 1016 struct cvmx_usbcx_hccharx_s { 1017 uint32_t chena : 1; 1018 uint32_t chdis : 1; 1019 uint32_t oddfrm : 1; 1020 uint32_t devaddr : 7; 1021 uint32_t ec : 2; 1022 uint32_t eptype : 2; 1023 uint32_t lspddev : 1; 1024 uint32_t reserved_16_16 : 1; 1025 uint32_t epdir : 1; 1026 uint32_t epnum : 4; 1027 uint32_t mps : 11; 1028 } s; 1029}; 1030 1031/** 1032 * cvmx_usbc#_hcfg 1033 * 1034 * Host Configuration Register (HCFG) 1035 * 1036 * This register configures the core after power-on. Do not make changes to this 1037 * register after initializing the host. 1038 */ 1039union cvmx_usbcx_hcfg { 1040 uint32_t u32; 1041 /** 1042 * struct cvmx_usbcx_hcfg_s 1043 * @fslssupp: FS- and LS-Only Support (FSLSSupp) 1044 * The application uses this bit to control the core's enumeration 1045 * speed. Using this bit, the application can make the core 1046 * enumerate as a FS host, even if the connected device supports 1047 * HS traffic. Do not make changes to this field after initial 1048 * programming. 1049 * * 1'b0: HS/FS/LS, based on the maximum speed supported by 1050 * the connected device 1051 * * 1'b1: FS/LS-only, even if the connected device can support HS 1052 * @fslspclksel: FS/LS PHY Clock Select (FSLSPclkSel) 1053 * When the core is in FS Host mode 1054 * * 2'b00: PHY clock is running at 30/60 MHz 1055 * * 2'b01: PHY clock is running at 48 MHz 1056 * * Others: Reserved 1057 * When the core is in LS Host mode 1058 * * 2'b00: PHY clock is running at 30/60 MHz. When the 1059 * UTMI+/ULPI PHY Low Power mode is not selected, use 1060 * 30/60 MHz. 1061 * * 2'b01: PHY clock is running at 48 MHz. When the UTMI+ 1062 * PHY Low Power mode is selected, use 48MHz if the PHY 1063 * supplies a 48 MHz clock during LS mode. 1064 * * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, 1065 * use 6 MHz when the UTMI+ PHY Low Power mode is 1066 * selected and the PHY supplies a 6 MHz clock during LS 1067 * mode. If you select a 6 MHz clock during LS mode, you must 1068 * do a soft reset. 1069 * * 2'b11: Reserved 1070 */ 1071 struct cvmx_usbcx_hcfg_s { 1072 uint32_t reserved_3_31 : 29; 1073 uint32_t fslssupp : 1; 1074 uint32_t fslspclksel : 2; 1075 } s; 1076}; 1077 1078/** 1079 * cvmx_usbc#_hcint# 1080 * 1081 * Host Channel-n Interrupt Register (HCINT) 1082 * 1083 * This register indicates the status of a channel with respect to USB- and 1084 * AHB-related events. The application must read this register when the Host 1085 * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is 1086 * set. Before the application can read this register, it must first read 1087 * the Host All Channels Interrupt (HAINT) register to get the exact channel 1088 * number for the Host Channel-n Interrupt register. The application must clear 1089 * the appropriate bit in this register to clear the corresponding bits in the 1090 * HAINT and GINTSTS registers. 1091 */ 1092union cvmx_usbcx_hcintx { 1093 uint32_t u32; 1094 /** 1095 * struct cvmx_usbcx_hcintx_s 1096 * @datatglerr: Data Toggle Error (DataTglErr) 1097 * @frmovrun: Frame Overrun (FrmOvrun) 1098 * @bblerr: Babble Error (BblErr) 1099 * @xacterr: Transaction Error (XactErr) 1100 * @nyet: NYET Response Received Interrupt (NYET) 1101 * @ack: ACK Response Received Interrupt (ACK) 1102 * @nak: NAK Response Received Interrupt (NAK) 1103 * @stall: STALL Response Received Interrupt (STALL) 1104 * @ahberr: This bit is always 0x0. 1105 * @chhltd: Channel Halted (ChHltd) 1106 * Indicates the transfer completed abnormally either because of 1107 * any USB transaction error or in response to disable request by 1108 * the application. 1109 * @xfercompl: Transfer Completed (XferCompl) 1110 * Transfer completed normally without any errors. 1111 */ 1112 struct cvmx_usbcx_hcintx_s { 1113 uint32_t reserved_11_31 : 21; 1114 uint32_t datatglerr : 1; 1115 uint32_t frmovrun : 1; 1116 uint32_t bblerr : 1; 1117 uint32_t xacterr : 1; 1118 uint32_t nyet : 1; 1119 uint32_t ack : 1; 1120 uint32_t nak : 1; 1121 uint32_t stall : 1; 1122 uint32_t ahberr : 1; 1123 uint32_t chhltd : 1; 1124 uint32_t xfercompl : 1; 1125 } s; 1126}; 1127 1128/** 1129 * cvmx_usbc#_hcintmsk# 1130 * 1131 * Host Channel-n Interrupt Mask Register (HCINTMSKn) 1132 * 1133 * This register reflects the mask for each channel status described in the 1134 * previous section. 1135 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1136 */ 1137union cvmx_usbcx_hcintmskx { 1138 uint32_t u32; 1139 /** 1140 * struct cvmx_usbcx_hcintmskx_s 1141 * @datatglerrmsk: Data Toggle Error Mask (DataTglErrMsk) 1142 * @frmovrunmsk: Frame Overrun Mask (FrmOvrunMsk) 1143 * @bblerrmsk: Babble Error Mask (BblErrMsk) 1144 * @xacterrmsk: Transaction Error Mask (XactErrMsk) 1145 * @nyetmsk: NYET Response Received Interrupt Mask (NyetMsk) 1146 * @ackmsk: ACK Response Received Interrupt Mask (AckMsk) 1147 * @nakmsk: NAK Response Received Interrupt Mask (NakMsk) 1148 * @stallmsk: STALL Response Received Interrupt Mask (StallMsk) 1149 * @ahberrmsk: AHB Error Mask (AHBErrMsk) 1150 * @chhltdmsk: Channel Halted Mask (ChHltdMsk) 1151 * @xfercomplmsk: Transfer Completed Mask (XferComplMsk) 1152 */ 1153 struct cvmx_usbcx_hcintmskx_s { 1154 uint32_t reserved_11_31 : 21; 1155 uint32_t datatglerrmsk : 1; 1156 uint32_t frmovrunmsk : 1; 1157 uint32_t bblerrmsk : 1; 1158 uint32_t xacterrmsk : 1; 1159 uint32_t nyetmsk : 1; 1160 uint32_t ackmsk : 1; 1161 uint32_t nakmsk : 1; 1162 uint32_t stallmsk : 1; 1163 uint32_t ahberrmsk : 1; 1164 uint32_t chhltdmsk : 1; 1165 uint32_t xfercomplmsk : 1; 1166 } s; 1167}; 1168 1169/** 1170 * cvmx_usbc#_hcsplt# 1171 * 1172 * Host Channel-n Split Control Register (HCSPLT) 1173 * 1174 */ 1175union cvmx_usbcx_hcspltx { 1176 uint32_t u32; 1177 /** 1178 * struct cvmx_usbcx_hcspltx_s 1179 * @spltena: Split Enable (SpltEna) 1180 * The application sets this field to indicate that this channel is 1181 * enabled to perform split transactions. 1182 * @compsplt: Do Complete Split (CompSplt) 1183 * The application sets this field to request the OTG host to 1184 * perform a complete split transaction. 1185 * @xactpos: Transaction Position (XactPos) 1186 * This field is used to determine whether to send all, first, 1187 * middle, or last payloads with each OUT transaction. 1188 * * 2'b11: All. This is the entire data payload is of this 1189 * transaction (which is less than or equal to 188 bytes). 1190 * * 2'b10: Begin. This is the first data payload of this 1191 * transaction (which is larger than 188 bytes). 1192 * * 2'b00: Mid. This is the middle payload of this transaction 1193 * (which is larger than 188 bytes). 1194 * * 2'b01: End. This is the last payload of this transaction 1195 * (which is larger than 188 bytes). 1196 * @hubaddr: Hub Address (HubAddr) 1197 * This field holds the device address of the transaction 1198 * translator's hub. 1199 * @prtaddr: Port Address (PrtAddr) 1200 * This field is the port number of the recipient transaction 1201 * translator. 1202 */ 1203 struct cvmx_usbcx_hcspltx_s { 1204 uint32_t spltena : 1; 1205 uint32_t reserved_17_30 : 14; 1206 uint32_t compsplt : 1; 1207 uint32_t xactpos : 2; 1208 uint32_t hubaddr : 7; 1209 uint32_t prtaddr : 7; 1210 } s; 1211}; 1212 1213/** 1214 * cvmx_usbc#_hctsiz# 1215 * 1216 * Host Channel-n Transfer Size Register (HCTSIZ) 1217 * 1218 */ 1219union cvmx_usbcx_hctsizx { 1220 uint32_t u32; 1221 /** 1222 * struct cvmx_usbcx_hctsizx_s 1223 * @dopng: Do Ping (DoPng) 1224 * Setting this field to 1 directs the host to do PING protocol. 1225 * @pid: PID (Pid) 1226 * The application programs this field with the type of PID to use 1227 * for the initial transaction. The host will maintain this field 1228 * for the rest of the transfer. 1229 * * 2'b00: DATA0 1230 * * 2'b01: DATA2 1231 * * 2'b10: DATA1 1232 * * 2'b11: MDATA (non-control)/SETUP (control) 1233 * @pktcnt: Packet Count (PktCnt) 1234 * This field is programmed by the application with the expected 1235 * number of packets to be transmitted (OUT) or received (IN). 1236 * The host decrements this count on every successful 1237 * transmission or reception of an OUT/IN packet. Once this count 1238 * reaches zero, the application is interrupted to indicate normal 1239 * completion. 1240 * @xfersize: Transfer Size (XferSize) 1241 * For an OUT, this field is the number of data bytes the host will 1242 * send during the transfer. 1243 * For an IN, this field is the buffer size that the application 1244 * has reserved for the transfer. The application is expected to 1245 * program this field as an integer multiple of the maximum packet 1246 * size for IN transactions (periodic and non-periodic). 1247 */ 1248 struct cvmx_usbcx_hctsizx_s { 1249 uint32_t dopng : 1; 1250 uint32_t pid : 2; 1251 uint32_t pktcnt : 10; 1252 uint32_t xfersize : 19; 1253 } s; 1254}; 1255 1256/** 1257 * cvmx_usbc#_hfir 1258 * 1259 * Host Frame Interval Register (HFIR) 1260 * 1261 * This register stores the frame interval information for the current speed to 1262 * which the O2P USB core has enumerated. 1263 */ 1264union cvmx_usbcx_hfir { 1265 uint32_t u32; 1266 /** 1267 * struct cvmx_usbcx_hfir_s 1268 * @frint: Frame Interval (FrInt) 1269 * The value that the application programs to this field specifies 1270 * the interval between two consecutive SOFs (FS) or micro- 1271 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the 1272 * number of PHY clocks that constitute the required frame 1273 * interval. The default value set in this field for a FS operation 1274 * when the PHY clock frequency is 60 MHz. The application can 1275 * write a value to this register only after the Port Enable bit of 1276 * the Host Port Control and Status register (HPRT.PrtEnaPort) 1277 * has been set. If no value is programmed, the core calculates 1278 * the value based on the PHY clock specified in the FS/LS PHY 1279 * Clock Select field of the Host Configuration register 1280 * (HCFG.FSLSPclkSel). Do not change the value of this field 1281 * after the initial configuration. 1282 * * 125 us (PHY clock frequency for HS) 1283 * * 1 ms (PHY clock frequency for FS/LS) 1284 */ 1285 struct cvmx_usbcx_hfir_s { 1286 uint32_t reserved_16_31 : 16; 1287 uint32_t frint : 16; 1288 } s; 1289}; 1290 1291/** 1292 * cvmx_usbc#_hfnum 1293 * 1294 * Host Frame Number/Frame Time Remaining Register (HFNUM) 1295 * 1296 * This register indicates the current frame number. 1297 * It also indicates the time remaining (in terms of the number of PHY clocks) 1298 * in the current (micro)frame. 1299 */ 1300union cvmx_usbcx_hfnum { 1301 uint32_t u32; 1302 /** 1303 * struct cvmx_usbcx_hfnum_s 1304 * @frrem: Frame Time Remaining (FrRem) 1305 * Indicates the amount of time remaining in the current 1306 * microframe (HS) or frame (FS/LS), in terms of PHY clocks. 1307 * This field decrements on each PHY clock. When it reaches 1308 * zero, this field is reloaded with the value in the Frame 1309 * Interval register and a new SOF is transmitted on the USB. 1310 * @frnum: Frame Number (FrNum) 1311 * This field increments when a new SOF is transmitted on the 1312 * USB, and is reset to 0 when it reaches 16'h3FFF. 1313 */ 1314 struct cvmx_usbcx_hfnum_s { 1315 uint32_t frrem : 16; 1316 uint32_t frnum : 16; 1317 } s; 1318}; 1319 1320/** 1321 * cvmx_usbc#_hprt 1322 * 1323 * Host Port Control and Status Register (HPRT) 1324 * 1325 * This register is available in both Host and Device modes. 1326 * Currently, the OTG Host supports only one port. 1327 * A single register holds USB port-related information such as USB reset, 1328 * enable, suspend, resume, connect status, and test mode for each port. The 1329 * R_SS_WC bits in this register can trigger an interrupt to the application 1330 * through the Host Port Interrupt bit of the Core Interrupt register 1331 * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this 1332 * register and clear the bit that caused the interrupt. For the R_SS_WC bits, 1333 * the application must write a 1 to the bit to clear the interrupt. 1334 */ 1335union cvmx_usbcx_hprt { 1336 uint32_t u32; 1337 /** 1338 * struct cvmx_usbcx_hprt_s 1339 * @prtspd: Port Speed (PrtSpd) 1340 * Indicates the speed of the device attached to this port. 1341 * * 2'b00: High speed 1342 * * 2'b01: Full speed 1343 * * 2'b10: Low speed 1344 * * 2'b11: Reserved 1345 * @prttstctl: Port Test Control (PrtTstCtl) 1346 * The application writes a nonzero value to this field to put 1347 * the port into a Test mode, and the corresponding pattern is 1348 * signaled on the port. 1349 * * 4'b0000: Test mode disabled 1350 * * 4'b0001: Test_J mode 1351 * * 4'b0010: Test_K mode 1352 * * 4'b0011: Test_SE0_NAK mode 1353 * * 4'b0100: Test_Packet mode 1354 * * 4'b0101: Test_Force_Enable 1355 * * Others: Reserved 1356 * PrtSpd must be zero (i.e. the interface must be in high-speed 1357 * mode) to use the PrtTstCtl test modes. 1358 * @prtpwr: Port Power (PrtPwr) 1359 * The application uses this field to control power to this port, 1360 * and the core clears this bit on an overcurrent condition. 1361 * * 1'b0: Power off 1362 * * 1'b1: Power on 1363 * @prtlnsts: Port Line Status (PrtLnSts) 1364 * Indicates the current logic level USB data lines 1365 * * Bit [10]: Logic level of D- 1366 * * Bit [11]: Logic level of D+ 1367 * @prtrst: Port Reset (PrtRst) 1368 * When the application sets this bit, a reset sequence is 1369 * started on this port. The application must time the reset 1370 * period and clear this bit after the reset sequence is 1371 * complete. 1372 * * 1'b0: Port not in reset 1373 * * 1'b1: Port in reset 1374 * The application must leave this bit set for at least a 1375 * minimum duration mentioned below to start a reset on the 1376 * port. The application can leave it set for another 10 ms in 1377 * addition to the required minimum duration, before clearing 1378 * the bit, even though there is no maximum limit set by the 1379 * USB standard. 1380 * * High speed: 50 ms 1381 * * Full speed/Low speed: 10 ms 1382 * @prtsusp: Port Suspend (PrtSusp) 1383 * The application sets this bit to put this port in Suspend 1384 * mode. The core only stops sending SOFs when this is set. 1385 * To stop the PHY clock, the application must set the Port 1386 * Clock Stop bit, which will assert the suspend input pin of 1387 * the PHY. 1388 * The read value of this bit reflects the current suspend 1389 * status of the port. This bit is cleared by the core after a 1390 * remote wakeup signal is detected or the application sets 1391 * the Port Reset bit or Port Resume bit in this register or the 1392 * Resume/Remote Wakeup Detected Interrupt bit or 1393 * Disconnect Detected Interrupt bit in the Core Interrupt 1394 * register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, 1395 * respectively). 1396 * * 1'b0: Port not in Suspend mode 1397 * * 1'b1: Port in Suspend mode 1398 * @prtres: Port Resume (PrtRes) 1399 * The application sets this bit to drive resume signaling on 1400 * the port. The core continues to drive the resume signal 1401 * until the application clears this bit. 1402 * If the core detects a USB remote wakeup sequence, as 1403 * indicated by the Port Resume/Remote Wakeup Detected 1404 * Interrupt bit of the Core Interrupt register 1405 * (GINTSTS.WkUpInt), the core starts driving resume 1406 * signaling without application intervention and clears this bit 1407 * when it detects a disconnect condition. The read value of 1408 * this bit indicates whether the core is currently driving 1409 * resume signaling. 1410 * * 1'b0: No resume driven 1411 * * 1'b1: Resume driven 1412 * @prtovrcurrchng: Port Overcurrent Change (PrtOvrCurrChng) 1413 * The core sets this bit when the status of the Port 1414 * Overcurrent Active bit (bit 4) in this register changes. 1415 * @prtovrcurract: Port Overcurrent Active (PrtOvrCurrAct) 1416 * Indicates the overcurrent condition of the port. 1417 * * 1'b0: No overcurrent condition 1418 * * 1'b1: Overcurrent condition 1419 * @prtenchng: Port Enable/Disable Change (PrtEnChng) 1420 * The core sets this bit when the status of the Port Enable bit 1421 * [2] of this register changes. 1422 * @prtena: Port Enable (PrtEna) 1423 * A port is enabled only by the core after a reset sequence, 1424 * and is disabled by an overcurrent condition, a disconnect 1425 * condition, or by the application clearing this bit. The 1426 * application cannot set this bit by a register write. It can only 1427 * clear it to disable the port. This bit does not trigger any 1428 * interrupt to the application. 1429 * * 1'b0: Port disabled 1430 * * 1'b1: Port enabled 1431 * @prtconndet: Port Connect Detected (PrtConnDet) 1432 * The core sets this bit when a device connection is detected 1433 * to trigger an interrupt to the application using the Host Port 1434 * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). 1435 * The application must write a 1 to this bit to clear the 1436 * interrupt. 1437 * @prtconnsts: Port Connect Status (PrtConnSts) 1438 * * 0: No device is attached to the port. 1439 * * 1: A device is attached to the port. 1440 */ 1441 struct cvmx_usbcx_hprt_s { 1442 uint32_t reserved_19_31 : 13; 1443 uint32_t prtspd : 2; 1444 uint32_t prttstctl : 4; 1445 uint32_t prtpwr : 1; 1446 uint32_t prtlnsts : 2; 1447 uint32_t reserved_9_9 : 1; 1448 uint32_t prtrst : 1; 1449 uint32_t prtsusp : 1; 1450 uint32_t prtres : 1; 1451 uint32_t prtovrcurrchng : 1; 1452 uint32_t prtovrcurract : 1; 1453 uint32_t prtenchng : 1; 1454 uint32_t prtena : 1; 1455 uint32_t prtconndet : 1; 1456 uint32_t prtconnsts : 1; 1457 } s; 1458}; 1459 1460/** 1461 * cvmx_usbc#_hptxfsiz 1462 * 1463 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ) 1464 * 1465 * This register holds the size and the memory start address of the Periodic 1466 * TxFIFO, as shown in Figures 310 and 311. 1467 */ 1468union cvmx_usbcx_hptxfsiz { 1469 uint32_t u32; 1470 /** 1471 * struct cvmx_usbcx_hptxfsiz_s 1472 * @ptxfsize: Host Periodic TxFIFO Depth (PTxFSize) 1473 * This value is in terms of 32-bit words. 1474 * * Minimum value is 16 1475 * * Maximum value is 32768 1476 * @ptxfstaddr: Host Periodic TxFIFO Start Address (PTxFStAddr) 1477 */ 1478 struct cvmx_usbcx_hptxfsiz_s { 1479 uint32_t ptxfsize : 16; 1480 uint32_t ptxfstaddr : 16; 1481 } s; 1482}; 1483 1484/** 1485 * cvmx_usbc#_hptxsts 1486 * 1487 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS) 1488 * 1489 * This read-only register contains the free space information for the Periodic 1490 * TxFIFO and the Periodic Transmit Request Queue 1491 */ 1492union cvmx_usbcx_hptxsts { 1493 uint32_t u32; 1494 /** 1495 * struct cvmx_usbcx_hptxsts_s 1496 * @ptxqtop: Top of the Periodic Transmit Request Queue (PTxQTop) 1497 * This indicates the entry in the Periodic Tx Request Queue that 1498 * is currently being processes by the MAC. 1499 * This register is used for debugging. 1500 * * Bit [31]: Odd/Even (micro)frame 1501 * - 1'b0: send in even (micro)frame 1502 * - 1'b1: send in odd (micro)frame 1503 * * Bits [30:27]: Channel/endpoint number 1504 * * Bits [26:25]: Type 1505 * - 2'b00: IN/OUT 1506 * - 2'b01: Zero-length packet 1507 * - 2'b10: CSPLIT 1508 * - 2'b11: Disable channel command 1509 * * Bit [24]: Terminate (last entry for the selected 1510 * channel/endpoint) 1511 * @ptxqspcavail: Periodic Transmit Request Queue Space Available 1512 * (PTxQSpcAvail) 1513 * Indicates the number of free locations available to be written 1514 * in the Periodic Transmit Request Queue. This queue holds both 1515 * IN and OUT requests. 1516 * * 8'h0: Periodic Transmit Request Queue is full 1517 * * 8'h1: 1 location available 1518 * * 8'h2: 2 locations available 1519 * * n: n locations available (0..8) 1520 * * Others: Reserved 1521 * @ptxfspcavail: Periodic Transmit Data FIFO Space Available 1522 * (PTxFSpcAvail) 1523 * Indicates the number of free locations available to be written 1524 * to in the Periodic TxFIFO. 1525 * Values are in terms of 32-bit words 1526 * * 16'h0: Periodic TxFIFO is full 1527 * * 16'h1: 1 word available 1528 * * 16'h2: 2 words available 1529 * * 16'hn: n words available (where 0..32768) 1530 * * 16'h8000: 32768 words available 1531 * * Others: Reserved 1532 */ 1533 struct cvmx_usbcx_hptxsts_s { 1534 uint32_t ptxqtop : 8; 1535 uint32_t ptxqspcavail : 8; 1536 uint32_t ptxfspcavail : 16; 1537 } s; 1538}; 1539 1540/** 1541 * cvmx_usbn#_clk_ctl 1542 * 1543 * USBN_CLK_CTL = USBN's Clock Control 1544 * 1545 * This register is used to control the frequency of the hclk and the 1546 * hreset and phy_rst signals. 1547 */ 1548union cvmx_usbnx_clk_ctl { 1549 uint64_t u64; 1550 /** 1551 * struct cvmx_usbnx_clk_ctl_s 1552 * @divide2: The 'hclk' used by the USB subsystem is derived 1553 * from the eclk. 1554 * Also see the field DIVIDE. DIVIDE2<1> must currently 1555 * be zero because it is not implemented, so the maximum 1556 * ratio of eclk/hclk is currently 16. 1557 * The actual divide number for hclk is: 1558 * (DIVIDE2 + 1) * (DIVIDE + 1) 1559 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to 1560 * generate the hclk in the USB Subsystem is held 1561 * in reset. This bit must be set to '0' before 1562 * changing the value os DIVIDE in this register. 1563 * The reset to the HCLK_DIVIDERis also asserted 1564 * when core reset is asserted. 1565 * @p_x_on: Force USB-PHY on during suspend. 1566 * '1' USB-PHY XO block is powered-down during 1567 * suspend. 1568 * '0' USB-PHY XO block is powered-up during 1569 * suspend. 1570 * The value of this field must be set while POR is 1571 * active. 1572 * @p_rtype: PHY reference clock type 1573 * On CN50XX/CN52XX/CN56XX the values are: 1574 * '0' The USB-PHY uses a 12MHz crystal as a clock source 1575 * at the USB_XO and USB_XI pins. 1576 * '1' Reserved. 1577 * '2' The USB_PHY uses 12/24/48MHz 2.5V board clock at the 1578 * USB_XO pin. USB_XI should be tied to ground in this 1579 * case. 1580 * '3' Reserved. 1581 * On CN3xxx bits 14 and 15 are p_xenbn and p_rclk and values are: 1582 * '0' Reserved. 1583 * '1' Reserved. 1584 * '2' The PHY PLL uses the XO block output as a reference. 1585 * The XO block uses an external clock supplied on the 1586 * XO pin. USB_XI should be tied to ground for this 1587 * usage. 1588 * '3' The XO block uses the clock from a crystal. 1589 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to 1590 * remain powered in Suspend Mode. 1591 * '1' The USB-PHY XO Bias, Bandgap and PLL are 1592 * powered down in suspend mode. 1593 * The value of this field must be set while POR is 1594 * active. 1595 * @p_c_sel: Phy clock speed select. 1596 * Selects the reference clock / crystal frequency. 1597 * '11': Reserved 1598 * '10': 48 MHz (reserved when a crystal is used) 1599 * '01': 24 MHz (reserved when a crystal is used) 1600 * '00': 12 MHz 1601 * The value of this field must be set while POR is 1602 * active. 1603 * NOTE: if a crystal is used as a reference clock, 1604 * this field must be set to 12 MHz. 1605 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV. 1606 * @sd_mode: Scaledown mode for the USBC. Control timing events 1607 * in the USBC, for normal operation this must be '0'. 1608 * @s_bist: Starts bist on the hclk memories, during the '0' 1609 * to '1' transition. 1610 * @por: Power On Reset for the PHY. 1611 * Resets all the PHYS registers and state machines. 1612 * @enable: When '1' allows the generation of the hclk. When 1613 * '0' the hclk will not be generated. SEE DIVIDE 1614 * field of this register. 1615 * @prst: When this field is '0' the reset associated with 1616 * the phy_clk functionality in the USB Subsystem is 1617 * help in reset. This bit should not be set to '1' 1618 * until the time it takes 6 clocks (hclk or phy_clk, 1619 * whichever is slower) has passed. Under normal 1620 * operation once this bit is set to '1' it should not 1621 * be set to '0'. 1622 * @hrst: When this field is '0' the reset associated with 1623 * the hclk functioanlity in the USB Subsystem is 1624 * held in reset.This bit should not be set to '1' 1625 * until 12ms after phy_clk is stable. Under normal 1626 * operation, once this bit is set to '1' it should 1627 * not be set to '0'. 1628 * @divide: The frequency of 'hclk' used by the USB subsystem 1629 * is the eclk frequency divided by the value of 1630 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 1631 * DIVIDE2 of this register. 1632 * The hclk frequency should be less than 125Mhz. 1633 * After writing a value to this field the SW should 1634 * read the field for the value written. 1635 * The ENABLE field of this register should not be set 1636 * until AFTER this field is set and then read. 1637 */ 1638 struct cvmx_usbnx_clk_ctl_s { 1639 uint64_t reserved_20_63 : 44; 1640 uint64_t divide2 : 2; 1641 uint64_t hclk_rst : 1; 1642 uint64_t p_x_on : 1; 1643 uint64_t p_rtype : 2; 1644 uint64_t p_com_on : 1; 1645 uint64_t p_c_sel : 2; 1646 uint64_t cdiv_byp : 1; 1647 uint64_t sd_mode : 2; 1648 uint64_t s_bist : 1; 1649 uint64_t por : 1; 1650 uint64_t enable : 1; 1651 uint64_t prst : 1; 1652 uint64_t hrst : 1; 1653 uint64_t divide : 3; 1654 } s; 1655}; 1656 1657/** 1658 * cvmx_usbn#_usbp_ctl_status 1659 * 1660 * USBN_USBP_CTL_STATUS = USBP Control And Status Register 1661 * 1662 * Contains general control and status information for the USBN block. 1663 */ 1664union cvmx_usbnx_usbp_ctl_status { 1665 uint64_t u64; 1666 /** 1667 * struct cvmx_usbnx_usbp_ctl_status_s 1668 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment 1669 * @txvreftune: HS DC Voltage Level Adjustment 1670 * @txfslstune: FS/LS Source Impedence Adjustment 1671 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment 1672 * @sqrxtune: Squelch Threshold Adjustment 1673 * @compdistune: Disconnect Threshold Adjustment 1674 * @otgtune: VBUS Valid Threshold Adjustment 1675 * @otgdisable: OTG Block Disable 1676 * @portreset: Per_Port Reset 1677 * @drvvbus: Drive VBUS 1678 * @lsbist: Low-Speed BIST Enable. 1679 * @fsbist: Full-Speed BIST Enable. 1680 * @hsbist: High-Speed BIST Enable. 1681 * @bist_done: PHY Bist Done. 1682 * Asserted at the end of the PHY BIST sequence. 1683 * @bist_err: PHY Bist Error. 1684 * Indicates an internal error was detected during 1685 * the BIST sequence. 1686 * @tdata_out: PHY Test Data Out. 1687 * Presents either internaly generated signals or 1688 * test register contents, based upon the value of 1689 * test_data_out_sel. 1690 * @siddq: Drives the USBP (USB-PHY) SIDDQ input. 1691 * Normally should be set to zero. 1692 * When customers have no intent to use USB PHY 1693 * interface, they should: 1694 * - still provide 3.3V to USB_VDD33, and 1695 * - tie USB_REXT to 3.3V supply, and 1696 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 1697 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable 1698 * @dma_bmode: When set to 1 the L2C DMA address will be updated 1699 * with byte-counts between packets. When set to 0 1700 * the L2C DMA address is incremented to the next 1701 * 4-byte aligned address after adding byte-count. 1702 * @usbc_end: Bigendian input to the USB Core. This should be 1703 * set to '0' for operation. 1704 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP. 1705 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP. 1706 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY. 1707 * This signal enables the pull-down resistance on 1708 * the D+ line. '1' pull down-resistance is connected 1709 * to D+/ '0' pull down resistance is not connected 1710 * to D+. When an A/B device is acting as a host 1711 * (downstream-facing port), dp_pulldown and 1712 * dm_pulldown are enabled. This must not toggle 1713 * during normal opeartion. 1714 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. 1715 * This signal enables the pull-down resistance on 1716 * the D- line. '1' pull down-resistance is connected 1717 * to D-. '0' pull down resistance is not connected 1718 * to D-. When an A/B device is acting as a host 1719 * (downstream-facing port), dp_pulldown and 1720 * dm_pulldown are enabled. This must not toggle 1721 * during normal opeartion. 1722 * @hst_mode: When '0' the USB is acting as HOST, when '1' 1723 * USB is acting as device. This field needs to be 1724 * set while the USB is in reset. 1725 * @tuning: Transmitter Tuning for High-Speed Operation. 1726 * Tunes the current supply and rise/fall output 1727 * times for high-speed operation. 1728 * [20:19] == 11: Current supply increased 1729 * approximately 9% 1730 * [20:19] == 10: Current supply increased 1731 * approximately 4.5% 1732 * [20:19] == 01: Design default. 1733 * [20:19] == 00: Current supply decreased 1734 * approximately 4.5% 1735 * [22:21] == 11: Rise and fall times are increased. 1736 * [22:21] == 10: Design default. 1737 * [22:21] == 01: Rise and fall times are decreased. 1738 * [22:21] == 00: Rise and fall times are decreased 1739 * further as compared to the 01 setting. 1740 * @tx_bs_enh: Transmit Bit Stuffing on [15:8]. 1741 * Enables or disables bit stuffing on data[15:8] 1742 * when bit-stuffing is enabled. 1743 * @tx_bs_en: Transmit Bit Stuffing on [7:0]. 1744 * Enables or disables bit stuffing on data[7:0] 1745 * when bit-stuffing is enabled. 1746 * @loop_enb: PHY Loopback Test Enable. 1747 * '1': During data transmission the receive is 1748 * enabled. 1749 * '0': During data transmission the receive is 1750 * disabled. 1751 * Must be '0' for normal operation. 1752 * @vtest_enb: Analog Test Pin Enable. 1753 * '1' The PHY's analog_test pin is enabled for the 1754 * input and output of applicable analog test signals. 1755 * '0' THe analog_test pin is disabled. 1756 * @bist_enb: Built-In Self Test Enable. 1757 * Used to activate BIST in the PHY. 1758 * @tdata_sel: Test Data Out Select. 1759 * '1' test_data_out[3:0] (PHY) register contents 1760 * are output. '0' internaly generated signals are 1761 * output. 1762 * @taddr_in: Mode Address for Test Interface. 1763 * Specifies the register address for writing to or 1764 * reading from the PHY test interface register. 1765 * @tdata_in: Internal Testing Register Input Data and Select 1766 * This is a test bus. Data is present on [3:0], 1767 * and its corresponding select (enable) is present 1768 * on bits [7:4]. 1769 * @ate_reset: Reset input from automatic test equipment. 1770 * This is a test signal. When the USB Core is 1771 * powered up (not in Susned Mode), an automatic 1772 * tester can use this to disable phy_clock and 1773 * free_clk, then re-eanable them with an aligned 1774 * phase. 1775 * '1': The phy_clk and free_clk outputs are 1776 * disabled. "0": The phy_clock and free_clk outputs 1777 * are available within a specific period after the 1778 * de-assertion. 1779 */ 1780 struct cvmx_usbnx_usbp_ctl_status_s { 1781 uint64_t txrisetune : 1; 1782 uint64_t txvreftune : 4; 1783 uint64_t txfslstune : 4; 1784 uint64_t txhsxvtune : 2; 1785 uint64_t sqrxtune : 3; 1786 uint64_t compdistune : 3; 1787 uint64_t otgtune : 3; 1788 uint64_t otgdisable : 1; 1789 uint64_t portreset : 1; 1790 uint64_t drvvbus : 1; 1791 uint64_t lsbist : 1; 1792 uint64_t fsbist : 1; 1793 uint64_t hsbist : 1; 1794 uint64_t bist_done : 1; 1795 uint64_t bist_err : 1; 1796 uint64_t tdata_out : 4; 1797 uint64_t siddq : 1; 1798 uint64_t txpreemphasistune : 1; 1799 uint64_t dma_bmode : 1; 1800 uint64_t usbc_end : 1; 1801 uint64_t usbp_bist : 1; 1802 uint64_t tclk : 1; 1803 uint64_t dp_pulld : 1; 1804 uint64_t dm_pulld : 1; 1805 uint64_t hst_mode : 1; 1806 uint64_t tuning : 4; 1807 uint64_t tx_bs_enh : 1; 1808 uint64_t tx_bs_en : 1; 1809 uint64_t loop_enb : 1; 1810 uint64_t vtest_enb : 1; 1811 uint64_t bist_enb : 1; 1812 uint64_t tdata_sel : 1; 1813 uint64_t taddr_in : 4; 1814 uint64_t tdata_in : 8; 1815 uint64_t ate_reset : 1; 1816 } s; 1817}; 1818 1819#endif /* __OCTEON_HCD_H__ */ 1820