1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * Modifications for inclusion into the Linux staging tree are 19 * Copyright(c) 2010 Larry Finger. All rights reserved. 20 * 21 * Contact information: 22 * WLAN FAE <wlanfae@realtek.com> 23 * Larry Finger <Larry.Finger@lwfinger.net> 24 * 25 ******************************************************************************/ 26#ifndef _IO_H_ 27#define _IO_H_ 28 29#include "osdep_service.h" 30#include "osdep_intf.h" 31 32#define NUM_IOREQ 8 33 34#define MAX_PROT_SZ (64-16) 35 36#define _IOREADY 0 37#define _IO_WAIT_COMPLETE 1 38#define _IO_WAIT_RSP 2 39 40/* IO COMMAND TYPE */ 41#define _IOSZ_MASK_ (0x7F) 42#define _IO_WRITE_ BIT(7) 43#define _IO_FIXED_ BIT(8) 44#define _IO_BURST_ BIT(9) 45#define _IO_BYTE_ BIT(10) 46#define _IO_HW_ BIT(11) 47#define _IO_WORD_ BIT(12) 48#define _IO_SYNC_ BIT(13) 49#define _IO_CMDMASK_ (0x1F80) 50 51/* 52 For prompt mode accessing, caller shall free io_req 53 Otherwise, io_handler will free io_req 54*/ 55/* IO STATUS TYPE */ 56#define _IO_ERR_ BIT(2) 57#define _IO_SUCCESS_ BIT(1) 58#define _IO_DONE_ BIT(0) 59#define IO_RD32 (_IO_SYNC_ | _IO_WORD_) 60#define IO_RD16 (_IO_SYNC_ | _IO_HW_) 61#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) 62#define IO_RD32_ASYNC (_IO_WORD_) 63#define IO_RD16_ASYNC (_IO_HW_) 64#define IO_RD8_ASYNC (_IO_BYTE_) 65#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) 66#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) 67#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) 68#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) 69#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) 70#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) 71/* 72 Only Sync. burst accessing is provided. 73*/ 74#define IO_WR_BURST(x) (IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | \ 75 ((x) & _IOSZ_MASK_)) 76#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) 77/*below is for the intf_option bit defition...*/ 78#define _INTF_ASYNC_ BIT(0) /*support async io*/ 79struct intf_priv; 80struct intf_hdl; 81struct io_queue; 82struct _io_ops { 83 uint (*_sdbus_read_bytes_to_membuf)(struct intf_priv *pintfpriv, 84 u32 addr, u32 cnt, u8 *pbuf); 85 uint (*_sdbus_read_blocks_to_membuf)(struct intf_priv *pintfpriv, 86 u32 addr, u32 cnt, u8 *pbuf); 87 u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); 88 u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); 89 u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); 90 uint (*_sdbus_write_blocks_from_membuf)(struct intf_priv *pintfpriv, 91 u32 addr, u32 cnt, u8 *pbuf, 92 u8 async); 93 uint (*_sdbus_write_bytes_from_membuf)(struct intf_priv *pintfpriv, 94 u32 addr, u32 cnt, u8 *pbuf); 95 u8 (*_cmd52r)(struct intf_priv *pintfpriv, u32 addr); 96 void (*_cmd52w)(struct intf_priv *pintfpriv, u32 addr, u8 val8); 97 u8 (*_cmdfunc152r)(struct intf_priv *pintfpriv, u32 addr); 98 void (*_cmdfunc152w)(struct intf_priv *pintfpriv, u32 addr, u8 val8); 99 void (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); 100 void (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); 101 void (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); 102 void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, 103 u8 *pmem); 104 void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, 105 u8 *pmem); 106 void (*_sync_irp_protocol_rw)(struct io_queue *pio_q); 107 u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, 108 u8 *pmem); 109 u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, 110 u8 *pmem); 111}; 112 113struct io_req { 114 struct list_head list; 115 u32 addr; 116 /*volatile*/ u32 val; 117 u32 command; 118 u32 status; 119 u8 *pbuf; 120 void (*_async_io_callback)(struct _adapter *padapter, 121 struct io_req *pio_req, u8 *cnxt); 122 u8 *cnxt; 123}; 124 125struct intf_hdl { 126 u32 intf_option; 127 u8 *adapter; 128 u8 *intf_dev; 129 struct intf_priv *pintfpriv; 130 void (*intf_hdl_init)(u8 *priv); 131 void (*intf_hdl_unload)(u8 *priv); 132 void (*intf_hdl_open)(u8 *priv); 133 void (*intf_hdl_close)(u8 *priv); 134 struct _io_ops io_ops; 135}; 136 137struct reg_protocol_rd { 138 139#ifdef __LITTLE_ENDIAN 140 /* DW1 */ 141 u32 NumOfTrans:4; 142 u32 Reserved1:4; 143 u32 Reserved2:24; 144 /* DW2 */ 145 u32 ByteCount:7; 146 u32 WriteEnable:1; /*0:read, 1:write*/ 147 u32 FixOrContinuous:1; /*0:continuous, 1: Fix*/ 148 u32 BurstMode:1; 149 u32 Byte1Access:1; 150 u32 Byte2Access:1; 151 u32 Byte4Access:1; 152 u32 Reserved3:3; 153 u32 Reserved4:16; 154 /*DW3*/ 155 u32 BusAddress; 156 /*DW4*/ 157#else 158/*DW1*/ 159 u32 Reserved1:4; 160 u32 NumOfTrans:4; 161 u32 Reserved2:24; 162 /*DW2*/ 163 u32 WriteEnable:1; 164 u32 ByteCount:7; 165 u32 Reserved3:3; 166 u32 Byte4Access:1; 167 u32 Byte2Access:1; 168 u32 Byte1Access:1; 169 u32 BurstMode:1; 170 u32 FixOrContinuous:1; 171 u32 Reserved4:16; 172 /*DW3*/ 173 u32 BusAddress; 174 /*DW4*/ 175#endif 176}; 177 178struct reg_protocol_wt { 179#ifdef __LITTLE_ENDIAN 180 /*DW1*/ 181 u32 NumOfTrans:4; 182 u32 Reserved1:4; 183 u32 Reserved2:24; 184 /*DW2*/ 185 u32 ByteCount:7; 186 u32 WriteEnable:1; /*0:read, 1:write*/ 187 u32 FixOrContinuous:1; /*0:continuous, 1: Fix*/ 188 u32 BurstMode:1; 189 u32 Byte1Access:1; 190 u32 Byte2Access:1; 191 u32 Byte4Access:1; 192 u32 Reserved3:3; 193 u32 Reserved4:16; 194 /*DW3*/ 195 u32 BusAddress; 196 /*DW4*/ 197 u32 Value; 198#else 199 /*DW1*/ 200 u32 Reserved1:4; 201 u32 NumOfTrans:4; 202 u32 Reserved2:24; 203 /*DW2*/ 204 u32 WriteEnable:1; 205 u32 ByteCount:7; 206 u32 Reserved3:3; 207 u32 Byte4Access:1; 208 u32 Byte2Access:1; 209 u32 Byte1Access:1; 210 u32 BurstMode:1; 211 u32 FixOrContinuous:1; 212 u32 Reserved4:16; 213 /*DW3*/ 214 u32 BusAddress; 215 /*DW4*/ 216 u32 Value; 217#endif 218}; 219 220/* 221Below is the data structure used by _io_handler 222*/ 223 224struct io_queue { 225 spinlock_t lock; 226 struct list_head free_ioreqs; 227 /*The io_req list that will be served in the single protocol r/w.*/ 228 struct list_head pending; 229 struct list_head processing; 230 u8 *free_ioreqs_buf; /* 4-byte aligned */ 231 u8 *pallocated_free_ioreqs_buf; 232 struct intf_hdl intf; 233}; 234 235static inline u32 _RND4(u32 sz) 236{ 237 u32 val; 238 239 val = ((sz >> 2) + ((sz & 3) ? 1 : 0)) << 2; 240 return val; 241} 242 243u8 r8712_read8(struct _adapter *adapter, u32 addr); 244u16 r8712_read16(struct _adapter *adapter, u32 addr); 245u32 r8712_read32(struct _adapter *adapter, u32 addr); 246void r8712_read_mem(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem); 247void r8712_read_port(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem); 248void r8712_write8(struct _adapter *adapter, u32 addr, u8 val); 249void r8712_write16(struct _adapter *adapter, u32 addr, u16 val); 250void r8712_write32(struct _adapter *adapter, u32 addr, u32 val); 251void r8712_write_mem(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem); 252void r8712_write_port(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem); 253/*ioreq */ 254uint r8712_alloc_io_queue(struct _adapter *adapter); 255void r8712_free_io_queue(struct _adapter *adapter); 256 257#endif /*_RTL8711_IO_H_*/ 258 259