1#if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2#define SUPPORT_SYSRQ 3#endif 4 5#include <linux/kernel.h> 6#include <linux/module.h> 7#include <linux/io.h> 8#include <linux/platform_device.h> 9#include <linux/console.h> 10#include <linux/sysrq.h> 11#include <linux/serial_core.h> 12#include <linux/tty_flip.h> 13#include <linux/slab.h> 14#include <linux/clk.h> 15#include <linux/of.h> 16#include <linux/of_device.h> 17 18#include <linux/platform_data/efm32-uart.h> 19 20#define DRIVER_NAME "efm32-uart" 21#define DEV_NAME "ttyefm" 22 23#define UARTn_CTRL 0x00 24#define UARTn_CTRL_SYNC 0x0001 25#define UARTn_CTRL_TXBIL 0x1000 26 27#define UARTn_FRAME 0x04 28#define UARTn_FRAME_DATABITS__MASK 0x000f 29#define UARTn_FRAME_DATABITS(n) ((n) - 3) 30#define UARTn_FRAME_PARITY_NONE 0x0000 31#define UARTn_FRAME_PARITY_EVEN 0x0200 32#define UARTn_FRAME_PARITY_ODD 0x0300 33#define UARTn_FRAME_STOPBITS_HALF 0x0000 34#define UARTn_FRAME_STOPBITS_ONE 0x1000 35#define UARTn_FRAME_STOPBITS_TWO 0x3000 36 37#define UARTn_CMD 0x0c 38#define UARTn_CMD_RXEN 0x0001 39#define UARTn_CMD_RXDIS 0x0002 40#define UARTn_CMD_TXEN 0x0004 41#define UARTn_CMD_TXDIS 0x0008 42 43#define UARTn_STATUS 0x10 44#define UARTn_STATUS_TXENS 0x0002 45#define UARTn_STATUS_TXC 0x0020 46#define UARTn_STATUS_TXBL 0x0040 47#define UARTn_STATUS_RXDATAV 0x0080 48 49#define UARTn_CLKDIV 0x14 50 51#define UARTn_RXDATAX 0x18 52#define UARTn_RXDATAX_RXDATA__MASK 0x01ff 53#define UARTn_RXDATAX_PERR 0x4000 54#define UARTn_RXDATAX_FERR 0x8000 55/* 56 * This is a software only flag used for ignore_status_mask and 57 * read_status_mask! It's used for breaks that the hardware doesn't report 58 * explicitly. 59 */ 60#define SW_UARTn_RXDATAX_BERR 0x2000 61 62#define UARTn_TXDATA 0x34 63 64#define UARTn_IF 0x40 65#define UARTn_IF_TXC 0x0001 66#define UARTn_IF_TXBL 0x0002 67#define UARTn_IF_RXDATAV 0x0004 68#define UARTn_IF_RXOF 0x0010 69 70#define UARTn_IFS 0x44 71#define UARTn_IFC 0x48 72#define UARTn_IEN 0x4c 73 74#define UARTn_ROUTE 0x54 75#define UARTn_ROUTE_LOCATION__MASK 0x0700 76#define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK) 77#define UARTn_ROUTE_RXPEN 0x0001 78#define UARTn_ROUTE_TXPEN 0x0002 79 80struct efm32_uart_port { 81 struct uart_port port; 82 unsigned int txirq; 83 struct clk *clk; 84 struct efm32_uart_pdata pdata; 85}; 86#define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port) 87#define efm_debug(efm_port, format, arg...) \ 88 dev_dbg(efm_port->port.dev, format, ##arg) 89 90static void efm32_uart_write32(struct efm32_uart_port *efm_port, 91 u32 value, unsigned offset) 92{ 93 writel_relaxed(value, efm_port->port.membase + offset); 94} 95 96static u32 efm32_uart_read32(struct efm32_uart_port *efm_port, 97 unsigned offset) 98{ 99 return readl_relaxed(efm_port->port.membase + offset); 100} 101 102static unsigned int efm32_uart_tx_empty(struct uart_port *port) 103{ 104 struct efm32_uart_port *efm_port = to_efm_port(port); 105 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS); 106 107 if (status & UARTn_STATUS_TXC) 108 return TIOCSER_TEMT; 109 else 110 return 0; 111} 112 113static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 114{ 115 /* sorry, neither handshaking lines nor loop functionallity */ 116} 117 118static unsigned int efm32_uart_get_mctrl(struct uart_port *port) 119{ 120 /* sorry, no handshaking lines available */ 121 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; 122} 123 124static void efm32_uart_stop_tx(struct uart_port *port) 125{ 126 struct efm32_uart_port *efm_port = to_efm_port(port); 127 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN); 128 129 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD); 130 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL); 131 efm32_uart_write32(efm_port, ien, UARTn_IEN); 132} 133 134static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port) 135{ 136 struct uart_port *port = &efm_port->port; 137 struct circ_buf *xmit = &port->state->xmit; 138 139 while (efm32_uart_read32(efm_port, UARTn_STATUS) & 140 UARTn_STATUS_TXBL) { 141 if (port->x_char) { 142 port->icount.tx++; 143 efm32_uart_write32(efm_port, port->x_char, 144 UARTn_TXDATA); 145 port->x_char = 0; 146 continue; 147 } 148 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 149 port->icount.tx++; 150 efm32_uart_write32(efm_port, xmit->buf[xmit->tail], 151 UARTn_TXDATA); 152 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 153 } else 154 break; 155 } 156 157 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 158 uart_write_wakeup(port); 159 160 if (!port->x_char && uart_circ_empty(xmit) && 161 efm32_uart_read32(efm_port, UARTn_STATUS) & 162 UARTn_STATUS_TXC) 163 efm32_uart_stop_tx(port); 164} 165 166static void efm32_uart_start_tx(struct uart_port *port) 167{ 168 struct efm32_uart_port *efm_port = to_efm_port(port); 169 u32 ien; 170 171 efm32_uart_write32(efm_port, 172 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC); 173 ien = efm32_uart_read32(efm_port, UARTn_IEN); 174 efm32_uart_write32(efm_port, 175 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN); 176 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD); 177 178 efm32_uart_tx_chars(efm_port); 179} 180 181static void efm32_uart_stop_rx(struct uart_port *port) 182{ 183 struct efm32_uart_port *efm_port = to_efm_port(port); 184 185 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD); 186} 187 188static void efm32_uart_break_ctl(struct uart_port *port, int ctl) 189{ 190 /* not possible without fiddling with gpios */ 191} 192 193static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port) 194{ 195 struct uart_port *port = &efm_port->port; 196 197 while (efm32_uart_read32(efm_port, UARTn_STATUS) & 198 UARTn_STATUS_RXDATAV) { 199 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX); 200 int flag = 0; 201 202 /* 203 * This is a reserved bit and I only saw it read as 0. But to be 204 * sure not to be confused too much by new devices adhere to the 205 * warning in the reference manual that reserverd bits might 206 * read as 1 in the future. 207 */ 208 rxdata &= ~SW_UARTn_RXDATAX_BERR; 209 210 port->icount.rx++; 211 212 if ((rxdata & UARTn_RXDATAX_FERR) && 213 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) { 214 rxdata |= SW_UARTn_RXDATAX_BERR; 215 port->icount.brk++; 216 if (uart_handle_break(port)) 217 continue; 218 } else if (rxdata & UARTn_RXDATAX_PERR) 219 port->icount.parity++; 220 else if (rxdata & UARTn_RXDATAX_FERR) 221 port->icount.frame++; 222 223 rxdata &= port->read_status_mask; 224 225 if (rxdata & SW_UARTn_RXDATAX_BERR) 226 flag = TTY_BREAK; 227 else if (rxdata & UARTn_RXDATAX_PERR) 228 flag = TTY_PARITY; 229 else if (rxdata & UARTn_RXDATAX_FERR) 230 flag = TTY_FRAME; 231 else if (uart_handle_sysrq_char(port, 232 rxdata & UARTn_RXDATAX_RXDATA__MASK)) 233 continue; 234 235 if ((rxdata & port->ignore_status_mask) == 0) 236 tty_insert_flip_char(&port->state->port, 237 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag); 238 } 239} 240 241static irqreturn_t efm32_uart_rxirq(int irq, void *data) 242{ 243 struct efm32_uart_port *efm_port = data; 244 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF); 245 int handled = IRQ_NONE; 246 struct uart_port *port = &efm_port->port; 247 struct tty_port *tport = &port->state->port; 248 249 spin_lock(&port->lock); 250 251 if (irqflag & UARTn_IF_RXDATAV) { 252 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC); 253 efm32_uart_rx_chars(efm_port); 254 255 handled = IRQ_HANDLED; 256 } 257 258 if (irqflag & UARTn_IF_RXOF) { 259 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC); 260 port->icount.overrun++; 261 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 262 263 handled = IRQ_HANDLED; 264 } 265 266 spin_unlock(&port->lock); 267 268 tty_flip_buffer_push(tport); 269 270 return handled; 271} 272 273static irqreturn_t efm32_uart_txirq(int irq, void *data) 274{ 275 struct efm32_uart_port *efm_port = data; 276 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF); 277 278 /* TXBL doesn't need to be cleared */ 279 if (irqflag & UARTn_IF_TXC) 280 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC); 281 282 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) { 283 efm32_uart_tx_chars(efm_port); 284 return IRQ_HANDLED; 285 } else 286 return IRQ_NONE; 287} 288 289static int efm32_uart_startup(struct uart_port *port) 290{ 291 struct efm32_uart_port *efm_port = to_efm_port(port); 292 int ret; 293 294 ret = clk_enable(efm_port->clk); 295 if (ret) { 296 efm_debug(efm_port, "failed to enable clk\n"); 297 goto err_clk_enable; 298 } 299 port->uartclk = clk_get_rate(efm_port->clk); 300 301 /* Enable pins at configured location */ 302 efm32_uart_write32(efm_port, 303 UARTn_ROUTE_LOCATION(efm_port->pdata.location) | 304 UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN, 305 UARTn_ROUTE); 306 307 ret = request_irq(port->irq, efm32_uart_rxirq, 0, 308 DRIVER_NAME, efm_port); 309 if (ret) { 310 efm_debug(efm_port, "failed to register rxirq\n"); 311 goto err_request_irq_rx; 312 } 313 314 /* disable all irqs */ 315 efm32_uart_write32(efm_port, 0, UARTn_IEN); 316 317 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0, 318 DRIVER_NAME, efm_port); 319 if (ret) { 320 efm_debug(efm_port, "failed to register txirq\n"); 321 free_irq(port->irq, efm_port); 322err_request_irq_rx: 323 324 clk_disable(efm_port->clk); 325 } else { 326 efm32_uart_write32(efm_port, 327 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN); 328 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD); 329 } 330 331err_clk_enable: 332 return ret; 333} 334 335static void efm32_uart_shutdown(struct uart_port *port) 336{ 337 struct efm32_uart_port *efm_port = to_efm_port(port); 338 339 efm32_uart_write32(efm_port, 0, UARTn_IEN); 340 free_irq(port->irq, efm_port); 341 342 clk_disable(efm_port->clk); 343} 344 345static void efm32_uart_set_termios(struct uart_port *port, 346 struct ktermios *new, struct ktermios *old) 347{ 348 struct efm32_uart_port *efm_port = to_efm_port(port); 349 unsigned long flags; 350 unsigned baud; 351 u32 clkdiv; 352 u32 frame = 0; 353 354 /* no modem control lines */ 355 new->c_cflag &= ~(CRTSCTS | CMSPAR); 356 357 baud = uart_get_baud_rate(port, new, old, 358 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192), 359 DIV_ROUND_CLOSEST(port->uartclk, 16)); 360 361 switch (new->c_cflag & CSIZE) { 362 case CS5: 363 frame |= UARTn_FRAME_DATABITS(5); 364 break; 365 case CS6: 366 frame |= UARTn_FRAME_DATABITS(6); 367 break; 368 case CS7: 369 frame |= UARTn_FRAME_DATABITS(7); 370 break; 371 case CS8: 372 frame |= UARTn_FRAME_DATABITS(8); 373 break; 374 } 375 376 if (new->c_cflag & CSTOPB) 377 /* the receiver only verifies the first stop bit */ 378 frame |= UARTn_FRAME_STOPBITS_TWO; 379 else 380 frame |= UARTn_FRAME_STOPBITS_ONE; 381 382 if (new->c_cflag & PARENB) { 383 if (new->c_cflag & PARODD) 384 frame |= UARTn_FRAME_PARITY_ODD; 385 else 386 frame |= UARTn_FRAME_PARITY_EVEN; 387 } else 388 frame |= UARTn_FRAME_PARITY_NONE; 389 390 /* 391 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25. 392 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow. 393 */ 394 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6; 395 396 spin_lock_irqsave(&port->lock, flags); 397 398 efm32_uart_write32(efm_port, 399 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD); 400 401 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK; 402 if (new->c_iflag & INPCK) 403 port->read_status_mask |= 404 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR; 405 if (new->c_iflag & (IGNBRK | BRKINT | PARMRK)) 406 port->read_status_mask |= SW_UARTn_RXDATAX_BERR; 407 408 port->ignore_status_mask = 0; 409 if (new->c_iflag & IGNPAR) 410 port->ignore_status_mask |= 411 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR; 412 if (new->c_iflag & IGNBRK) 413 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR; 414 415 uart_update_timeout(port, new->c_cflag, baud); 416 417 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL); 418 efm32_uart_write32(efm_port, frame, UARTn_FRAME); 419 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV); 420 421 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN, 422 UARTn_CMD); 423 424 spin_unlock_irqrestore(&port->lock, flags); 425} 426 427static const char *efm32_uart_type(struct uart_port *port) 428{ 429 return port->type == PORT_EFMUART ? "efm32-uart" : NULL; 430} 431 432static void efm32_uart_release_port(struct uart_port *port) 433{ 434 struct efm32_uart_port *efm_port = to_efm_port(port); 435 436 clk_unprepare(efm_port->clk); 437 clk_put(efm_port->clk); 438 iounmap(port->membase); 439} 440 441static int efm32_uart_request_port(struct uart_port *port) 442{ 443 struct efm32_uart_port *efm_port = to_efm_port(port); 444 int ret; 445 446 port->membase = ioremap(port->mapbase, 60); 447 if (!efm_port->port.membase) { 448 ret = -ENOMEM; 449 efm_debug(efm_port, "failed to remap\n"); 450 goto err_ioremap; 451 } 452 453 efm_port->clk = clk_get(port->dev, NULL); 454 if (IS_ERR(efm_port->clk)) { 455 ret = PTR_ERR(efm_port->clk); 456 efm_debug(efm_port, "failed to get clock\n"); 457 goto err_clk_get; 458 } 459 460 ret = clk_prepare(efm_port->clk); 461 if (ret) { 462 clk_put(efm_port->clk); 463err_clk_get: 464 465 iounmap(port->membase); 466err_ioremap: 467 return ret; 468 } 469 return 0; 470} 471 472static void efm32_uart_config_port(struct uart_port *port, int type) 473{ 474 if (type & UART_CONFIG_TYPE && 475 !efm32_uart_request_port(port)) 476 port->type = PORT_EFMUART; 477} 478 479static int efm32_uart_verify_port(struct uart_port *port, 480 struct serial_struct *serinfo) 481{ 482 int ret = 0; 483 484 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART) 485 ret = -EINVAL; 486 487 return ret; 488} 489 490static struct uart_ops efm32_uart_pops = { 491 .tx_empty = efm32_uart_tx_empty, 492 .set_mctrl = efm32_uart_set_mctrl, 493 .get_mctrl = efm32_uart_get_mctrl, 494 .stop_tx = efm32_uart_stop_tx, 495 .start_tx = efm32_uart_start_tx, 496 .stop_rx = efm32_uart_stop_rx, 497 .break_ctl = efm32_uart_break_ctl, 498 .startup = efm32_uart_startup, 499 .shutdown = efm32_uart_shutdown, 500 .set_termios = efm32_uart_set_termios, 501 .type = efm32_uart_type, 502 .release_port = efm32_uart_release_port, 503 .request_port = efm32_uart_request_port, 504 .config_port = efm32_uart_config_port, 505 .verify_port = efm32_uart_verify_port, 506}; 507 508static struct efm32_uart_port *efm32_uart_ports[5]; 509 510#ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE 511static void efm32_uart_console_putchar(struct uart_port *port, int ch) 512{ 513 struct efm32_uart_port *efm_port = to_efm_port(port); 514 unsigned int timeout = 0x400; 515 u32 status; 516 517 while (1) { 518 status = efm32_uart_read32(efm_port, UARTn_STATUS); 519 520 if (status & UARTn_STATUS_TXBL) 521 break; 522 if (!timeout--) 523 return; 524 } 525 efm32_uart_write32(efm_port, ch, UARTn_TXDATA); 526} 527 528static void efm32_uart_console_write(struct console *co, const char *s, 529 unsigned int count) 530{ 531 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index]; 532 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS); 533 unsigned int timeout = 0x400; 534 535 if (!(status & UARTn_STATUS_TXENS)) 536 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD); 537 538 uart_console_write(&efm_port->port, s, count, 539 efm32_uart_console_putchar); 540 541 /* Wait for the transmitter to become empty */ 542 while (1) { 543 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS); 544 if (status & UARTn_STATUS_TXC) 545 break; 546 if (!timeout--) 547 break; 548 } 549 550 if (!(status & UARTn_STATUS_TXENS)) 551 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD); 552} 553 554static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port, 555 int *baud, int *parity, int *bits) 556{ 557 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL); 558 u32 route, clkdiv, frame; 559 560 if (ctrl & UARTn_CTRL_SYNC) 561 /* not operating in async mode */ 562 return; 563 564 route = efm32_uart_read32(efm_port, UARTn_ROUTE); 565 if (!(route & UARTn_ROUTE_TXPEN)) 566 /* tx pin not routed */ 567 return; 568 569 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV); 570 571 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk, 572 16 * (4 + (clkdiv >> 6))); 573 574 frame = efm32_uart_read32(efm_port, UARTn_FRAME); 575 if (frame & UARTn_FRAME_PARITY_ODD) 576 *parity = 'o'; 577 else if (frame & UARTn_FRAME_PARITY_EVEN) 578 *parity = 'e'; 579 else 580 *parity = 'n'; 581 582 *bits = (frame & UARTn_FRAME_DATABITS__MASK) - 583 UARTn_FRAME_DATABITS(4) + 4; 584 585 efm_debug(efm_port, "get_opts: options=%d%c%d\n", 586 *baud, *parity, *bits); 587} 588 589static int efm32_uart_console_setup(struct console *co, char *options) 590{ 591 struct efm32_uart_port *efm_port; 592 int baud = 115200; 593 int bits = 8; 594 int parity = 'n'; 595 int flow = 'n'; 596 int ret; 597 598 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) { 599 unsigned i; 600 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) { 601 if (efm32_uart_ports[i]) { 602 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n", 603 i, co->index); 604 co->index = i; 605 break; 606 } 607 } 608 } 609 610 efm_port = efm32_uart_ports[co->index]; 611 if (!efm_port) { 612 pr_warn("efm32-console: No port at %d\n", co->index); 613 return -ENODEV; 614 } 615 616 ret = clk_prepare(efm_port->clk); 617 if (ret) { 618 dev_warn(efm_port->port.dev, 619 "console: clk_prepare failed: %d\n", ret); 620 return ret; 621 } 622 623 efm_port->port.uartclk = clk_get_rate(efm_port->clk); 624 625 if (options) 626 uart_parse_options(options, &baud, &parity, &bits, &flow); 627 else 628 efm32_uart_console_get_options(efm_port, 629 &baud, &parity, &bits); 630 631 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow); 632} 633 634static struct uart_driver efm32_uart_reg; 635 636static struct console efm32_uart_console = { 637 .name = DEV_NAME, 638 .write = efm32_uart_console_write, 639 .device = uart_console_device, 640 .setup = efm32_uart_console_setup, 641 .flags = CON_PRINTBUFFER, 642 .index = -1, 643 .data = &efm32_uart_reg, 644}; 645 646#else 647#define efm32_uart_console (*(struct console *)NULL) 648#endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */ 649 650static struct uart_driver efm32_uart_reg = { 651 .owner = THIS_MODULE, 652 .driver_name = DRIVER_NAME, 653 .dev_name = DEV_NAME, 654 .nr = ARRAY_SIZE(efm32_uart_ports), 655 .cons = &efm32_uart_console, 656}; 657 658static int efm32_uart_probe_dt(struct platform_device *pdev, 659 struct efm32_uart_port *efm_port) 660{ 661 struct device_node *np = pdev->dev.of_node; 662 u32 location; 663 int ret; 664 665 if (!np) 666 return 1; 667 668 ret = of_property_read_u32(np, "energymicro,location", &location); 669 670 if (ret) 671 /* fall back to wrongly namespaced property */ 672 ret = of_property_read_u32(np, "efm32,location", &location); 673 674 if (ret) 675 /* fall back to old and (wrongly) generic property "location" */ 676 ret = of_property_read_u32(np, "location", &location); 677 678 if (!ret) { 679 if (location > 5) { 680 dev_err(&pdev->dev, "invalid location\n"); 681 return -EINVAL; 682 } 683 efm_debug(efm_port, "using location %u\n", location); 684 efm_port->pdata.location = location; 685 } else { 686 efm_debug(efm_port, "fall back to location 0\n"); 687 } 688 689 ret = of_alias_get_id(np, "serial"); 690 if (ret < 0) { 691 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); 692 return ret; 693 } else { 694 efm_port->port.line = ret; 695 return 0; 696 } 697 698} 699 700static int efm32_uart_probe(struct platform_device *pdev) 701{ 702 struct efm32_uart_port *efm_port; 703 struct resource *res; 704 unsigned int line; 705 int ret; 706 707 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL); 708 if (!efm_port) { 709 dev_dbg(&pdev->dev, "failed to allocate private data\n"); 710 return -ENOMEM; 711 } 712 713 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 714 if (!res) { 715 ret = -ENODEV; 716 dev_dbg(&pdev->dev, "failed to determine base address\n"); 717 goto err_get_base; 718 } 719 720 if (resource_size(res) < 60) { 721 ret = -EINVAL; 722 dev_dbg(&pdev->dev, "memory resource too small\n"); 723 goto err_too_small; 724 } 725 726 ret = platform_get_irq(pdev, 0); 727 if (ret <= 0) { 728 dev_dbg(&pdev->dev, "failed to get rx irq\n"); 729 goto err_get_rxirq; 730 } 731 732 efm_port->port.irq = ret; 733 734 ret = platform_get_irq(pdev, 1); 735 if (ret <= 0) 736 ret = efm_port->port.irq + 1; 737 738 efm_port->txirq = ret; 739 740 efm_port->port.dev = &pdev->dev; 741 efm_port->port.mapbase = res->start; 742 efm_port->port.type = PORT_EFMUART; 743 efm_port->port.iotype = UPIO_MEM32; 744 efm_port->port.fifosize = 2; 745 efm_port->port.ops = &efm32_uart_pops; 746 efm_port->port.flags = UPF_BOOT_AUTOCONF; 747 748 ret = efm32_uart_probe_dt(pdev, efm_port); 749 if (ret > 0) { 750 /* not created by device tree */ 751 const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev); 752 753 efm_port->port.line = pdev->id; 754 755 if (pdata) 756 efm_port->pdata = *pdata; 757 } else if (ret < 0) 758 goto err_probe_dt; 759 760 line = efm_port->port.line; 761 762 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports)) 763 efm32_uart_ports[line] = efm_port; 764 765 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port); 766 if (ret) { 767 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret); 768 769 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports)) 770 efm32_uart_ports[line] = NULL; 771err_probe_dt: 772err_get_rxirq: 773err_too_small: 774err_get_base: 775 kfree(efm_port); 776 } else { 777 platform_set_drvdata(pdev, efm_port); 778 dev_dbg(&pdev->dev, "\\o/\n"); 779 } 780 781 return ret; 782} 783 784static int efm32_uart_remove(struct platform_device *pdev) 785{ 786 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev); 787 unsigned int line = efm_port->port.line; 788 789 uart_remove_one_port(&efm32_uart_reg, &efm_port->port); 790 791 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports)) 792 efm32_uart_ports[line] = NULL; 793 794 kfree(efm_port); 795 796 return 0; 797} 798 799static const struct of_device_id efm32_uart_dt_ids[] = { 800 { 801 .compatible = "energymicro,efm32-uart", 802 }, { 803 /* doesn't follow the "vendor,device" scheme, don't use */ 804 .compatible = "efm32,uart", 805 }, { 806 /* sentinel */ 807 } 808}; 809MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids); 810 811static struct platform_driver efm32_uart_driver = { 812 .probe = efm32_uart_probe, 813 .remove = efm32_uart_remove, 814 815 .driver = { 816 .name = DRIVER_NAME, 817 .owner = THIS_MODULE, 818 .of_match_table = efm32_uart_dt_ids, 819 }, 820}; 821 822static int __init efm32_uart_init(void) 823{ 824 int ret; 825 826 ret = uart_register_driver(&efm32_uart_reg); 827 if (ret) 828 return ret; 829 830 ret = platform_driver_register(&efm32_uart_driver); 831 if (ret) 832 uart_unregister_driver(&efm32_uart_reg); 833 834 pr_info("EFM32 UART/USART driver\n"); 835 836 return ret; 837} 838module_init(efm32_uart_init); 839 840static void __exit efm32_uart_exit(void) 841{ 842 platform_driver_unregister(&efm32_uart_driver); 843 uart_unregister_driver(&efm32_uart_reg); 844} 845module_exit(efm32_uart_exit); 846 847MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>"); 848MODULE_DESCRIPTION("EFM32 UART/USART driver"); 849MODULE_LICENSE("GPL v2"); 850MODULE_ALIAS("platform:" DRIVER_NAME); 851