1/* 2 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 3 * 4 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 8 * Based on max3107.c, by Aavamobile 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16#include <linux/bitops.h> 17#include <linux/clk.h> 18#include <linux/delay.h> 19#include <linux/device.h> 20#include <linux/gpio.h> 21#include <linux/module.h> 22#include <linux/of.h> 23#include <linux/of_device.h> 24#include <linux/regmap.h> 25#include <linux/serial_core.h> 26#include <linux/serial.h> 27#include <linux/tty.h> 28#include <linux/tty_flip.h> 29#include <linux/spi/spi.h> 30#include <linux/uaccess.h> 31 32#define MAX310X_NAME "max310x" 33#define MAX310X_MAJOR 204 34#define MAX310X_MINOR 209 35 36/* MAX310X register definitions */ 37#define MAX310X_RHR_REG (0x00) /* RX FIFO */ 38#define MAX310X_THR_REG (0x00) /* TX FIFO */ 39#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 40#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 41#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 42#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 43#define MAX310X_REG_05 (0x05) 44#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 45#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 46#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 47#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 48#define MAX310X_MODE1_REG (0x09) /* MODE1 */ 49#define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 50#define MAX310X_LCR_REG (0x0b) /* LCR */ 51#define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 52#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 53#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 54#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 55#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 56#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 57#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 58#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 59#define MAX310X_XON1_REG (0x14) /* XON1 character */ 60#define MAX310X_XON2_REG (0x15) /* XON2 character */ 61#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 62#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 63#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 64#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 65#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 66#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 67#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 68#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 69#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 70#define MAX310X_REG_1F (0x1f) 71 72#define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 73 74#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 75#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 76 77/* Extended registers */ 78#define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 79 80/* IRQ register bits */ 81#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 82#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 83#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 84#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 85#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 86#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 87#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 88#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 89 90/* LSR register bits */ 91#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 92#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 93#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 94#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 95#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 96#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 97#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 98 99/* Special character register bits */ 100#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 101#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 102#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 103#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 104#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 105#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 106 107/* Status register bits */ 108#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 109#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 110#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 111#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 112#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 113#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 114 115/* MODE1 register bits */ 116#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 117#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 118#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 119#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 120#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 121#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 122#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 123#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 124 125/* MODE2 register bits */ 126#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 127#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 128#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 129#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 130#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 131#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 132#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 133#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 134 135/* LCR register bits */ 136#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 137#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 138 * 139 * Word length bits table: 140 * 00 -> 5 bit words 141 * 01 -> 6 bit words 142 * 10 -> 7 bit words 143 * 11 -> 8 bit words 144 */ 145#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 146 * 147 * STOP length bit table: 148 * 0 -> 1 stop bit 149 * 1 -> 1-1.5 stop bits if 150 * word length is 5, 151 * 2 stop bits otherwise 152 */ 153#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 154#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 155#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 156#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 157#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 158#define MAX310X_LCR_WORD_LEN_5 (0x00) 159#define MAX310X_LCR_WORD_LEN_6 (0x01) 160#define MAX310X_LCR_WORD_LEN_7 (0x02) 161#define MAX310X_LCR_WORD_LEN_8 (0x03) 162 163/* IRDA register bits */ 164#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 165#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 166 167/* Flow control trigger level register masks */ 168#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 169#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 170#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 171#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 172 173/* FIFO interrupt trigger level register masks */ 174#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 175#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 176#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 177#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 178 179/* Flow control register bits */ 180#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 181#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 182#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 183 * are used in conjunction with 184 * XOFF2 for definition of 185 * special character */ 186#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 187#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 188#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 189 * 190 * SWFLOW bits 1 & 0 table: 191 * 00 -> no transmitter flow 192 * control 193 * 01 -> receiver compares 194 * XON2 and XOFF2 195 * and controls 196 * transmitter 197 * 10 -> receiver compares 198 * XON1 and XOFF1 199 * and controls 200 * transmitter 201 * 11 -> receiver compares 202 * XON1, XON2, XOFF1 and 203 * XOFF2 and controls 204 * transmitter 205 */ 206#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 207#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 208 * 209 * SWFLOW bits 3 & 2 table: 210 * 00 -> no received flow 211 * control 212 * 01 -> transmitter generates 213 * XON2 and XOFF2 214 * 10 -> transmitter generates 215 * XON1 and XOFF1 216 * 11 -> transmitter generates 217 * XON1, XON2, XOFF1 and 218 * XOFF2 219 */ 220 221/* PLL configuration register masks */ 222#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 223#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 224 225/* Baud rate generator configuration register bits */ 226#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 227#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 228 229/* Clock source register bits */ 230#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 231#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 232#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 233#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 234#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 235 236/* Global commands */ 237#define MAX310X_EXTREG_ENBL (0xce) 238#define MAX310X_EXTREG_DSBL (0xcd) 239 240/* Misc definitions */ 241#define MAX310X_FIFO_SIZE (128) 242#define MAX310x_REV_MASK (0xfc) 243 244/* MAX3107 specific */ 245#define MAX3107_REV_ID (0xa0) 246 247/* MAX3109 specific */ 248#define MAX3109_REV_ID (0xc0) 249 250/* MAX14830 specific */ 251#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 252#define MAX14830_REV_ID (0xb0) 253 254struct max310x_devtype { 255 char name[9]; 256 int nr; 257 int (*detect)(struct device *); 258 void (*power)(struct uart_port *, int); 259}; 260 261struct max310x_one { 262 struct uart_port port; 263 struct work_struct tx_work; 264 struct work_struct md_work; 265}; 266 267struct max310x_port { 268 struct uart_driver uart; 269 struct max310x_devtype *devtype; 270 struct regmap *regmap; 271 struct mutex mutex; 272 struct clk *clk; 273#ifdef CONFIG_GPIOLIB 274 struct gpio_chip gpio; 275#endif 276 struct max310x_one p[0]; 277}; 278 279static u8 max310x_port_read(struct uart_port *port, u8 reg) 280{ 281 struct max310x_port *s = dev_get_drvdata(port->dev); 282 unsigned int val = 0; 283 284 regmap_read(s->regmap, port->iobase + reg, &val); 285 286 return val; 287} 288 289static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 290{ 291 struct max310x_port *s = dev_get_drvdata(port->dev); 292 293 regmap_write(s->regmap, port->iobase + reg, val); 294} 295 296static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 297{ 298 struct max310x_port *s = dev_get_drvdata(port->dev); 299 300 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); 301} 302 303static int max3107_detect(struct device *dev) 304{ 305 struct max310x_port *s = dev_get_drvdata(dev); 306 unsigned int val = 0; 307 int ret; 308 309 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 310 if (ret) 311 return ret; 312 313 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 314 dev_err(dev, 315 "%s ID 0x%02x does not match\n", s->devtype->name, val); 316 return -ENODEV; 317 } 318 319 return 0; 320} 321 322static int max3108_detect(struct device *dev) 323{ 324 struct max310x_port *s = dev_get_drvdata(dev); 325 unsigned int val = 0; 326 int ret; 327 328 /* MAX3108 have not REV ID register, we just check default value 329 * from clocksource register to make sure everything works. 330 */ 331 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 332 if (ret) 333 return ret; 334 335 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 336 dev_err(dev, "%s not present\n", s->devtype->name); 337 return -ENODEV; 338 } 339 340 return 0; 341} 342 343static int max3109_detect(struct device *dev) 344{ 345 struct max310x_port *s = dev_get_drvdata(dev); 346 unsigned int val = 0; 347 int ret; 348 349 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 350 if (ret) 351 return ret; 352 353 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 354 dev_err(dev, 355 "%s ID 0x%02x does not match\n", s->devtype->name, val); 356 return -ENODEV; 357 } 358 359 return 0; 360} 361 362static void max310x_power(struct uart_port *port, int on) 363{ 364 max310x_port_update(port, MAX310X_MODE1_REG, 365 MAX310X_MODE1_FORCESLEEP_BIT, 366 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 367 if (on) 368 msleep(50); 369} 370 371static int max14830_detect(struct device *dev) 372{ 373 struct max310x_port *s = dev_get_drvdata(dev); 374 unsigned int val = 0; 375 int ret; 376 377 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 378 MAX310X_EXTREG_ENBL); 379 if (ret) 380 return ret; 381 382 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 383 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 384 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 385 dev_err(dev, 386 "%s ID 0x%02x does not match\n", s->devtype->name, val); 387 return -ENODEV; 388 } 389 390 return 0; 391} 392 393static void max14830_power(struct uart_port *port, int on) 394{ 395 max310x_port_update(port, MAX310X_BRGCFG_REG, 396 MAX14830_BRGCFG_CLKDIS_BIT, 397 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 398 if (on) 399 msleep(50); 400} 401 402static const struct max310x_devtype max3107_devtype = { 403 .name = "MAX3107", 404 .nr = 1, 405 .detect = max3107_detect, 406 .power = max310x_power, 407}; 408 409static const struct max310x_devtype max3108_devtype = { 410 .name = "MAX3108", 411 .nr = 1, 412 .detect = max3108_detect, 413 .power = max310x_power, 414}; 415 416static const struct max310x_devtype max3109_devtype = { 417 .name = "MAX3109", 418 .nr = 2, 419 .detect = max3109_detect, 420 .power = max310x_power, 421}; 422 423static const struct max310x_devtype max14830_devtype = { 424 .name = "MAX14830", 425 .nr = 4, 426 .detect = max14830_detect, 427 .power = max14830_power, 428}; 429 430static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 431{ 432 switch (reg & 0x1f) { 433 case MAX310X_IRQSTS_REG: 434 case MAX310X_LSR_IRQSTS_REG: 435 case MAX310X_SPCHR_IRQSTS_REG: 436 case MAX310X_STS_IRQSTS_REG: 437 case MAX310X_TXFIFOLVL_REG: 438 case MAX310X_RXFIFOLVL_REG: 439 return false; 440 default: 441 break; 442 } 443 444 return true; 445} 446 447static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 448{ 449 switch (reg & 0x1f) { 450 case MAX310X_RHR_REG: 451 case MAX310X_IRQSTS_REG: 452 case MAX310X_LSR_IRQSTS_REG: 453 case MAX310X_SPCHR_IRQSTS_REG: 454 case MAX310X_STS_IRQSTS_REG: 455 case MAX310X_TXFIFOLVL_REG: 456 case MAX310X_RXFIFOLVL_REG: 457 case MAX310X_GPIODATA_REG: 458 case MAX310X_BRGDIVLSB_REG: 459 case MAX310X_REG_05: 460 case MAX310X_REG_1F: 461 return true; 462 default: 463 break; 464 } 465 466 return false; 467} 468 469static bool max310x_reg_precious(struct device *dev, unsigned int reg) 470{ 471 switch (reg & 0x1f) { 472 case MAX310X_RHR_REG: 473 case MAX310X_IRQSTS_REG: 474 case MAX310X_SPCHR_IRQSTS_REG: 475 case MAX310X_STS_IRQSTS_REG: 476 return true; 477 default: 478 break; 479 } 480 481 return false; 482} 483 484static int max310x_set_baud(struct uart_port *port, int baud) 485{ 486 unsigned int mode = 0, clk = port->uartclk, div = clk / baud; 487 488 /* Check for minimal value for divider */ 489 if (div < 16) 490 div = 16; 491 492 if (clk % baud && (div / 16) < 0x8000) { 493 /* Mode x2 */ 494 mode = MAX310X_BRGCFG_2XMODE_BIT; 495 clk = port->uartclk * 2; 496 div = clk / baud; 497 498 if (clk % baud && (div / 16) < 0x8000) { 499 /* Mode x4 */ 500 mode = MAX310X_BRGCFG_4XMODE_BIT; 501 clk = port->uartclk * 4; 502 div = clk / baud; 503 } 504 } 505 506 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); 507 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); 508 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); 509 510 return DIV_ROUND_CLOSEST(clk, div); 511} 512 513static int max310x_update_best_err(unsigned long f, long *besterr) 514{ 515 /* Use baudrate 115200 for calculate error */ 516 long err = f % (115200 * 16); 517 518 if ((*besterr < 0) || (*besterr > err)) { 519 *besterr = err; 520 return 0; 521 } 522 523 return 1; 524} 525 526static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq, 527 bool xtal) 528{ 529 unsigned int div, clksrc, pllcfg = 0; 530 long besterr = -1; 531 unsigned long fdiv, fmul, bestfreq = freq; 532 533 /* First, update error without PLL */ 534 max310x_update_best_err(freq, &besterr); 535 536 /* Try all possible PLL dividers */ 537 for (div = 1; (div <= 63) && besterr; div++) { 538 fdiv = DIV_ROUND_CLOSEST(freq, div); 539 540 /* Try multiplier 6 */ 541 fmul = fdiv * 6; 542 if ((fdiv >= 500000) && (fdiv <= 800000)) 543 if (!max310x_update_best_err(fmul, &besterr)) { 544 pllcfg = (0 << 6) | div; 545 bestfreq = fmul; 546 } 547 /* Try multiplier 48 */ 548 fmul = fdiv * 48; 549 if ((fdiv >= 850000) && (fdiv <= 1200000)) 550 if (!max310x_update_best_err(fmul, &besterr)) { 551 pllcfg = (1 << 6) | div; 552 bestfreq = fmul; 553 } 554 /* Try multiplier 96 */ 555 fmul = fdiv * 96; 556 if ((fdiv >= 425000) && (fdiv <= 1000000)) 557 if (!max310x_update_best_err(fmul, &besterr)) { 558 pllcfg = (2 << 6) | div; 559 bestfreq = fmul; 560 } 561 /* Try multiplier 144 */ 562 fmul = fdiv * 144; 563 if ((fdiv >= 390000) && (fdiv <= 667000)) 564 if (!max310x_update_best_err(fmul, &besterr)) { 565 pllcfg = (3 << 6) | div; 566 bestfreq = fmul; 567 } 568 } 569 570 /* Configure clock source */ 571 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT; 572 573 /* Configure PLL */ 574 if (pllcfg) { 575 clksrc |= MAX310X_CLKSRC_PLL_BIT; 576 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 577 } else 578 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 579 580 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 581 582 /* Wait for crystal */ 583 if (pllcfg && xtal) 584 msleep(10); 585 586 return (int)bestfreq; 587} 588 589static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 590{ 591 unsigned int sts, ch, flag; 592 593 if (unlikely(rxlen >= port->fifosize)) { 594 dev_warn_ratelimited(port->dev, 595 "Port %i: Possible RX FIFO overrun\n", 596 port->line); 597 port->icount.buf_overrun++; 598 /* Ensure sanity of RX level */ 599 rxlen = port->fifosize; 600 } 601 602 while (rxlen--) { 603 ch = max310x_port_read(port, MAX310X_RHR_REG); 604 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 605 606 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 607 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 608 609 port->icount.rx++; 610 flag = TTY_NORMAL; 611 612 if (unlikely(sts)) { 613 if (sts & MAX310X_LSR_RXBRK_BIT) { 614 port->icount.brk++; 615 if (uart_handle_break(port)) 616 continue; 617 } else if (sts & MAX310X_LSR_RXPAR_BIT) 618 port->icount.parity++; 619 else if (sts & MAX310X_LSR_FRERR_BIT) 620 port->icount.frame++; 621 else if (sts & MAX310X_LSR_RXOVR_BIT) 622 port->icount.overrun++; 623 624 sts &= port->read_status_mask; 625 if (sts & MAX310X_LSR_RXBRK_BIT) 626 flag = TTY_BREAK; 627 else if (sts & MAX310X_LSR_RXPAR_BIT) 628 flag = TTY_PARITY; 629 else if (sts & MAX310X_LSR_FRERR_BIT) 630 flag = TTY_FRAME; 631 else if (sts & MAX310X_LSR_RXOVR_BIT) 632 flag = TTY_OVERRUN; 633 } 634 635 if (uart_handle_sysrq_char(port, ch)) 636 continue; 637 638 if (sts & port->ignore_status_mask) 639 continue; 640 641 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 642 } 643 644 tty_flip_buffer_push(&port->state->port); 645} 646 647static void max310x_handle_tx(struct uart_port *port) 648{ 649 struct circ_buf *xmit = &port->state->xmit; 650 unsigned int txlen, to_send; 651 652 if (unlikely(port->x_char)) { 653 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 654 port->icount.tx++; 655 port->x_char = 0; 656 return; 657 } 658 659 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 660 return; 661 662 /* Get length of data pending in circular buffer */ 663 to_send = uart_circ_chars_pending(xmit); 664 if (likely(to_send)) { 665 /* Limit to size of TX FIFO */ 666 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 667 txlen = port->fifosize - txlen; 668 to_send = (to_send > txlen) ? txlen : to_send; 669 670 /* Add data to send */ 671 port->icount.tx += to_send; 672 while (to_send--) { 673 max310x_port_write(port, MAX310X_THR_REG, 674 xmit->buf[xmit->tail]); 675 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 676 } 677 } 678 679 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 680 uart_write_wakeup(port); 681} 682 683static void max310x_port_irq(struct max310x_port *s, int portno) 684{ 685 struct uart_port *port = &s->p[portno].port; 686 687 do { 688 unsigned int ists, lsr, rxlen; 689 690 /* Read IRQ status & RX FIFO level */ 691 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 692 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 693 if (!ists && !rxlen) 694 break; 695 696 if (ists & MAX310X_IRQ_CTS_BIT) { 697 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 698 uart_handle_cts_change(port, 699 !!(lsr & MAX310X_LSR_CTS_BIT)); 700 } 701 if (rxlen) 702 max310x_handle_rx(port, rxlen); 703 if (ists & MAX310X_IRQ_TXEMPTY_BIT) { 704 mutex_lock(&s->mutex); 705 max310x_handle_tx(port); 706 mutex_unlock(&s->mutex); 707 } 708 } while (1); 709} 710 711static irqreturn_t max310x_ist(int irq, void *dev_id) 712{ 713 struct max310x_port *s = (struct max310x_port *)dev_id; 714 715 if (s->uart.nr > 1) { 716 do { 717 unsigned int val = ~0; 718 719 WARN_ON_ONCE(regmap_read(s->regmap, 720 MAX310X_GLOBALIRQ_REG, &val)); 721 val = ((1 << s->uart.nr) - 1) & ~val; 722 if (!val) 723 break; 724 max310x_port_irq(s, fls(val) - 1); 725 } while (1); 726 } else 727 max310x_port_irq(s, 0); 728 729 return IRQ_HANDLED; 730} 731 732static void max310x_wq_proc(struct work_struct *ws) 733{ 734 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 735 struct max310x_port *s = dev_get_drvdata(one->port.dev); 736 737 mutex_lock(&s->mutex); 738 max310x_handle_tx(&one->port); 739 mutex_unlock(&s->mutex); 740} 741 742static void max310x_start_tx(struct uart_port *port) 743{ 744 struct max310x_one *one = container_of(port, struct max310x_one, port); 745 746 if (!work_pending(&one->tx_work)) 747 schedule_work(&one->tx_work); 748} 749 750static unsigned int max310x_tx_empty(struct uart_port *port) 751{ 752 unsigned int lvl, sts; 753 754 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 755 sts = max310x_port_read(port, MAX310X_IRQSTS_REG); 756 757 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0; 758} 759 760static unsigned int max310x_get_mctrl(struct uart_port *port) 761{ 762 /* DCD and DSR are not wired and CTS/RTS is handled automatically 763 * so just indicate DSR and CAR asserted 764 */ 765 return TIOCM_DSR | TIOCM_CAR; 766} 767 768static void max310x_md_proc(struct work_struct *ws) 769{ 770 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 771 772 max310x_port_update(&one->port, MAX310X_MODE2_REG, 773 MAX310X_MODE2_LOOPBACK_BIT, 774 (one->port.mctrl & TIOCM_LOOP) ? 775 MAX310X_MODE2_LOOPBACK_BIT : 0); 776} 777 778static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 779{ 780 struct max310x_one *one = container_of(port, struct max310x_one, port); 781 782 schedule_work(&one->md_work); 783} 784 785static void max310x_break_ctl(struct uart_port *port, int break_state) 786{ 787 max310x_port_update(port, MAX310X_LCR_REG, 788 MAX310X_LCR_TXBREAK_BIT, 789 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 790} 791 792static void max310x_set_termios(struct uart_port *port, 793 struct ktermios *termios, 794 struct ktermios *old) 795{ 796 unsigned int lcr, flow = 0; 797 int baud; 798 799 /* Mask termios capabilities we don't support */ 800 termios->c_cflag &= ~CMSPAR; 801 802 /* Word size */ 803 switch (termios->c_cflag & CSIZE) { 804 case CS5: 805 lcr = MAX310X_LCR_WORD_LEN_5; 806 break; 807 case CS6: 808 lcr = MAX310X_LCR_WORD_LEN_6; 809 break; 810 case CS7: 811 lcr = MAX310X_LCR_WORD_LEN_7; 812 break; 813 case CS8: 814 default: 815 lcr = MAX310X_LCR_WORD_LEN_8; 816 break; 817 } 818 819 /* Parity */ 820 if (termios->c_cflag & PARENB) { 821 lcr |= MAX310X_LCR_PARITY_BIT; 822 if (!(termios->c_cflag & PARODD)) 823 lcr |= MAX310X_LCR_EVENPARITY_BIT; 824 } 825 826 /* Stop bits */ 827 if (termios->c_cflag & CSTOPB) 828 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 829 830 /* Update LCR register */ 831 max310x_port_write(port, MAX310X_LCR_REG, lcr); 832 833 /* Set read status mask */ 834 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 835 if (termios->c_iflag & INPCK) 836 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 837 MAX310X_LSR_FRERR_BIT; 838 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 839 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 840 841 /* Set status ignore mask */ 842 port->ignore_status_mask = 0; 843 if (termios->c_iflag & IGNBRK) 844 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 845 if (!(termios->c_cflag & CREAD)) 846 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 847 MAX310X_LSR_RXOVR_BIT | 848 MAX310X_LSR_FRERR_BIT | 849 MAX310X_LSR_RXBRK_BIT; 850 851 /* Configure flow control */ 852 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 853 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 854 if (termios->c_cflag & CRTSCTS) 855 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 856 MAX310X_FLOWCTRL_AUTORTS_BIT; 857 if (termios->c_iflag & IXON) 858 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 859 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 860 if (termios->c_iflag & IXOFF) 861 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 862 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 863 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 864 865 /* Get baud rate generator configuration */ 866 baud = uart_get_baud_rate(port, termios, old, 867 port->uartclk / 16 / 0xffff, 868 port->uartclk / 4); 869 870 /* Setup baudrate generator */ 871 baud = max310x_set_baud(port, baud); 872 873 /* Update timeout according to new baud rate */ 874 uart_update_timeout(port, termios->c_cflag, baud); 875} 876 877static int max310x_ioctl(struct uart_port *port, unsigned int cmd, 878 unsigned long arg) 879{ 880#if defined(TIOCSRS485) && defined(TIOCGRS485) 881 struct serial_rs485 rs485; 882 unsigned int val; 883 884 switch (cmd) { 885 case TIOCSRS485: 886 if (copy_from_user(&rs485, (void __user *)arg, sizeof(rs485))) 887 return -EFAULT; 888 if (rs485.delay_rts_before_send > 0x0f || 889 rs485.delay_rts_after_send > 0x0f) 890 return -ERANGE; 891 val = (rs485.delay_rts_before_send << 4) | 892 rs485.delay_rts_after_send; 893 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 894 if (rs485.flags & SER_RS485_ENABLED) { 895 max310x_port_update(port, MAX310X_MODE1_REG, 896 MAX310X_MODE1_TRNSCVCTRL_BIT, 897 MAX310X_MODE1_TRNSCVCTRL_BIT); 898 max310x_port_update(port, MAX310X_MODE2_REG, 899 MAX310X_MODE2_ECHOSUPR_BIT, 900 MAX310X_MODE2_ECHOSUPR_BIT); 901 } else { 902 max310x_port_update(port, MAX310X_MODE1_REG, 903 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 904 max310x_port_update(port, MAX310X_MODE2_REG, 905 MAX310X_MODE2_ECHOSUPR_BIT, 0); 906 } 907 return 0; 908 case TIOCGRS485: 909 memset(&rs485, 0, sizeof(rs485)); 910 val = max310x_port_read(port, MAX310X_MODE1_REG); 911 rs485.flags = (val & MAX310X_MODE1_TRNSCVCTRL_BIT) ? 912 SER_RS485_ENABLED : 0; 913 rs485.flags |= SER_RS485_RTS_ON_SEND; 914 val = max310x_port_read(port, MAX310X_HDPIXDELAY_REG); 915 rs485.delay_rts_before_send = val >> 4; 916 rs485.delay_rts_after_send = val & 0x0f; 917 if (copy_to_user((void __user *)arg, &rs485, sizeof(rs485))) 918 return -EFAULT; 919 return 0; 920 default: 921 break; 922 } 923#endif 924 925 return -ENOIOCTLCMD; 926} 927 928static int max310x_startup(struct uart_port *port) 929{ 930 struct max310x_port *s = dev_get_drvdata(port->dev); 931 unsigned int val; 932 933 s->devtype->power(port, 1); 934 935 /* Configure MODE1 register */ 936 max310x_port_update(port, MAX310X_MODE1_REG, 937 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 938 939 /* Configure MODE2 register & Reset FIFOs*/ 940 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 941 max310x_port_write(port, MAX310X_MODE2_REG, val); 942 max310x_port_update(port, MAX310X_MODE2_REG, 943 MAX310X_MODE2_FIFORST_BIT, 0); 944 945 /* Configure flow control levels */ 946 /* Flow control halt level 96, resume level 48 */ 947 max310x_port_write(port, MAX310X_FLOWLVL_REG, 948 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 949 950 /* Clear IRQ status register */ 951 max310x_port_read(port, MAX310X_IRQSTS_REG); 952 953 /* Enable RX, TX, CTS change interrupts */ 954 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 955 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 956 957 return 0; 958} 959 960static void max310x_shutdown(struct uart_port *port) 961{ 962 struct max310x_port *s = dev_get_drvdata(port->dev); 963 964 /* Disable all interrupts */ 965 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 966 967 s->devtype->power(port, 0); 968} 969 970static const char *max310x_type(struct uart_port *port) 971{ 972 struct max310x_port *s = dev_get_drvdata(port->dev); 973 974 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 975} 976 977static int max310x_request_port(struct uart_port *port) 978{ 979 /* Do nothing */ 980 return 0; 981} 982 983static void max310x_config_port(struct uart_port *port, int flags) 984{ 985 if (flags & UART_CONFIG_TYPE) 986 port->type = PORT_MAX310X; 987} 988 989static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 990{ 991 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 992 return -EINVAL; 993 if (s->irq != port->irq) 994 return -EINVAL; 995 996 return 0; 997} 998 999static void max310x_null_void(struct uart_port *port) 1000{ 1001 /* Do nothing */ 1002} 1003 1004static const struct uart_ops max310x_ops = { 1005 .tx_empty = max310x_tx_empty, 1006 .set_mctrl = max310x_set_mctrl, 1007 .get_mctrl = max310x_get_mctrl, 1008 .stop_tx = max310x_null_void, 1009 .start_tx = max310x_start_tx, 1010 .stop_rx = max310x_null_void, 1011 .break_ctl = max310x_break_ctl, 1012 .startup = max310x_startup, 1013 .shutdown = max310x_shutdown, 1014 .set_termios = max310x_set_termios, 1015 .type = max310x_type, 1016 .request_port = max310x_request_port, 1017 .release_port = max310x_null_void, 1018 .config_port = max310x_config_port, 1019 .verify_port = max310x_verify_port, 1020 .ioctl = max310x_ioctl, 1021}; 1022 1023static int __maybe_unused max310x_suspend(struct device *dev) 1024{ 1025 struct max310x_port *s = dev_get_drvdata(dev); 1026 int i; 1027 1028 for (i = 0; i < s->uart.nr; i++) { 1029 uart_suspend_port(&s->uart, &s->p[i].port); 1030 s->devtype->power(&s->p[i].port, 0); 1031 } 1032 1033 return 0; 1034} 1035 1036static int __maybe_unused max310x_resume(struct device *dev) 1037{ 1038 struct max310x_port *s = dev_get_drvdata(dev); 1039 int i; 1040 1041 for (i = 0; i < s->uart.nr; i++) { 1042 s->devtype->power(&s->p[i].port, 1); 1043 uart_resume_port(&s->uart, &s->p[i].port); 1044 } 1045 1046 return 0; 1047} 1048 1049static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1050 1051#ifdef CONFIG_GPIOLIB 1052static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1053{ 1054 unsigned int val; 1055 struct max310x_port *s = container_of(chip, struct max310x_port, gpio); 1056 struct uart_port *port = &s->p[offset / 4].port; 1057 1058 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1059 1060 return !!((val >> 4) & (1 << (offset % 4))); 1061} 1062 1063static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1064{ 1065 struct max310x_port *s = container_of(chip, struct max310x_port, gpio); 1066 struct uart_port *port = &s->p[offset / 4].port; 1067 1068 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1069 value ? 1 << (offset % 4) : 0); 1070} 1071 1072static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1073{ 1074 struct max310x_port *s = container_of(chip, struct max310x_port, gpio); 1075 struct uart_port *port = &s->p[offset / 4].port; 1076 1077 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1078 1079 return 0; 1080} 1081 1082static int max310x_gpio_direction_output(struct gpio_chip *chip, 1083 unsigned offset, int value) 1084{ 1085 struct max310x_port *s = container_of(chip, struct max310x_port, gpio); 1086 struct uart_port *port = &s->p[offset / 4].port; 1087 1088 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1089 value ? 1 << (offset % 4) : 0); 1090 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1091 1 << (offset % 4)); 1092 1093 return 0; 1094} 1095#endif 1096 1097static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, 1098 struct regmap *regmap, int irq, unsigned long flags) 1099{ 1100 int i, ret, fmin, fmax, freq, uartclk; 1101 struct clk *clk_osc, *clk_xtal; 1102 struct max310x_port *s; 1103 bool xtal = false; 1104 1105 if (IS_ERR(regmap)) 1106 return PTR_ERR(regmap); 1107 1108 /* Alloc port structure */ 1109 s = devm_kzalloc(dev, sizeof(*s) + 1110 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL); 1111 if (!s) { 1112 dev_err(dev, "Error allocating port structure\n"); 1113 return -ENOMEM; 1114 } 1115 1116 clk_osc = devm_clk_get(dev, "osc"); 1117 clk_xtal = devm_clk_get(dev, "xtal"); 1118 if (!IS_ERR(clk_osc)) { 1119 s->clk = clk_osc; 1120 fmin = 500000; 1121 fmax = 35000000; 1122 } else if (!IS_ERR(clk_xtal)) { 1123 s->clk = clk_xtal; 1124 fmin = 1000000; 1125 fmax = 4000000; 1126 xtal = true; 1127 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || 1128 PTR_ERR(clk_xtal) == -EPROBE_DEFER) { 1129 return -EPROBE_DEFER; 1130 } else { 1131 dev_err(dev, "Cannot get clock\n"); 1132 return -EINVAL; 1133 } 1134 1135 ret = clk_prepare_enable(s->clk); 1136 if (ret) 1137 return ret; 1138 1139 freq = clk_get_rate(s->clk); 1140 /* Check frequency limits */ 1141 if (freq < fmin || freq > fmax) { 1142 ret = -ERANGE; 1143 goto out_clk; 1144 } 1145 1146 s->regmap = regmap; 1147 s->devtype = devtype; 1148 dev_set_drvdata(dev, s); 1149 1150 /* Check device to ensure we are talking to what we expect */ 1151 ret = devtype->detect(dev); 1152 if (ret) 1153 goto out_clk; 1154 1155 for (i = 0; i < devtype->nr; i++) { 1156 unsigned int offs = i << 5; 1157 1158 /* Reset port */ 1159 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 1160 MAX310X_MODE2_RST_BIT); 1161 /* Clear port reset */ 1162 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); 1163 1164 /* Wait for port startup */ 1165 do { 1166 regmap_read(s->regmap, 1167 MAX310X_BRGDIVLSB_REG + offs, &ret); 1168 } while (ret != 0x01); 1169 1170 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs, 1171 MAX310X_MODE1_AUTOSLEEP_BIT, 1172 MAX310X_MODE1_AUTOSLEEP_BIT); 1173 } 1174 1175 uartclk = max310x_set_ref_clk(s, freq, xtal); 1176 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1177 1178 /* Register UART driver */ 1179 s->uart.owner = THIS_MODULE; 1180 s->uart.dev_name = "ttyMAX"; 1181 s->uart.major = MAX310X_MAJOR; 1182 s->uart.minor = MAX310X_MINOR; 1183 s->uart.nr = devtype->nr; 1184 ret = uart_register_driver(&s->uart); 1185 if (ret) { 1186 dev_err(dev, "Registering UART driver failed\n"); 1187 goto out_clk; 1188 } 1189 1190#ifdef CONFIG_GPIOLIB 1191 /* Setup GPIO cotroller */ 1192 s->gpio.owner = THIS_MODULE; 1193 s->gpio.dev = dev; 1194 s->gpio.label = dev_name(dev); 1195 s->gpio.direction_input = max310x_gpio_direction_input; 1196 s->gpio.get = max310x_gpio_get; 1197 s->gpio.direction_output= max310x_gpio_direction_output; 1198 s->gpio.set = max310x_gpio_set; 1199 s->gpio.base = -1; 1200 s->gpio.ngpio = devtype->nr * 4; 1201 s->gpio.can_sleep = 1; 1202 ret = gpiochip_add(&s->gpio); 1203 if (ret) 1204 goto out_uart; 1205#endif 1206 1207 mutex_init(&s->mutex); 1208 1209 for (i = 0; i < devtype->nr; i++) { 1210 /* Initialize port data */ 1211 s->p[i].port.line = i; 1212 s->p[i].port.dev = dev; 1213 s->p[i].port.irq = irq; 1214 s->p[i].port.type = PORT_MAX310X; 1215 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1216 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1217 s->p[i].port.iotype = UPIO_PORT; 1218 s->p[i].port.iobase = i * 0x20; 1219 s->p[i].port.membase = (void __iomem *)~0; 1220 s->p[i].port.uartclk = uartclk; 1221 s->p[i].port.ops = &max310x_ops; 1222 /* Disable all interrupts */ 1223 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1224 /* Clear IRQ status register */ 1225 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1226 /* Enable IRQ pin */ 1227 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG, 1228 MAX310X_MODE1_IRQSEL_BIT, 1229 MAX310X_MODE1_IRQSEL_BIT); 1230 /* Initialize queue for start TX */ 1231 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc); 1232 /* Initialize queue for changing mode */ 1233 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1234 /* Register port */ 1235 uart_add_one_port(&s->uart, &s->p[i].port); 1236 /* Go to suspend mode */ 1237 devtype->power(&s->p[i].port, 0); 1238 } 1239 1240 /* Setup interrupt */ 1241 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1242 IRQF_ONESHOT | flags, dev_name(dev), s); 1243 if (!ret) 1244 return 0; 1245 1246 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1247 1248 mutex_destroy(&s->mutex); 1249 1250#ifdef CONFIG_GPIOLIB 1251 gpiochip_remove(&s->gpio); 1252 1253out_uart: 1254#endif 1255 uart_unregister_driver(&s->uart); 1256 1257out_clk: 1258 clk_disable_unprepare(s->clk); 1259 1260 return ret; 1261} 1262 1263static int max310x_remove(struct device *dev) 1264{ 1265 struct max310x_port *s = dev_get_drvdata(dev); 1266 int i; 1267 1268#ifdef CONFIG_GPIOLIB 1269 gpiochip_remove(&s->gpio); 1270#endif 1271 1272 for (i = 0; i < s->uart.nr; i++) { 1273 cancel_work_sync(&s->p[i].tx_work); 1274 cancel_work_sync(&s->p[i].md_work); 1275 uart_remove_one_port(&s->uart, &s->p[i].port); 1276 s->devtype->power(&s->p[i].port, 0); 1277 } 1278 1279 mutex_destroy(&s->mutex); 1280 uart_unregister_driver(&s->uart); 1281 clk_disable_unprepare(s->clk); 1282 1283 return 0; 1284} 1285 1286static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1287 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1288 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1289 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1290 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1291 { } 1292}; 1293MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1294 1295static struct regmap_config regcfg = { 1296 .reg_bits = 8, 1297 .val_bits = 8, 1298 .write_flag_mask = 0x80, 1299 .cache_type = REGCACHE_RBTREE, 1300 .writeable_reg = max310x_reg_writeable, 1301 .volatile_reg = max310x_reg_volatile, 1302 .precious_reg = max310x_reg_precious, 1303}; 1304 1305#ifdef CONFIG_SPI_MASTER 1306static int max310x_spi_probe(struct spi_device *spi) 1307{ 1308 struct max310x_devtype *devtype; 1309 unsigned long flags = 0; 1310 struct regmap *regmap; 1311 int ret; 1312 1313 /* Setup SPI bus */ 1314 spi->bits_per_word = 8; 1315 spi->mode = spi->mode ? : SPI_MODE_0; 1316 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1317 ret = spi_setup(spi); 1318 if (ret) 1319 return ret; 1320 1321 if (spi->dev.of_node) { 1322 const struct of_device_id *of_id = 1323 of_match_device(max310x_dt_ids, &spi->dev); 1324 1325 devtype = (struct max310x_devtype *)of_id->data; 1326 } else { 1327 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1328 1329 devtype = (struct max310x_devtype *)id_entry->driver_data; 1330 flags = IRQF_TRIGGER_FALLING; 1331 } 1332 1333 regcfg.max_register = devtype->nr * 0x20 - 1; 1334 regmap = devm_regmap_init_spi(spi, ®cfg); 1335 1336 return max310x_probe(&spi->dev, devtype, regmap, spi->irq, flags); 1337} 1338 1339static int max310x_spi_remove(struct spi_device *spi) 1340{ 1341 return max310x_remove(&spi->dev); 1342} 1343 1344static const struct spi_device_id max310x_id_table[] = { 1345 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1346 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1347 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1348 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1349 { } 1350}; 1351MODULE_DEVICE_TABLE(spi, max310x_id_table); 1352 1353static struct spi_driver max310x_uart_driver = { 1354 .driver = { 1355 .name = MAX310X_NAME, 1356 .owner = THIS_MODULE, 1357 .of_match_table = of_match_ptr(max310x_dt_ids), 1358 .pm = &max310x_pm_ops, 1359 }, 1360 .probe = max310x_spi_probe, 1361 .remove = max310x_spi_remove, 1362 .id_table = max310x_id_table, 1363}; 1364module_spi_driver(max310x_uart_driver); 1365#endif 1366 1367MODULE_LICENSE("GPL"); 1368MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1369MODULE_DESCRIPTION("MAX310X serial driver"); 1370