1/* 2 * Cadence UART driver (found in Xilinx Zynq) 3 * 4 * 2011 - 2014 (C) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 13 * still shows in the naming of this file, the kconfig symbols and some symbols 14 * in the code. 15 */ 16 17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18#define SUPPORT_SYSRQ 19#endif 20 21#include <linux/platform_device.h> 22#include <linux/serial.h> 23#include <linux/console.h> 24#include <linux/serial_core.h> 25#include <linux/slab.h> 26#include <linux/tty.h> 27#include <linux/tty_flip.h> 28#include <linux/clk.h> 29#include <linux/irq.h> 30#include <linux/io.h> 31#include <linux/of.h> 32#include <linux/module.h> 33 34#define CDNS_UART_TTY_NAME "ttyPS" 35#define CDNS_UART_NAME "xuartps" 36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 38#define CDNS_UART_NR_PORTS 2 39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 40#define CDNS_UART_REGISTER_SPACE 0xFFF 41 42#define cdns_uart_readl(offset) ioread32(port->membase + offset) 43#define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset) 44 45/* Rx Trigger level */ 46static int rx_trigger_level = 56; 47module_param(rx_trigger_level, uint, S_IRUGO); 48MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 49 50/* Rx Timeout */ 51static int rx_timeout = 10; 52module_param(rx_timeout, uint, S_IRUGO); 53MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 54 55/* Register offsets for the UART. */ 56#define CDNS_UART_CR_OFFSET 0x00 /* Control Register */ 57#define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */ 58#define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */ 59#define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */ 60#define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */ 61#define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */ 62#define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */ 63#define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */ 64#define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */ 65#define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */ 66#define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */ 67#define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */ 68#define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */ 69#define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */ 70#define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */ 71#define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */ 72#define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */ 73#define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */ 74 75/* Control Register Bit Definitions */ 76#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 77#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 78#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 79#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 80#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 81#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 82#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 83#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 84#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 85 86/* 87 * Mode Register: 88 * The mode register (MR) defines the mode of transfer as well as the data 89 * format. If this register is modified during transmission or reception, 90 * data validity cannot be guaranteed. 91 */ 92#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 93#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 94#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 95 96#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 97#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 98 99#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 100#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 101#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 102#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 103#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 104 105#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 106#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 107#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 108 109/* 110 * Interrupt Registers: 111 * Interrupt control logic uses the interrupt enable register (IER) and the 112 * interrupt disable register (IDR) to set the value of the bits in the 113 * interrupt mask register (IMR). The IMR determines whether to pass an 114 * interrupt to the interrupt status register (ISR). 115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 116 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 117 * Reading either IER or IDR returns 0x00. 118 * All four registers have the same bit definitions. 119 */ 120#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 121#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 122#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 123#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 124#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 125#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 126#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 127#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 128#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 129#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 130#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ 131 132/* Goes in read_status_mask for break detection as the HW doesn't do it*/ 133#define CDNS_UART_IXR_BRK 0x80000000 134 135/* 136 * Channel Status Register: 137 * The channel status register (CSR) is provided to enable the control logic 138 * to monitor the status of bits in the channel interrupt status register, 139 * even if these are masked out by the interrupt mask register. 140 */ 141#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 142#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 143#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 144#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 145 146/* baud dividers min/max values */ 147#define CDNS_UART_BDIV_MIN 4 148#define CDNS_UART_BDIV_MAX 255 149#define CDNS_UART_CD_MAX 65535 150 151/** 152 * struct cdns_uart - device data 153 * @port: Pointer to the UART port 154 * @uartclk: Reference clock 155 * @pclk: APB clock 156 * @baud: Current baud rate 157 * @clk_rate_change_nb: Notifier block for clock changes 158 */ 159struct cdns_uart { 160 struct uart_port *port; 161 struct clk *uartclk; 162 struct clk *pclk; 163 unsigned int baud; 164 struct notifier_block clk_rate_change_nb; 165}; 166#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 167 clk_rate_change_nb); 168 169/** 170 * cdns_uart_isr - Interrupt handler 171 * @irq: Irq number 172 * @dev_id: Id of the port 173 * 174 * Return: IRQHANDLED 175 */ 176static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 177{ 178 struct uart_port *port = (struct uart_port *)dev_id; 179 unsigned long flags; 180 unsigned int isrstatus, numbytes; 181 unsigned int data; 182 char status = TTY_NORMAL; 183 184 spin_lock_irqsave(&port->lock, flags); 185 186 /* Read the interrupt status register to determine which 187 * interrupt(s) is/are active. 188 */ 189 isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET); 190 191 /* 192 * There is no hardware break detection, so we interpret framing 193 * error with all-zeros data as a break sequence. Most of the time, 194 * there's another non-zero byte at the end of the sequence. 195 */ 196 if (isrstatus & CDNS_UART_IXR_FRAMING) { 197 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & 198 CDNS_UART_SR_RXEMPTY)) { 199 if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) { 200 port->read_status_mask |= CDNS_UART_IXR_BRK; 201 isrstatus &= ~CDNS_UART_IXR_FRAMING; 202 } 203 } 204 cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET); 205 } 206 207 /* drop byte with parity error if IGNPAR specified */ 208 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY) 209 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT); 210 211 isrstatus &= port->read_status_mask; 212 isrstatus &= ~port->ignore_status_mask; 213 214 if ((isrstatus & CDNS_UART_IXR_TOUT) || 215 (isrstatus & CDNS_UART_IXR_RXTRIG)) { 216 /* Receive Timeout Interrupt */ 217 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & 218 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 219 data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET); 220 221 /* Non-NULL byte after BREAK is garbage (99%) */ 222 if (data && (port->read_status_mask & 223 CDNS_UART_IXR_BRK)) { 224 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 225 port->icount.brk++; 226 if (uart_handle_break(port)) 227 continue; 228 } 229 230#ifdef SUPPORT_SYSRQ 231 /* 232 * uart_handle_sysrq_char() doesn't work if 233 * spinlocked, for some reason 234 */ 235 if (port->sysrq) { 236 spin_unlock(&port->lock); 237 if (uart_handle_sysrq_char(port, 238 (unsigned char)data)) { 239 spin_lock(&port->lock); 240 continue; 241 } 242 spin_lock(&port->lock); 243 } 244#endif 245 246 port->icount.rx++; 247 248 if (isrstatus & CDNS_UART_IXR_PARITY) { 249 port->icount.parity++; 250 status = TTY_PARITY; 251 } else if (isrstatus & CDNS_UART_IXR_FRAMING) { 252 port->icount.frame++; 253 status = TTY_FRAME; 254 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) { 255 port->icount.overrun++; 256 } 257 258 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN, 259 data, status); 260 } 261 spin_unlock(&port->lock); 262 tty_flip_buffer_push(&port->state->port); 263 spin_lock(&port->lock); 264 } 265 266 /* Dispatch an appropriate handler */ 267 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) { 268 if (uart_circ_empty(&port->state->xmit)) { 269 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, 270 CDNS_UART_IDR_OFFSET); 271 } else { 272 numbytes = port->fifosize; 273 /* Break if no more data available in the UART buffer */ 274 while (numbytes--) { 275 if (uart_circ_empty(&port->state->xmit)) 276 break; 277 /* Get the data from the UART circular buffer 278 * and write it to the cdns_uart's TX_FIFO 279 * register. 280 */ 281 cdns_uart_writel( 282 port->state->xmit.buf[port->state->xmit. 283 tail], CDNS_UART_FIFO_OFFSET); 284 285 port->icount.tx++; 286 287 /* Adjust the tail of the UART buffer and wrap 288 * the buffer if it reaches limit. 289 */ 290 port->state->xmit.tail = 291 (port->state->xmit.tail + 1) & 292 (UART_XMIT_SIZE - 1); 293 } 294 295 if (uart_circ_chars_pending( 296 &port->state->xmit) < WAKEUP_CHARS) 297 uart_write_wakeup(port); 298 } 299 } 300 301 cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET); 302 303 /* be sure to release the lock and tty before leaving */ 304 spin_unlock_irqrestore(&port->lock, flags); 305 306 return IRQ_HANDLED; 307} 308 309/** 310 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 311 * @clk: UART module input clock 312 * @baud: Desired baud rate 313 * @rbdiv: BDIV value (return value) 314 * @rcd: CD value (return value) 315 * @div8: Value for clk_sel bit in mod (return value) 316 * Return: baud rate, requested baud when possible, or actual baud when there 317 * was too much error, zero if no valid divisors are found. 318 * 319 * Formula to obtain baud rate is 320 * baud_tx/rx rate = clk/CD * (BDIV + 1) 321 * input_clk = (Uart User Defined Clock or Apb Clock) 322 * depends on UCLKEN in MR Reg 323 * clk = input_clk or input_clk/8; 324 * depends on CLKS in MR reg 325 * CD and BDIV depends on values in 326 * baud rate generate register 327 * baud rate clock divisor register 328 */ 329static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 330 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 331{ 332 u32 cd, bdiv; 333 unsigned int calc_baud; 334 unsigned int bestbaud = 0; 335 unsigned int bauderror; 336 unsigned int besterror = ~0; 337 338 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 339 *div8 = 1; 340 clk /= 8; 341 } else { 342 *div8 = 0; 343 } 344 345 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 346 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 347 if (cd < 1 || cd > CDNS_UART_CD_MAX) 348 continue; 349 350 calc_baud = clk / (cd * (bdiv + 1)); 351 352 if (baud > calc_baud) 353 bauderror = baud - calc_baud; 354 else 355 bauderror = calc_baud - baud; 356 357 if (besterror > bauderror) { 358 *rbdiv = bdiv; 359 *rcd = cd; 360 bestbaud = calc_baud; 361 besterror = bauderror; 362 } 363 } 364 /* use the values when percent error is acceptable */ 365 if (((besterror * 100) / baud) < 3) 366 bestbaud = baud; 367 368 return bestbaud; 369} 370 371/** 372 * cdns_uart_set_baud_rate - Calculate and set the baud rate 373 * @port: Handle to the uart port structure 374 * @baud: Baud rate to set 375 * Return: baud rate, requested baud when possible, or actual baud when there 376 * was too much error, zero if no valid divisors are found. 377 */ 378static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 379 unsigned int baud) 380{ 381 unsigned int calc_baud; 382 u32 cd = 0, bdiv = 0; 383 u32 mreg; 384 int div8; 385 struct cdns_uart *cdns_uart = port->private_data; 386 387 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 388 &div8); 389 390 /* Write new divisors to hardware */ 391 mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET); 392 if (div8) 393 mreg |= CDNS_UART_MR_CLKSEL; 394 else 395 mreg &= ~CDNS_UART_MR_CLKSEL; 396 cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET); 397 cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET); 398 cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET); 399 cdns_uart->baud = baud; 400 401 return calc_baud; 402} 403 404#ifdef CONFIG_COMMON_CLK 405/** 406 * cdns_uart_clk_notitifer_cb - Clock notifier callback 407 * @nb: Notifier block 408 * @event: Notify event 409 * @data: Notifier data 410 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 411 */ 412static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 413 unsigned long event, void *data) 414{ 415 u32 ctrl_reg; 416 struct uart_port *port; 417 int locked = 0; 418 struct clk_notifier_data *ndata = data; 419 unsigned long flags = 0; 420 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 421 422 port = cdns_uart->port; 423 if (port->suspended) 424 return NOTIFY_OK; 425 426 switch (event) { 427 case PRE_RATE_CHANGE: 428 { 429 u32 bdiv, cd; 430 int div8; 431 432 /* 433 * Find out if current baud-rate can be achieved with new clock 434 * frequency. 435 */ 436 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 437 &bdiv, &cd, &div8)) { 438 dev_warn(port->dev, "clock rate change rejected\n"); 439 return NOTIFY_BAD; 440 } 441 442 spin_lock_irqsave(&cdns_uart->port->lock, flags); 443 444 /* Disable the TX and RX to set baud rate */ 445 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 446 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 447 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 448 449 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 450 451 return NOTIFY_OK; 452 } 453 case POST_RATE_CHANGE: 454 /* 455 * Set clk dividers to generate correct baud with new clock 456 * frequency. 457 */ 458 459 spin_lock_irqsave(&cdns_uart->port->lock, flags); 460 461 locked = 1; 462 port->uartclk = ndata->new_rate; 463 464 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 465 cdns_uart->baud); 466 /* fall through */ 467 case ABORT_RATE_CHANGE: 468 if (!locked) 469 spin_lock_irqsave(&cdns_uart->port->lock, flags); 470 471 /* Set TX/RX Reset */ 472 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 473 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 474 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 475 476 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) & 477 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 478 cpu_relax(); 479 480 /* 481 * Clear the RX disable and TX disable bits and then set the TX 482 * enable bit and RX enable bit to enable the transmitter and 483 * receiver. 484 */ 485 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 486 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 487 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 488 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 489 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 490 491 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 492 493 return NOTIFY_OK; 494 default: 495 return NOTIFY_DONE; 496 } 497} 498#endif 499 500/** 501 * cdns_uart_start_tx - Start transmitting bytes 502 * @port: Handle to the uart port structure 503 */ 504static void cdns_uart_start_tx(struct uart_port *port) 505{ 506 unsigned int status, numbytes = port->fifosize; 507 508 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 509 return; 510 511 status = cdns_uart_readl(CDNS_UART_CR_OFFSET); 512 /* Set the TX enable bit and clear the TX disable bit to enable the 513 * transmitter. 514 */ 515 cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, 516 CDNS_UART_CR_OFFSET); 517 518 while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & 519 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) { 520 /* Break if no more data available in the UART buffer */ 521 if (uart_circ_empty(&port->state->xmit)) 522 break; 523 524 /* Get the data from the UART circular buffer and 525 * write it to the cdns_uart's TX_FIFO register. 526 */ 527 cdns_uart_writel( 528 port->state->xmit.buf[port->state->xmit.tail], 529 CDNS_UART_FIFO_OFFSET); 530 port->icount.tx++; 531 532 /* Adjust the tail of the UART buffer and wrap 533 * the buffer if it reaches limit. 534 */ 535 port->state->xmit.tail = (port->state->xmit.tail + 1) & 536 (UART_XMIT_SIZE - 1); 537 } 538 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET); 539 /* Enable the TX Empty interrupt */ 540 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET); 541 542 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 543 uart_write_wakeup(port); 544} 545 546/** 547 * cdns_uart_stop_tx - Stop TX 548 * @port: Handle to the uart port structure 549 */ 550static void cdns_uart_stop_tx(struct uart_port *port) 551{ 552 unsigned int regval; 553 554 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET); 555 regval |= CDNS_UART_CR_TX_DIS; 556 /* Disable the transmitter */ 557 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET); 558} 559 560/** 561 * cdns_uart_stop_rx - Stop RX 562 * @port: Handle to the uart port structure 563 */ 564static void cdns_uart_stop_rx(struct uart_port *port) 565{ 566 unsigned int regval; 567 568 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET); 569 regval |= CDNS_UART_CR_RX_DIS; 570 /* Disable the receiver */ 571 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET); 572} 573 574/** 575 * cdns_uart_tx_empty - Check whether TX is empty 576 * @port: Handle to the uart port structure 577 * 578 * Return: TIOCSER_TEMT on success, 0 otherwise 579 */ 580static unsigned int cdns_uart_tx_empty(struct uart_port *port) 581{ 582 unsigned int status; 583 584 status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY; 585 return status ? TIOCSER_TEMT : 0; 586} 587 588/** 589 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 590 * transmitting char breaks 591 * @port: Handle to the uart port structure 592 * @ctl: Value based on which start or stop decision is taken 593 */ 594static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 595{ 596 unsigned int status; 597 unsigned long flags; 598 599 spin_lock_irqsave(&port->lock, flags); 600 601 status = cdns_uart_readl(CDNS_UART_CR_OFFSET); 602 603 if (ctl == -1) 604 cdns_uart_writel(CDNS_UART_CR_STARTBRK | status, 605 CDNS_UART_CR_OFFSET); 606 else { 607 if ((status & CDNS_UART_CR_STOPBRK) == 0) 608 cdns_uart_writel(CDNS_UART_CR_STOPBRK | status, 609 CDNS_UART_CR_OFFSET); 610 } 611 spin_unlock_irqrestore(&port->lock, flags); 612} 613 614/** 615 * cdns_uart_set_termios - termios operations, handling data length, parity, 616 * stop bits, flow control, baud rate 617 * @port: Handle to the uart port structure 618 * @termios: Handle to the input termios structure 619 * @old: Values of the previously saved termios structure 620 */ 621static void cdns_uart_set_termios(struct uart_port *port, 622 struct ktermios *termios, struct ktermios *old) 623{ 624 unsigned int cval = 0; 625 unsigned int baud, minbaud, maxbaud; 626 unsigned long flags; 627 unsigned int ctrl_reg, mode_reg; 628 629 spin_lock_irqsave(&port->lock, flags); 630 631 /* Empty the receive FIFO 1st before making changes */ 632 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & 633 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 634 cdns_uart_readl(CDNS_UART_FIFO_OFFSET); 635 } 636 637 /* Disable the TX and RX to set baud rate */ 638 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 639 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 640 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 641 642 /* 643 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 644 * min and max baud should be calculated here based on port->uartclk. 645 * this way we get a valid baud and can safely call set_baud() 646 */ 647 minbaud = port->uartclk / 648 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 649 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 650 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 651 baud = cdns_uart_set_baud_rate(port, baud); 652 if (tty_termios_baud_rate(termios)) 653 tty_termios_encode_baud_rate(termios, baud, baud); 654 655 /* Update the per-port timeout. */ 656 uart_update_timeout(port, termios->c_cflag, baud); 657 658 /* Set TX/RX Reset */ 659 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 660 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 661 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 662 663 /* 664 * Clear the RX disable and TX disable bits and then set the TX enable 665 * bit and RX enable bit to enable the transmitter and receiver. 666 */ 667 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 668 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 669 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 670 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 671 672 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 673 674 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 675 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 676 port->ignore_status_mask = 0; 677 678 if (termios->c_iflag & INPCK) 679 port->read_status_mask |= CDNS_UART_IXR_PARITY | 680 CDNS_UART_IXR_FRAMING; 681 682 if (termios->c_iflag & IGNPAR) 683 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 684 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 685 686 /* ignore all characters if CREAD is not set */ 687 if ((termios->c_cflag & CREAD) == 0) 688 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 689 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 690 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 691 692 mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET); 693 694 /* Handling Data Size */ 695 switch (termios->c_cflag & CSIZE) { 696 case CS6: 697 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 698 break; 699 case CS7: 700 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 701 break; 702 default: 703 case CS8: 704 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 705 termios->c_cflag &= ~CSIZE; 706 termios->c_cflag |= CS8; 707 break; 708 } 709 710 /* Handling Parity and Stop Bits length */ 711 if (termios->c_cflag & CSTOPB) 712 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 713 else 714 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 715 716 if (termios->c_cflag & PARENB) { 717 /* Mark or Space parity */ 718 if (termios->c_cflag & CMSPAR) { 719 if (termios->c_cflag & PARODD) 720 cval |= CDNS_UART_MR_PARITY_MARK; 721 else 722 cval |= CDNS_UART_MR_PARITY_SPACE; 723 } else { 724 if (termios->c_cflag & PARODD) 725 cval |= CDNS_UART_MR_PARITY_ODD; 726 else 727 cval |= CDNS_UART_MR_PARITY_EVEN; 728 } 729 } else { 730 cval |= CDNS_UART_MR_PARITY_NONE; 731 } 732 cval |= mode_reg & 1; 733 cdns_uart_writel(cval, CDNS_UART_MR_OFFSET); 734 735 spin_unlock_irqrestore(&port->lock, flags); 736} 737 738/** 739 * cdns_uart_startup - Called when an application opens a cdns_uart port 740 * @port: Handle to the uart port structure 741 * 742 * Return: 0 on success, negative errno otherwise 743 */ 744static int cdns_uart_startup(struct uart_port *port) 745{ 746 unsigned int retval = 0, status = 0; 747 748 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, 749 (void *)port); 750 if (retval) 751 return retval; 752 753 /* Disable the TX and RX */ 754 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 755 CDNS_UART_CR_OFFSET); 756 757 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 758 * no break chars. 759 */ 760 cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 761 CDNS_UART_CR_OFFSET); 762 763 status = cdns_uart_readl(CDNS_UART_CR_OFFSET); 764 765 /* Clear the RX disable and TX disable bits and then set the TX enable 766 * bit and RX enable bit to enable the transmitter and receiver. 767 */ 768 cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS)) 769 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN | 770 CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET); 771 772 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 773 * no parity. 774 */ 775 cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 776 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 777 CDNS_UART_MR_OFFSET); 778 779 /* 780 * Set the RX FIFO Trigger level to use most of the FIFO, but it 781 * can be tuned with a module parameter 782 */ 783 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET); 784 785 /* 786 * Receive Timeout register is enabled but it 787 * can be tuned with a module parameter 788 */ 789 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 790 791 /* Clear out any pending interrupts before enabling them */ 792 cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET), 793 CDNS_UART_ISR_OFFSET); 794 795 /* Set the Interrupt Registers with desired interrupts */ 796 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY | 797 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN | 798 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT, 799 CDNS_UART_IER_OFFSET); 800 801 return retval; 802} 803 804/** 805 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 806 * @port: Handle to the uart port structure 807 */ 808static void cdns_uart_shutdown(struct uart_port *port) 809{ 810 int status; 811 812 /* Disable interrupts */ 813 status = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 814 cdns_uart_writel(status, CDNS_UART_IDR_OFFSET); 815 816 /* Disable the TX and RX */ 817 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 818 CDNS_UART_CR_OFFSET); 819 free_irq(port->irq, port); 820} 821 822/** 823 * cdns_uart_type - Set UART type to cdns_uart port 824 * @port: Handle to the uart port structure 825 * 826 * Return: string on success, NULL otherwise 827 */ 828static const char *cdns_uart_type(struct uart_port *port) 829{ 830 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 831} 832 833/** 834 * cdns_uart_verify_port - Verify the port params 835 * @port: Handle to the uart port structure 836 * @ser: Handle to the structure whose members are compared 837 * 838 * Return: 0 on success, negative errno otherwise. 839 */ 840static int cdns_uart_verify_port(struct uart_port *port, 841 struct serial_struct *ser) 842{ 843 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 844 return -EINVAL; 845 if (port->irq != ser->irq) 846 return -EINVAL; 847 if (ser->io_type != UPIO_MEM) 848 return -EINVAL; 849 if (port->iobase != ser->port) 850 return -EINVAL; 851 if (ser->hub6 != 0) 852 return -EINVAL; 853 return 0; 854} 855 856/** 857 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 858 * called when the driver adds a cdns_uart port via 859 * uart_add_one_port() 860 * @port: Handle to the uart port structure 861 * 862 * Return: 0 on success, negative errno otherwise. 863 */ 864static int cdns_uart_request_port(struct uart_port *port) 865{ 866 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 867 CDNS_UART_NAME)) { 868 return -ENOMEM; 869 } 870 871 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 872 if (!port->membase) { 873 dev_err(port->dev, "Unable to map registers\n"); 874 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 875 return -ENOMEM; 876 } 877 return 0; 878} 879 880/** 881 * cdns_uart_release_port - Release UART port 882 * @port: Handle to the uart port structure 883 * 884 * Release the memory region attached to a cdns_uart port. Called when the 885 * driver removes a cdns_uart port via uart_remove_one_port(). 886 */ 887static void cdns_uart_release_port(struct uart_port *port) 888{ 889 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 890 iounmap(port->membase); 891 port->membase = NULL; 892} 893 894/** 895 * cdns_uart_config_port - Configure UART port 896 * @port: Handle to the uart port structure 897 * @flags: If any 898 */ 899static void cdns_uart_config_port(struct uart_port *port, int flags) 900{ 901 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 902 port->type = PORT_XUARTPS; 903} 904 905/** 906 * cdns_uart_get_mctrl - Get the modem control state 907 * @port: Handle to the uart port structure 908 * 909 * Return: the modem control state 910 */ 911static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 912{ 913 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 914} 915 916static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 917{ 918 /* N/A */ 919} 920 921#ifdef CONFIG_CONSOLE_POLL 922static int cdns_uart_poll_get_char(struct uart_port *port) 923{ 924 u32 imr; 925 int c; 926 927 /* Disable all interrupts */ 928 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 929 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); 930 931 /* Check if FIFO is empty */ 932 if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY) 933 c = NO_POLL_CHAR; 934 else /* Read a character */ 935 c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET); 936 937 /* Enable interrupts */ 938 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); 939 940 return c; 941} 942 943static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 944{ 945 u32 imr; 946 947 /* Disable all interrupts */ 948 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 949 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); 950 951 /* Wait until FIFO is empty */ 952 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)) 953 cpu_relax(); 954 955 /* Write a character */ 956 cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET); 957 958 /* Wait until FIFO is empty */ 959 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)) 960 cpu_relax(); 961 962 /* Enable interrupts */ 963 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); 964 965 return; 966} 967#endif 968 969static struct uart_ops cdns_uart_ops = { 970 .set_mctrl = cdns_uart_set_mctrl, 971 .get_mctrl = cdns_uart_get_mctrl, 972 .start_tx = cdns_uart_start_tx, 973 .stop_tx = cdns_uart_stop_tx, 974 .stop_rx = cdns_uart_stop_rx, 975 .tx_empty = cdns_uart_tx_empty, 976 .break_ctl = cdns_uart_break_ctl, 977 .set_termios = cdns_uart_set_termios, 978 .startup = cdns_uart_startup, 979 .shutdown = cdns_uart_shutdown, 980 .type = cdns_uart_type, 981 .verify_port = cdns_uart_verify_port, 982 .request_port = cdns_uart_request_port, 983 .release_port = cdns_uart_release_port, 984 .config_port = cdns_uart_config_port, 985#ifdef CONFIG_CONSOLE_POLL 986 .poll_get_char = cdns_uart_poll_get_char, 987 .poll_put_char = cdns_uart_poll_put_char, 988#endif 989}; 990 991static struct uart_port cdns_uart_port[2]; 992 993/** 994 * cdns_uart_get_port - Configure the port from platform device resource info 995 * @id: Port id 996 * 997 * Return: a pointer to a uart_port or NULL for failure 998 */ 999static struct uart_port *cdns_uart_get_port(int id) 1000{ 1001 struct uart_port *port; 1002 1003 /* Try the given port id if failed use default method */ 1004 if (cdns_uart_port[id].mapbase != 0) { 1005 /* Find the next unused port */ 1006 for (id = 0; id < CDNS_UART_NR_PORTS; id++) 1007 if (cdns_uart_port[id].mapbase == 0) 1008 break; 1009 } 1010 1011 if (id >= CDNS_UART_NR_PORTS) 1012 return NULL; 1013 1014 port = &cdns_uart_port[id]; 1015 1016 /* At this point, we've got an empty uart_port struct, initialize it */ 1017 spin_lock_init(&port->lock); 1018 port->membase = NULL; 1019 port->iobase = 1; /* mark port in use */ 1020 port->irq = 0; 1021 port->type = PORT_UNKNOWN; 1022 port->iotype = UPIO_MEM32; 1023 port->flags = UPF_BOOT_AUTOCONF; 1024 port->ops = &cdns_uart_ops; 1025 port->fifosize = CDNS_UART_FIFO_SIZE; 1026 port->line = id; 1027 port->dev = NULL; 1028 return port; 1029} 1030 1031#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1032/** 1033 * cdns_uart_console_wait_tx - Wait for the TX to be full 1034 * @port: Handle to the uart port structure 1035 */ 1036static void cdns_uart_console_wait_tx(struct uart_port *port) 1037{ 1038 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY) 1039 != CDNS_UART_SR_TXEMPTY) 1040 barrier(); 1041} 1042 1043/** 1044 * cdns_uart_console_putchar - write the character to the FIFO buffer 1045 * @port: Handle to the uart port structure 1046 * @ch: Character to be written 1047 */ 1048static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1049{ 1050 cdns_uart_console_wait_tx(port); 1051 cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET); 1052} 1053 1054static void cdns_early_write(struct console *con, const char *s, unsigned n) 1055{ 1056 struct earlycon_device *dev = con->data; 1057 1058 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1059} 1060 1061static int __init cdns_early_console_setup(struct earlycon_device *device, 1062 const char *opt) 1063{ 1064 if (!device->port.membase) 1065 return -ENODEV; 1066 1067 device->con->write = cdns_early_write; 1068 1069 return 0; 1070} 1071EARLYCON_DECLARE(cdns, cdns_early_console_setup); 1072 1073/** 1074 * cdns_uart_console_write - perform write operation 1075 * @co: Console handle 1076 * @s: Pointer to character array 1077 * @count: No of characters 1078 */ 1079static void cdns_uart_console_write(struct console *co, const char *s, 1080 unsigned int count) 1081{ 1082 struct uart_port *port = &cdns_uart_port[co->index]; 1083 unsigned long flags; 1084 unsigned int imr, ctrl; 1085 int locked = 1; 1086 1087 if (oops_in_progress) 1088 locked = spin_trylock_irqsave(&port->lock, flags); 1089 else 1090 spin_lock_irqsave(&port->lock, flags); 1091 1092 /* save and disable interrupt */ 1093 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 1094 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); 1095 1096 /* 1097 * Make sure that the tx part is enabled. Set the TX enable bit and 1098 * clear the TX disable bit to enable the transmitter. 1099 */ 1100 ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET); 1101 cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, 1102 CDNS_UART_CR_OFFSET); 1103 1104 uart_console_write(port, s, count, cdns_uart_console_putchar); 1105 cdns_uart_console_wait_tx(port); 1106 1107 cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET); 1108 1109 /* restore interrupt state */ 1110 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); 1111 1112 if (locked) 1113 spin_unlock_irqrestore(&port->lock, flags); 1114} 1115 1116/** 1117 * cdns_uart_console_setup - Initialize the uart to default config 1118 * @co: Console handle 1119 * @options: Initial settings of uart 1120 * 1121 * Return: 0 on success, negative errno otherwise. 1122 */ 1123static int __init cdns_uart_console_setup(struct console *co, char *options) 1124{ 1125 struct uart_port *port = &cdns_uart_port[co->index]; 1126 int baud = 9600; 1127 int bits = 8; 1128 int parity = 'n'; 1129 int flow = 'n'; 1130 1131 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) 1132 return -EINVAL; 1133 1134 if (!port->mapbase) { 1135 pr_debug("console on ttyPS%i not present\n", co->index); 1136 return -ENODEV; 1137 } 1138 1139 if (options) 1140 uart_parse_options(options, &baud, &parity, &bits, &flow); 1141 1142 return uart_set_options(port, co, baud, parity, bits, flow); 1143} 1144 1145static struct uart_driver cdns_uart_uart_driver; 1146 1147static struct console cdns_uart_console = { 1148 .name = CDNS_UART_TTY_NAME, 1149 .write = cdns_uart_console_write, 1150 .device = uart_console_device, 1151 .setup = cdns_uart_console_setup, 1152 .flags = CON_PRINTBUFFER, 1153 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1154 .data = &cdns_uart_uart_driver, 1155}; 1156 1157/** 1158 * cdns_uart_console_init - Initialization call 1159 * 1160 * Return: 0 on success, negative errno otherwise 1161 */ 1162static int __init cdns_uart_console_init(void) 1163{ 1164 register_console(&cdns_uart_console); 1165 return 0; 1166} 1167 1168console_initcall(cdns_uart_console_init); 1169 1170#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1171 1172static struct uart_driver cdns_uart_uart_driver = { 1173 .owner = THIS_MODULE, 1174 .driver_name = CDNS_UART_NAME, 1175 .dev_name = CDNS_UART_TTY_NAME, 1176 .major = CDNS_UART_MAJOR, 1177 .minor = CDNS_UART_MINOR, 1178 .nr = CDNS_UART_NR_PORTS, 1179#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1180 .cons = &cdns_uart_console, 1181#endif 1182}; 1183 1184#ifdef CONFIG_PM_SLEEP 1185/** 1186 * cdns_uart_suspend - suspend event 1187 * @device: Pointer to the device structure 1188 * 1189 * Return: 0 1190 */ 1191static int cdns_uart_suspend(struct device *device) 1192{ 1193 struct uart_port *port = dev_get_drvdata(device); 1194 struct tty_struct *tty; 1195 struct device *tty_dev; 1196 int may_wake = 0; 1197 1198 /* Get the tty which could be NULL so don't assume it's valid */ 1199 tty = tty_port_tty_get(&port->state->port); 1200 if (tty) { 1201 tty_dev = tty->dev; 1202 may_wake = device_may_wakeup(tty_dev); 1203 tty_kref_put(tty); 1204 } 1205 1206 /* 1207 * Call the API provided in serial_core.c file which handles 1208 * the suspend. 1209 */ 1210 uart_suspend_port(&cdns_uart_uart_driver, port); 1211 if (console_suspend_enabled && !may_wake) { 1212 struct cdns_uart *cdns_uart = port->private_data; 1213 1214 clk_disable(cdns_uart->uartclk); 1215 clk_disable(cdns_uart->pclk); 1216 } else { 1217 unsigned long flags = 0; 1218 1219 spin_lock_irqsave(&port->lock, flags); 1220 /* Empty the receive FIFO 1st before making changes */ 1221 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & 1222 CDNS_UART_SR_RXEMPTY)) 1223 cdns_uart_readl(CDNS_UART_FIFO_OFFSET); 1224 /* set RX trigger level to 1 */ 1225 cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET); 1226 /* disable RX timeout interrups */ 1227 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET); 1228 spin_unlock_irqrestore(&port->lock, flags); 1229 } 1230 1231 return 0; 1232} 1233 1234/** 1235 * cdns_uart_resume - Resume after a previous suspend 1236 * @device: Pointer to the device structure 1237 * 1238 * Return: 0 1239 */ 1240static int cdns_uart_resume(struct device *device) 1241{ 1242 struct uart_port *port = dev_get_drvdata(device); 1243 unsigned long flags = 0; 1244 u32 ctrl_reg; 1245 struct tty_struct *tty; 1246 struct device *tty_dev; 1247 int may_wake = 0; 1248 1249 /* Get the tty which could be NULL so don't assume it's valid */ 1250 tty = tty_port_tty_get(&port->state->port); 1251 if (tty) { 1252 tty_dev = tty->dev; 1253 may_wake = device_may_wakeup(tty_dev); 1254 tty_kref_put(tty); 1255 } 1256 1257 if (console_suspend_enabled && !may_wake) { 1258 struct cdns_uart *cdns_uart = port->private_data; 1259 1260 clk_enable(cdns_uart->pclk); 1261 clk_enable(cdns_uart->uartclk); 1262 1263 spin_lock_irqsave(&port->lock, flags); 1264 1265 /* Set TX/RX Reset */ 1266 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 1267 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1268 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 1269 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) & 1270 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1271 cpu_relax(); 1272 1273 /* restore rx timeout value */ 1274 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 1275 /* Enable Tx/Rx */ 1276 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 1277 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1278 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1279 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 1280 1281 spin_unlock_irqrestore(&port->lock, flags); 1282 } else { 1283 spin_lock_irqsave(&port->lock, flags); 1284 /* restore original rx trigger level */ 1285 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET); 1286 /* enable RX timeout interrupt */ 1287 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET); 1288 spin_unlock_irqrestore(&port->lock, flags); 1289 } 1290 1291 return uart_resume_port(&cdns_uart_uart_driver, port); 1292} 1293#endif /* ! CONFIG_PM_SLEEP */ 1294 1295static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend, 1296 cdns_uart_resume); 1297 1298/** 1299 * cdns_uart_probe - Platform driver probe 1300 * @pdev: Pointer to the platform device structure 1301 * 1302 * Return: 0 on success, negative errno otherwise 1303 */ 1304static int cdns_uart_probe(struct platform_device *pdev) 1305{ 1306 int rc, id; 1307 struct uart_port *port; 1308 struct resource *res, *res2; 1309 struct cdns_uart *cdns_uart_data; 1310 1311 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1312 GFP_KERNEL); 1313 if (!cdns_uart_data) 1314 return -ENOMEM; 1315 1316 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1317 if (IS_ERR(cdns_uart_data->pclk)) { 1318 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1319 if (!IS_ERR(cdns_uart_data->pclk)) 1320 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1321 } 1322 if (IS_ERR(cdns_uart_data->pclk)) { 1323 dev_err(&pdev->dev, "pclk clock not found.\n"); 1324 return PTR_ERR(cdns_uart_data->pclk); 1325 } 1326 1327 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1328 if (IS_ERR(cdns_uart_data->uartclk)) { 1329 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1330 if (!IS_ERR(cdns_uart_data->uartclk)) 1331 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1332 } 1333 if (IS_ERR(cdns_uart_data->uartclk)) { 1334 dev_err(&pdev->dev, "uart_clk clock not found.\n"); 1335 return PTR_ERR(cdns_uart_data->uartclk); 1336 } 1337 1338 rc = clk_prepare_enable(cdns_uart_data->pclk); 1339 if (rc) { 1340 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1341 return rc; 1342 } 1343 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1344 if (rc) { 1345 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1346 goto err_out_clk_dis_pclk; 1347 } 1348 1349 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1350 if (!res) { 1351 rc = -ENODEV; 1352 goto err_out_clk_disable; 1353 } 1354 1355 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1356 if (!res2) { 1357 rc = -ENODEV; 1358 goto err_out_clk_disable; 1359 } 1360 1361#ifdef CONFIG_COMMON_CLK 1362 cdns_uart_data->clk_rate_change_nb.notifier_call = 1363 cdns_uart_clk_notifier_cb; 1364 if (clk_notifier_register(cdns_uart_data->uartclk, 1365 &cdns_uart_data->clk_rate_change_nb)) 1366 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1367#endif 1368 /* Look for a serialN alias */ 1369 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1370 if (id < 0) 1371 id = 0; 1372 1373 /* Initialize the port structure */ 1374 port = cdns_uart_get_port(id); 1375 1376 if (!port) { 1377 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1378 rc = -ENODEV; 1379 goto err_out_notif_unreg; 1380 } else { 1381 /* Register the port. 1382 * This function also registers this device with the tty layer 1383 * and triggers invocation of the config_port() entry point. 1384 */ 1385 port->mapbase = res->start; 1386 port->irq = res2->start; 1387 port->dev = &pdev->dev; 1388 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1389 port->private_data = cdns_uart_data; 1390 cdns_uart_data->port = port; 1391 platform_set_drvdata(pdev, port); 1392 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1393 if (rc) { 1394 dev_err(&pdev->dev, 1395 "uart_add_one_port() failed; err=%i\n", rc); 1396 goto err_out_notif_unreg; 1397 } 1398 return 0; 1399 } 1400 1401err_out_notif_unreg: 1402#ifdef CONFIG_COMMON_CLK 1403 clk_notifier_unregister(cdns_uart_data->uartclk, 1404 &cdns_uart_data->clk_rate_change_nb); 1405#endif 1406err_out_clk_disable: 1407 clk_disable_unprepare(cdns_uart_data->uartclk); 1408err_out_clk_dis_pclk: 1409 clk_disable_unprepare(cdns_uart_data->pclk); 1410 1411 return rc; 1412} 1413 1414/** 1415 * cdns_uart_remove - called when the platform driver is unregistered 1416 * @pdev: Pointer to the platform device structure 1417 * 1418 * Return: 0 on success, negative errno otherwise 1419 */ 1420static int cdns_uart_remove(struct platform_device *pdev) 1421{ 1422 struct uart_port *port = platform_get_drvdata(pdev); 1423 struct cdns_uart *cdns_uart_data = port->private_data; 1424 int rc; 1425 1426 /* Remove the cdns_uart port from the serial core */ 1427#ifdef CONFIG_COMMON_CLK 1428 clk_notifier_unregister(cdns_uart_data->uartclk, 1429 &cdns_uart_data->clk_rate_change_nb); 1430#endif 1431 rc = uart_remove_one_port(&cdns_uart_uart_driver, port); 1432 port->mapbase = 0; 1433 clk_disable_unprepare(cdns_uart_data->uartclk); 1434 clk_disable_unprepare(cdns_uart_data->pclk); 1435 return rc; 1436} 1437 1438/* Match table for of_platform binding */ 1439static struct of_device_id cdns_uart_of_match[] = { 1440 { .compatible = "xlnx,xuartps", }, 1441 { .compatible = "cdns,uart-r1p8", }, 1442 {} 1443}; 1444MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1445 1446static struct platform_driver cdns_uart_platform_driver = { 1447 .probe = cdns_uart_probe, 1448 .remove = cdns_uart_remove, 1449 .driver = { 1450 .name = CDNS_UART_NAME, 1451 .of_match_table = cdns_uart_of_match, 1452 .pm = &cdns_uart_dev_pm_ops, 1453 }, 1454}; 1455 1456static int __init cdns_uart_init(void) 1457{ 1458 int retval = 0; 1459 1460 /* Register the cdns_uart driver with the serial core */ 1461 retval = uart_register_driver(&cdns_uart_uart_driver); 1462 if (retval) 1463 return retval; 1464 1465 /* Register the platform driver */ 1466 retval = platform_driver_register(&cdns_uart_platform_driver); 1467 if (retval) 1468 uart_unregister_driver(&cdns_uart_uart_driver); 1469 1470 return retval; 1471} 1472 1473static void __exit cdns_uart_exit(void) 1474{ 1475 /* Unregister the platform driver */ 1476 platform_driver_unregister(&cdns_uart_platform_driver); 1477 1478 /* Unregister the cdns_uart driver */ 1479 uart_unregister_driver(&cdns_uart_uart_driver); 1480} 1481 1482module_init(cdns_uart_init); 1483module_exit(cdns_uart_exit); 1484 1485MODULE_DESCRIPTION("Driver for Cadence UART"); 1486MODULE_AUTHOR("Xilinx Inc."); 1487MODULE_LICENSE("GPL"); 1488