1/* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37/* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41#include <linux/kernel.h> 42#include <linux/module.h> 43#include <linux/spinlock.h> 44#include <linux/interrupt.h> 45#include <linux/dma-mapping.h> 46#include <linux/delay.h> 47#include <linux/io.h> 48#include <linux/slab.h> 49#include <linux/usb.h> 50 51#include <linux/usb/hcd.h> 52#include <linux/usb/ch11.h> 53 54#include "core.h" 55#include "hcd.h" 56 57/** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70{ 71#ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119#endif /* VERBOSE_DEBUG */ 120} 121 122/* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130{ 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141} 142 143static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145{ 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 spin_unlock_irqrestore(&hsotg->lock, flags); 168 dwc2_hcd_qh_free(hsotg, qh); 169 spin_lock_irqsave(&hsotg->lock, flags); 170 } 171 172 spin_unlock_irqrestore(&hsotg->lock, flags); 173} 174 175/* 176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 177 * and periodic schedules. The QTD associated with each URB is removed from 178 * the schedule and freed. This function may be called when a disconnect is 179 * detected or when the HCD is being stopped. 180 * 181 * Must be called with interrupt disabled and spinlock held 182 */ 183static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 184{ 185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 191} 192 193/** 194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 195 * 196 * @hsotg: Pointer to struct dwc2_hsotg 197 */ 198void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 199{ 200 u32 hprt0; 201 202 if (hsotg->op_state == OTG_STATE_B_HOST) { 203 /* 204 * Reset the port. During a HNP mode switch the reset 205 * needs to occur within 1ms and have a duration of at 206 * least 50ms. 207 */ 208 hprt0 = dwc2_read_hprt0(hsotg); 209 hprt0 |= HPRT0_RST; 210 writel(hprt0, hsotg->regs + HPRT0); 211 } 212 213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 214 msecs_to_jiffies(50)); 215} 216 217/* Must be called with interrupt disabled and spinlock held */ 218static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 219{ 220 int num_channels = hsotg->core_params->host_channels; 221 struct dwc2_host_chan *channel; 222 u32 hcchar; 223 int i; 224 225 if (hsotg->core_params->dma_enable <= 0) { 226 /* Flush out any channel requests in slave mode */ 227 for (i = 0; i < num_channels; i++) { 228 channel = hsotg->hc_ptr_array[i]; 229 if (!list_empty(&channel->hc_list_entry)) 230 continue; 231 hcchar = readl(hsotg->regs + HCCHAR(i)); 232 if (hcchar & HCCHAR_CHENA) { 233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 234 hcchar |= HCCHAR_CHDIS; 235 writel(hcchar, hsotg->regs + HCCHAR(i)); 236 } 237 } 238 } 239 240 for (i = 0; i < num_channels; i++) { 241 channel = hsotg->hc_ptr_array[i]; 242 if (!list_empty(&channel->hc_list_entry)) 243 continue; 244 hcchar = readl(hsotg->regs + HCCHAR(i)); 245 if (hcchar & HCCHAR_CHENA) { 246 /* Halt the channel */ 247 hcchar |= HCCHAR_CHDIS; 248 writel(hcchar, hsotg->regs + HCCHAR(i)); 249 } 250 251 dwc2_hc_cleanup(hsotg, channel); 252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 253 /* 254 * Added for Descriptor DMA to prevent channel double cleanup in 255 * release_channel_ddma(), which is called from ep_disable when 256 * device disconnects 257 */ 258 channel->qh = NULL; 259 } 260} 261 262/** 263 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 264 * 265 * @hsotg: Pointer to struct dwc2_hsotg 266 * 267 * Must be called with interrupt disabled and spinlock held 268 */ 269void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 270{ 271 u32 intr; 272 273 /* Set status flags for the hub driver */ 274 hsotg->flags.b.port_connect_status_change = 1; 275 hsotg->flags.b.port_connect_status = 0; 276 277 /* 278 * Shutdown any transfers in process by clearing the Tx FIFO Empty 279 * interrupt mask and status bits and disabling subsequent host 280 * channel interrupts. 281 */ 282 intr = readl(hsotg->regs + GINTMSK); 283 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 284 writel(intr, hsotg->regs + GINTMSK); 285 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 286 writel(intr, hsotg->regs + GINTSTS); 287 288 /* 289 * Turn off the vbus power only if the core has transitioned to device 290 * mode. If still in host mode, need to keep power on to detect a 291 * reconnection. 292 */ 293 if (dwc2_is_device_mode(hsotg)) { 294 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 295 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 296 writel(0, hsotg->regs + HPRT0); 297 } 298 299 dwc2_disable_host_interrupts(hsotg); 300 } 301 302 /* Respond with an error status to all URBs in the schedule */ 303 dwc2_kill_all_urbs(hsotg); 304 305 if (dwc2_is_host_mode(hsotg)) 306 /* Clean up any host channels that were in use */ 307 dwc2_hcd_cleanup_channels(hsotg); 308 309 dwc2_host_disconnect(hsotg); 310} 311 312/** 313 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 314 * 315 * @hsotg: Pointer to struct dwc2_hsotg 316 */ 317static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 318{ 319 if (hsotg->lx_state == DWC2_L2) 320 hsotg->flags.b.port_suspend_change = 1; 321 else 322 hsotg->flags.b.port_l1_change = 1; 323} 324 325/** 326 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 327 * 328 * @hsotg: Pointer to struct dwc2_hsotg 329 * 330 * Must be called with interrupt disabled and spinlock held 331 */ 332void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 333{ 334 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 335 336 /* 337 * The root hub should be disconnected before this function is called. 338 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 339 * and the QH lists (via ..._hcd_endpoint_disable). 340 */ 341 342 /* Turn off all host-specific interrupts */ 343 dwc2_disable_host_interrupts(hsotg); 344 345 /* Turn off the vbus power */ 346 dev_dbg(hsotg->dev, "PortPower off\n"); 347 writel(0, hsotg->regs + HPRT0); 348} 349 350static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 351 struct dwc2_hcd_urb *urb, void **ep_handle, 352 gfp_t mem_flags) 353{ 354 struct dwc2_qtd *qtd; 355 unsigned long flags; 356 u32 intr_mask; 357 int retval; 358 int dev_speed; 359 360 if (!hsotg->flags.b.port_connect_status) { 361 /* No longer connected */ 362 dev_err(hsotg->dev, "Not connected\n"); 363 return -ENODEV; 364 } 365 366 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 367 368 /* Some configurations cannot support LS traffic on a FS root port */ 369 if ((dev_speed == USB_SPEED_LOW) && 370 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 371 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 372 u32 hprt0 = readl(hsotg->regs + HPRT0); 373 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 374 375 if (prtspd == HPRT0_SPD_FULL_SPEED) 376 return -ENODEV; 377 } 378 379 qtd = kzalloc(sizeof(*qtd), mem_flags); 380 if (!qtd) 381 return -ENOMEM; 382 383 dwc2_hcd_qtd_init(qtd, urb); 384 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 385 mem_flags); 386 if (retval) { 387 dev_err(hsotg->dev, 388 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 389 retval); 390 kfree(qtd); 391 return retval; 392 } 393 394 intr_mask = readl(hsotg->regs + GINTMSK); 395 if (!(intr_mask & GINTSTS_SOF)) { 396 enum dwc2_transaction_type tr_type; 397 398 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 399 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 400 /* 401 * Do not schedule SG transactions until qtd has 402 * URB_GIVEBACK_ASAP set 403 */ 404 return 0; 405 406 spin_lock_irqsave(&hsotg->lock, flags); 407 tr_type = dwc2_hcd_select_transactions(hsotg); 408 if (tr_type != DWC2_TRANSACTION_NONE) 409 dwc2_hcd_queue_transactions(hsotg, tr_type); 410 spin_unlock_irqrestore(&hsotg->lock, flags); 411 } 412 413 return 0; 414} 415 416/* Must be called with interrupt disabled and spinlock held */ 417static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 418 struct dwc2_hcd_urb *urb) 419{ 420 struct dwc2_qh *qh; 421 struct dwc2_qtd *urb_qtd; 422 423 urb_qtd = urb->qtd; 424 if (!urb_qtd) { 425 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 426 return -EINVAL; 427 } 428 429 qh = urb_qtd->qh; 430 if (!qh) { 431 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 432 return -EINVAL; 433 } 434 435 urb->priv = NULL; 436 437 if (urb_qtd->in_process && qh->channel) { 438 dwc2_dump_channel_info(hsotg, qh->channel); 439 440 /* The QTD is in process (it has been assigned to a channel) */ 441 if (hsotg->flags.b.port_connect_status) 442 /* 443 * If still connected (i.e. in host mode), halt the 444 * channel so it can be used for other transfers. If 445 * no longer connected, the host registers can't be 446 * written to halt the channel since the core is in 447 * device mode. 448 */ 449 dwc2_hc_halt(hsotg, qh->channel, 450 DWC2_HC_XFER_URB_DEQUEUE); 451 } 452 453 /* 454 * Free the QTD and clean up the associated QH. Leave the QH in the 455 * schedule if it has any remaining QTDs. 456 */ 457 if (hsotg->core_params->dma_desc_enable <= 0) { 458 u8 in_process = urb_qtd->in_process; 459 460 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 461 if (in_process) { 462 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 463 qh->channel = NULL; 464 } else if (list_empty(&qh->qtd_list)) { 465 dwc2_hcd_qh_unlink(hsotg, qh); 466 } 467 } else { 468 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 469 } 470 471 return 0; 472} 473 474/* Must NOT be called with interrupt disabled or spinlock held */ 475static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 476 struct usb_host_endpoint *ep, int retry) 477{ 478 struct dwc2_qtd *qtd, *qtd_tmp; 479 struct dwc2_qh *qh; 480 unsigned long flags; 481 int rc; 482 483 spin_lock_irqsave(&hsotg->lock, flags); 484 485 qh = ep->hcpriv; 486 if (!qh) { 487 rc = -EINVAL; 488 goto err; 489 } 490 491 while (!list_empty(&qh->qtd_list) && retry--) { 492 if (retry == 0) { 493 dev_err(hsotg->dev, 494 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 495 rc = -EBUSY; 496 goto err; 497 } 498 499 spin_unlock_irqrestore(&hsotg->lock, flags); 500 usleep_range(20000, 40000); 501 spin_lock_irqsave(&hsotg->lock, flags); 502 qh = ep->hcpriv; 503 if (!qh) { 504 rc = -EINVAL; 505 goto err; 506 } 507 } 508 509 dwc2_hcd_qh_unlink(hsotg, qh); 510 511 /* Free each QTD in the QH's QTD list */ 512 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 513 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 514 515 ep->hcpriv = NULL; 516 spin_unlock_irqrestore(&hsotg->lock, flags); 517 dwc2_hcd_qh_free(hsotg, qh); 518 519 return 0; 520 521err: 522 ep->hcpriv = NULL; 523 spin_unlock_irqrestore(&hsotg->lock, flags); 524 525 return rc; 526} 527 528/* Must be called with interrupt disabled and spinlock held */ 529static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 530 struct usb_host_endpoint *ep) 531{ 532 struct dwc2_qh *qh = ep->hcpriv; 533 534 if (!qh) 535 return -EINVAL; 536 537 qh->data_toggle = DWC2_HC_PID_DATA0; 538 539 return 0; 540} 541 542/* 543 * Initializes dynamic portions of the DWC_otg HCD state 544 * 545 * Must be called with interrupt disabled and spinlock held 546 */ 547static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 548{ 549 struct dwc2_host_chan *chan, *chan_tmp; 550 int num_channels; 551 int i; 552 553 hsotg->flags.d32 = 0; 554 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 555 556 if (hsotg->core_params->uframe_sched > 0) { 557 hsotg->available_host_channels = 558 hsotg->core_params->host_channels; 559 } else { 560 hsotg->non_periodic_channels = 0; 561 hsotg->periodic_channels = 0; 562 } 563 564 /* 565 * Put all channels in the free channel list and clean up channel 566 * states 567 */ 568 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 569 hc_list_entry) 570 list_del_init(&chan->hc_list_entry); 571 572 num_channels = hsotg->core_params->host_channels; 573 for (i = 0; i < num_channels; i++) { 574 chan = hsotg->hc_ptr_array[i]; 575 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 576 dwc2_hc_cleanup(hsotg, chan); 577 } 578 579 /* Initialize the DWC core for host mode operation */ 580 dwc2_core_host_init(hsotg); 581} 582 583static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 584 struct dwc2_host_chan *chan, 585 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 586{ 587 int hub_addr, hub_port; 588 589 chan->do_split = 1; 590 chan->xact_pos = qtd->isoc_split_pos; 591 chan->complete_split = qtd->complete_split; 592 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 593 chan->hub_addr = (u8)hub_addr; 594 chan->hub_port = (u8)hub_port; 595} 596 597static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 598 struct dwc2_host_chan *chan, 599 struct dwc2_qtd *qtd, void *bufptr) 600{ 601 struct dwc2_hcd_urb *urb = qtd->urb; 602 struct dwc2_hcd_iso_packet_desc *frame_desc; 603 604 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 605 case USB_ENDPOINT_XFER_CONTROL: 606 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 607 608 switch (qtd->control_phase) { 609 case DWC2_CONTROL_SETUP: 610 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 611 chan->do_ping = 0; 612 chan->ep_is_in = 0; 613 chan->data_pid_start = DWC2_HC_PID_SETUP; 614 if (hsotg->core_params->dma_enable > 0) 615 chan->xfer_dma = urb->setup_dma; 616 else 617 chan->xfer_buf = urb->setup_packet; 618 chan->xfer_len = 8; 619 bufptr = NULL; 620 break; 621 622 case DWC2_CONTROL_DATA: 623 dev_vdbg(hsotg->dev, " Control data transaction\n"); 624 chan->data_pid_start = qtd->data_toggle; 625 break; 626 627 case DWC2_CONTROL_STATUS: 628 /* 629 * Direction is opposite of data direction or IN if no 630 * data 631 */ 632 dev_vdbg(hsotg->dev, " Control status transaction\n"); 633 if (urb->length == 0) 634 chan->ep_is_in = 1; 635 else 636 chan->ep_is_in = 637 dwc2_hcd_is_pipe_out(&urb->pipe_info); 638 if (chan->ep_is_in) 639 chan->do_ping = 0; 640 chan->data_pid_start = DWC2_HC_PID_DATA1; 641 chan->xfer_len = 0; 642 if (hsotg->core_params->dma_enable > 0) 643 chan->xfer_dma = hsotg->status_buf_dma; 644 else 645 chan->xfer_buf = hsotg->status_buf; 646 bufptr = NULL; 647 break; 648 } 649 break; 650 651 case USB_ENDPOINT_XFER_BULK: 652 chan->ep_type = USB_ENDPOINT_XFER_BULK; 653 break; 654 655 case USB_ENDPOINT_XFER_INT: 656 chan->ep_type = USB_ENDPOINT_XFER_INT; 657 break; 658 659 case USB_ENDPOINT_XFER_ISOC: 660 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 661 if (hsotg->core_params->dma_desc_enable > 0) 662 break; 663 664 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 665 frame_desc->status = 0; 666 667 if (hsotg->core_params->dma_enable > 0) { 668 chan->xfer_dma = urb->dma; 669 chan->xfer_dma += frame_desc->offset + 670 qtd->isoc_split_offset; 671 } else { 672 chan->xfer_buf = urb->buf; 673 chan->xfer_buf += frame_desc->offset + 674 qtd->isoc_split_offset; 675 } 676 677 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 678 679 /* For non-dword aligned buffers */ 680 if (hsotg->core_params->dma_enable > 0 && 681 (chan->xfer_dma & 0x3)) 682 bufptr = (u8 *)urb->buf + frame_desc->offset + 683 qtd->isoc_split_offset; 684 else 685 bufptr = NULL; 686 687 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 688 if (chan->xfer_len <= 188) 689 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 690 else 691 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 692 } 693 break; 694 } 695 696 return bufptr; 697} 698 699static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 700 struct dwc2_host_chan *chan, 701 struct dwc2_hcd_urb *urb, void *bufptr) 702{ 703 u32 buf_size; 704 struct urb *usb_urb; 705 struct usb_hcd *hcd; 706 707 if (!qh->dw_align_buf) { 708 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 709 buf_size = hsotg->core_params->max_transfer_size; 710 else 711 /* 3072 = 3 max-size Isoc packets */ 712 buf_size = 3072; 713 714 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size, 715 &qh->dw_align_buf_dma, 716 GFP_ATOMIC); 717 if (!qh->dw_align_buf) 718 return -ENOMEM; 719 qh->dw_align_buf_size = buf_size; 720 } 721 722 if (chan->xfer_len) { 723 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 724 usb_urb = urb->priv; 725 726 if (usb_urb) { 727 if (usb_urb->transfer_flags & 728 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG | 729 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) { 730 hcd = dwc2_hsotg_to_hcd(hsotg); 731 usb_hcd_unmap_urb_for_dma(hcd, usb_urb); 732 } 733 if (!chan->ep_is_in) 734 memcpy(qh->dw_align_buf, bufptr, 735 chan->xfer_len); 736 } else { 737 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 738 } 739 } 740 741 chan->align_buf = qh->dw_align_buf_dma; 742 return 0; 743} 744 745/** 746 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 747 * channel and initializes the host channel to perform the transactions. The 748 * host channel is removed from the free list. 749 * 750 * @hsotg: The HCD state structure 751 * @qh: Transactions from the first QTD for this QH are selected and assigned 752 * to a free host channel 753 */ 754static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 755{ 756 struct dwc2_host_chan *chan; 757 struct dwc2_hcd_urb *urb; 758 struct dwc2_qtd *qtd; 759 void *bufptr = NULL; 760 761 if (dbg_qh(qh)) 762 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 763 764 if (list_empty(&qh->qtd_list)) { 765 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 766 return -ENOMEM; 767 } 768 769 if (list_empty(&hsotg->free_hc_list)) { 770 dev_dbg(hsotg->dev, "No free channel to assign\n"); 771 return -ENOMEM; 772 } 773 774 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 775 hc_list_entry); 776 777 /* Remove host channel from free list */ 778 list_del_init(&chan->hc_list_entry); 779 780 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 781 urb = qtd->urb; 782 qh->channel = chan; 783 qtd->in_process = 1; 784 785 /* 786 * Use usb_pipedevice to determine device address. This address is 787 * 0 before the SET_ADDRESS command and the correct address afterward. 788 */ 789 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 790 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 791 chan->speed = qh->dev_speed; 792 chan->max_packet = dwc2_max_packet(qh->maxp); 793 794 chan->xfer_started = 0; 795 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 796 chan->error_state = (qtd->error_count > 0); 797 chan->halt_on_queue = 0; 798 chan->halt_pending = 0; 799 chan->requests = 0; 800 801 /* 802 * The following values may be modified in the transfer type section 803 * below. The xfer_len value may be reduced when the transfer is 804 * started to accommodate the max widths of the XferSize and PktCnt 805 * fields in the HCTSIZn register. 806 */ 807 808 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 809 if (chan->ep_is_in) 810 chan->do_ping = 0; 811 else 812 chan->do_ping = qh->ping_state; 813 814 chan->data_pid_start = qh->data_toggle; 815 chan->multi_count = 1; 816 817 if (urb->actual_length > urb->length && 818 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 819 urb->actual_length = urb->length; 820 821 if (hsotg->core_params->dma_enable > 0) { 822 chan->xfer_dma = urb->dma + urb->actual_length; 823 824 /* For non-dword aligned case */ 825 if (hsotg->core_params->dma_desc_enable <= 0 && 826 (chan->xfer_dma & 0x3)) 827 bufptr = (u8 *)urb->buf + urb->actual_length; 828 } else { 829 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 830 } 831 832 chan->xfer_len = urb->length - urb->actual_length; 833 chan->xfer_count = 0; 834 835 /* Set the split attributes if required */ 836 if (qh->do_split) 837 dwc2_hc_init_split(hsotg, chan, qtd, urb); 838 else 839 chan->do_split = 0; 840 841 /* Set the transfer attributes */ 842 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr); 843 844 /* Non DWORD-aligned buffer case */ 845 if (bufptr) { 846 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 847 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 848 dev_err(hsotg->dev, 849 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 850 __func__); 851 /* Add channel back to free list */ 852 chan->align_buf = 0; 853 chan->multi_count = 0; 854 list_add_tail(&chan->hc_list_entry, 855 &hsotg->free_hc_list); 856 qtd->in_process = 0; 857 qh->channel = NULL; 858 return -ENOMEM; 859 } 860 } else { 861 chan->align_buf = 0; 862 } 863 864 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 865 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 866 /* 867 * This value may be modified when the transfer is started 868 * to reflect the actual transfer length 869 */ 870 chan->multi_count = dwc2_hb_mult(qh->maxp); 871 872 if (hsotg->core_params->dma_desc_enable > 0) 873 chan->desc_list_addr = qh->desc_list_dma; 874 875 dwc2_hc_init(hsotg, chan); 876 chan->qh = qh; 877 878 return 0; 879} 880 881/** 882 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 883 * schedule and assigns them to available host channels. Called from the HCD 884 * interrupt handler functions. 885 * 886 * @hsotg: The HCD state structure 887 * 888 * Return: The types of new transactions that were assigned to host channels 889 */ 890enum dwc2_transaction_type dwc2_hcd_select_transactions( 891 struct dwc2_hsotg *hsotg) 892{ 893 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 894 struct list_head *qh_ptr; 895 struct dwc2_qh *qh; 896 int num_channels; 897 898#ifdef DWC2_DEBUG_SOF 899 dev_vdbg(hsotg->dev, " Select Transactions\n"); 900#endif 901 902 /* Process entries in the periodic ready list */ 903 qh_ptr = hsotg->periodic_sched_ready.next; 904 while (qh_ptr != &hsotg->periodic_sched_ready) { 905 if (list_empty(&hsotg->free_hc_list)) 906 break; 907 if (hsotg->core_params->uframe_sched > 0) { 908 if (hsotg->available_host_channels <= 1) 909 break; 910 hsotg->available_host_channels--; 911 } 912 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 913 if (dwc2_assign_and_init_hc(hsotg, qh)) 914 break; 915 916 /* 917 * Move the QH from the periodic ready schedule to the 918 * periodic assigned schedule 919 */ 920 qh_ptr = qh_ptr->next; 921 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 922 ret_val = DWC2_TRANSACTION_PERIODIC; 923 } 924 925 /* 926 * Process entries in the inactive portion of the non-periodic 927 * schedule. Some free host channels may not be used if they are 928 * reserved for periodic transfers. 929 */ 930 num_channels = hsotg->core_params->host_channels; 931 qh_ptr = hsotg->non_periodic_sched_inactive.next; 932 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 933 if (hsotg->core_params->uframe_sched <= 0 && 934 hsotg->non_periodic_channels >= num_channels - 935 hsotg->periodic_channels) 936 break; 937 if (list_empty(&hsotg->free_hc_list)) 938 break; 939 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 940 if (hsotg->core_params->uframe_sched > 0) { 941 if (hsotg->available_host_channels < 1) 942 break; 943 hsotg->available_host_channels--; 944 } 945 946 if (dwc2_assign_and_init_hc(hsotg, qh)) 947 break; 948 949 /* 950 * Move the QH from the non-periodic inactive schedule to the 951 * non-periodic active schedule 952 */ 953 qh_ptr = qh_ptr->next; 954 list_move(&qh->qh_list_entry, 955 &hsotg->non_periodic_sched_active); 956 957 if (ret_val == DWC2_TRANSACTION_NONE) 958 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 959 else 960 ret_val = DWC2_TRANSACTION_ALL; 961 962 if (hsotg->core_params->uframe_sched <= 0) 963 hsotg->non_periodic_channels++; 964 } 965 966 return ret_val; 967} 968 969/** 970 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 971 * a host channel associated with either a periodic or non-periodic transfer 972 * 973 * @hsotg: The HCD state structure 974 * @chan: Host channel descriptor associated with either a periodic or 975 * non-periodic transfer 976 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 977 * for periodic transfers or the non-periodic Tx FIFO 978 * for non-periodic transfers 979 * 980 * Return: 1 if a request is queued and more requests may be needed to 981 * complete the transfer, 0 if no more requests are required for this 982 * transfer, -1 if there is insufficient space in the Tx FIFO 983 * 984 * This function assumes that there is space available in the appropriate 985 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 986 * it checks whether space is available in the appropriate Tx FIFO. 987 * 988 * Must be called with interrupt disabled and spinlock held 989 */ 990static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 991 struct dwc2_host_chan *chan, 992 u16 fifo_dwords_avail) 993{ 994 int retval = 0; 995 996 if (hsotg->core_params->dma_enable > 0) { 997 if (hsotg->core_params->dma_desc_enable > 0) { 998 if (!chan->xfer_started || 999 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1000 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1001 chan->qh->ping_state = 0; 1002 } 1003 } else if (!chan->xfer_started) { 1004 dwc2_hc_start_transfer(hsotg, chan); 1005 chan->qh->ping_state = 0; 1006 } 1007 } else if (chan->halt_pending) { 1008 /* Don't queue a request if the channel has been halted */ 1009 } else if (chan->halt_on_queue) { 1010 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1011 } else if (chan->do_ping) { 1012 if (!chan->xfer_started) 1013 dwc2_hc_start_transfer(hsotg, chan); 1014 } else if (!chan->ep_is_in || 1015 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1016 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1017 if (!chan->xfer_started) { 1018 dwc2_hc_start_transfer(hsotg, chan); 1019 retval = 1; 1020 } else { 1021 retval = dwc2_hc_continue_transfer(hsotg, chan); 1022 } 1023 } else { 1024 retval = -1; 1025 } 1026 } else { 1027 if (!chan->xfer_started) { 1028 dwc2_hc_start_transfer(hsotg, chan); 1029 retval = 1; 1030 } else { 1031 retval = dwc2_hc_continue_transfer(hsotg, chan); 1032 } 1033 } 1034 1035 return retval; 1036} 1037 1038/* 1039 * Processes periodic channels for the next frame and queues transactions for 1040 * these channels to the DWC_otg controller. After queueing transactions, the 1041 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1042 * to queue as Periodic Tx FIFO or request queue space becomes available. 1043 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1044 * 1045 * Must be called with interrupt disabled and spinlock held 1046 */ 1047static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1048{ 1049 struct list_head *qh_ptr; 1050 struct dwc2_qh *qh; 1051 u32 tx_status; 1052 u32 fspcavail; 1053 u32 gintmsk; 1054 int status; 1055 int no_queue_space = 0; 1056 int no_fifo_space = 0; 1057 u32 qspcavail; 1058 1059 if (dbg_perio()) 1060 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1061 1062 tx_status = readl(hsotg->regs + HPTXSTS); 1063 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1064 TXSTS_QSPCAVAIL_SHIFT; 1065 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1066 TXSTS_FSPCAVAIL_SHIFT; 1067 1068 if (dbg_perio()) { 1069 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1070 qspcavail); 1071 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1072 fspcavail); 1073 } 1074 1075 qh_ptr = hsotg->periodic_sched_assigned.next; 1076 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1077 tx_status = readl(hsotg->regs + HPTXSTS); 1078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1079 TXSTS_QSPCAVAIL_SHIFT; 1080 if (qspcavail == 0) { 1081 no_queue_space = 1; 1082 break; 1083 } 1084 1085 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1086 if (!qh->channel) { 1087 qh_ptr = qh_ptr->next; 1088 continue; 1089 } 1090 1091 /* Make sure EP's TT buffer is clean before queueing qtds */ 1092 if (qh->tt_buffer_dirty) { 1093 qh_ptr = qh_ptr->next; 1094 continue; 1095 } 1096 1097 /* 1098 * Set a flag if we're queuing high-bandwidth in slave mode. 1099 * The flag prevents any halts to get into the request queue in 1100 * the middle of multiple high-bandwidth packets getting queued. 1101 */ 1102 if (hsotg->core_params->dma_enable <= 0 && 1103 qh->channel->multi_count > 1) 1104 hsotg->queuing_high_bandwidth = 1; 1105 1106 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1107 TXSTS_FSPCAVAIL_SHIFT; 1108 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1109 if (status < 0) { 1110 no_fifo_space = 1; 1111 break; 1112 } 1113 1114 /* 1115 * In Slave mode, stay on the current transfer until there is 1116 * nothing more to do or the high-bandwidth request count is 1117 * reached. In DMA mode, only need to queue one request. The 1118 * controller automatically handles multiple packets for 1119 * high-bandwidth transfers. 1120 */ 1121 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1122 qh->channel->requests == qh->channel->multi_count) { 1123 qh_ptr = qh_ptr->next; 1124 /* 1125 * Move the QH from the periodic assigned schedule to 1126 * the periodic queued schedule 1127 */ 1128 list_move(&qh->qh_list_entry, 1129 &hsotg->periodic_sched_queued); 1130 1131 /* done queuing high bandwidth */ 1132 hsotg->queuing_high_bandwidth = 0; 1133 } 1134 } 1135 1136 if (hsotg->core_params->dma_enable <= 0) { 1137 tx_status = readl(hsotg->regs + HPTXSTS); 1138 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1139 TXSTS_QSPCAVAIL_SHIFT; 1140 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1141 TXSTS_FSPCAVAIL_SHIFT; 1142 if (dbg_perio()) { 1143 dev_vdbg(hsotg->dev, 1144 " P Tx Req Queue Space Avail (after queue): %d\n", 1145 qspcavail); 1146 dev_vdbg(hsotg->dev, 1147 " P Tx FIFO Space Avail (after queue): %d\n", 1148 fspcavail); 1149 } 1150 1151 if (!list_empty(&hsotg->periodic_sched_assigned) || 1152 no_queue_space || no_fifo_space) { 1153 /* 1154 * May need to queue more transactions as the request 1155 * queue or Tx FIFO empties. Enable the periodic Tx 1156 * FIFO empty interrupt. (Always use the half-empty 1157 * level to ensure that new requests are loaded as 1158 * soon as possible.) 1159 */ 1160 gintmsk = readl(hsotg->regs + GINTMSK); 1161 gintmsk |= GINTSTS_PTXFEMP; 1162 writel(gintmsk, hsotg->regs + GINTMSK); 1163 } else { 1164 /* 1165 * Disable the Tx FIFO empty interrupt since there are 1166 * no more transactions that need to be queued right 1167 * now. This function is called from interrupt 1168 * handlers to queue more transactions as transfer 1169 * states change. 1170 */ 1171 gintmsk = readl(hsotg->regs + GINTMSK); 1172 gintmsk &= ~GINTSTS_PTXFEMP; 1173 writel(gintmsk, hsotg->regs + GINTMSK); 1174 } 1175 } 1176} 1177 1178/* 1179 * Processes active non-periodic channels and queues transactions for these 1180 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1181 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1182 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1183 * FIFO Empty interrupt is disabled. 1184 * 1185 * Must be called with interrupt disabled and spinlock held 1186 */ 1187static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1188{ 1189 struct list_head *orig_qh_ptr; 1190 struct dwc2_qh *qh; 1191 u32 tx_status; 1192 u32 qspcavail; 1193 u32 fspcavail; 1194 u32 gintmsk; 1195 int status; 1196 int no_queue_space = 0; 1197 int no_fifo_space = 0; 1198 int more_to_do = 0; 1199 1200 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1201 1202 tx_status = readl(hsotg->regs + GNPTXSTS); 1203 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1204 TXSTS_QSPCAVAIL_SHIFT; 1205 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1206 TXSTS_FSPCAVAIL_SHIFT; 1207 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1208 qspcavail); 1209 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1210 fspcavail); 1211 1212 /* 1213 * Keep track of the starting point. Skip over the start-of-list 1214 * entry. 1215 */ 1216 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1217 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1218 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1219 1220 /* 1221 * Process once through the active list or until no more space is 1222 * available in the request queue or the Tx FIFO 1223 */ 1224 do { 1225 tx_status = readl(hsotg->regs + GNPTXSTS); 1226 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1227 TXSTS_QSPCAVAIL_SHIFT; 1228 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1229 no_queue_space = 1; 1230 break; 1231 } 1232 1233 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1234 qh_list_entry); 1235 if (!qh->channel) 1236 goto next; 1237 1238 /* Make sure EP's TT buffer is clean before queueing qtds */ 1239 if (qh->tt_buffer_dirty) 1240 goto next; 1241 1242 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1243 TXSTS_FSPCAVAIL_SHIFT; 1244 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1245 1246 if (status > 0) { 1247 more_to_do = 1; 1248 } else if (status < 0) { 1249 no_fifo_space = 1; 1250 break; 1251 } 1252next: 1253 /* Advance to next QH, skipping start-of-list entry */ 1254 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1255 if (hsotg->non_periodic_qh_ptr == 1256 &hsotg->non_periodic_sched_active) 1257 hsotg->non_periodic_qh_ptr = 1258 hsotg->non_periodic_qh_ptr->next; 1259 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1260 1261 if (hsotg->core_params->dma_enable <= 0) { 1262 tx_status = readl(hsotg->regs + GNPTXSTS); 1263 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1264 TXSTS_QSPCAVAIL_SHIFT; 1265 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1266 TXSTS_FSPCAVAIL_SHIFT; 1267 dev_vdbg(hsotg->dev, 1268 " NP Tx Req Queue Space Avail (after queue): %d\n", 1269 qspcavail); 1270 dev_vdbg(hsotg->dev, 1271 " NP Tx FIFO Space Avail (after queue): %d\n", 1272 fspcavail); 1273 1274 if (more_to_do || no_queue_space || no_fifo_space) { 1275 /* 1276 * May need to queue more transactions as the request 1277 * queue or Tx FIFO empties. Enable the non-periodic 1278 * Tx FIFO empty interrupt. (Always use the half-empty 1279 * level to ensure that new requests are loaded as 1280 * soon as possible.) 1281 */ 1282 gintmsk = readl(hsotg->regs + GINTMSK); 1283 gintmsk |= GINTSTS_NPTXFEMP; 1284 writel(gintmsk, hsotg->regs + GINTMSK); 1285 } else { 1286 /* 1287 * Disable the Tx FIFO empty interrupt since there are 1288 * no more transactions that need to be queued right 1289 * now. This function is called from interrupt 1290 * handlers to queue more transactions as transfer 1291 * states change. 1292 */ 1293 gintmsk = readl(hsotg->regs + GINTMSK); 1294 gintmsk &= ~GINTSTS_NPTXFEMP; 1295 writel(gintmsk, hsotg->regs + GINTMSK); 1296 } 1297 } 1298} 1299 1300/** 1301 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1302 * and queues transactions for these channels to the DWC_otg controller. Called 1303 * from the HCD interrupt handler functions. 1304 * 1305 * @hsotg: The HCD state structure 1306 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1307 * or both) 1308 * 1309 * Must be called with interrupt disabled and spinlock held 1310 */ 1311void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1312 enum dwc2_transaction_type tr_type) 1313{ 1314#ifdef DWC2_DEBUG_SOF 1315 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1316#endif 1317 /* Process host channels associated with periodic transfers */ 1318 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1319 tr_type == DWC2_TRANSACTION_ALL) && 1320 !list_empty(&hsotg->periodic_sched_assigned)) 1321 dwc2_process_periodic_channels(hsotg); 1322 1323 /* Process host channels associated with non-periodic transfers */ 1324 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1325 tr_type == DWC2_TRANSACTION_ALL) { 1326 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1327 dwc2_process_non_periodic_channels(hsotg); 1328 } else { 1329 /* 1330 * Ensure NP Tx FIFO empty interrupt is disabled when 1331 * there are no non-periodic transfers to process 1332 */ 1333 u32 gintmsk = readl(hsotg->regs + GINTMSK); 1334 1335 gintmsk &= ~GINTSTS_NPTXFEMP; 1336 writel(gintmsk, hsotg->regs + GINTMSK); 1337 } 1338 } 1339} 1340 1341static void dwc2_conn_id_status_change(struct work_struct *work) 1342{ 1343 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1344 wf_otg); 1345 u32 count = 0; 1346 u32 gotgctl; 1347 1348 dev_dbg(hsotg->dev, "%s()\n", __func__); 1349 1350 gotgctl = readl(hsotg->regs + GOTGCTL); 1351 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1352 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1353 !!(gotgctl & GOTGCTL_CONID_B)); 1354 1355 /* B-Device connector (Device Mode) */ 1356 if (gotgctl & GOTGCTL_CONID_B) { 1357 /* Wait for switch to device mode */ 1358 dev_dbg(hsotg->dev, "connId B\n"); 1359 while (!dwc2_is_device_mode(hsotg)) { 1360 dev_info(hsotg->dev, 1361 "Waiting for Peripheral Mode, Mode=%s\n", 1362 dwc2_is_host_mode(hsotg) ? "Host" : 1363 "Peripheral"); 1364 usleep_range(20000, 40000); 1365 if (++count > 250) 1366 break; 1367 } 1368 if (count > 250) 1369 dev_err(hsotg->dev, 1370 "Connection id status change timed out\n"); 1371 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1372 dwc2_core_init(hsotg, false, -1); 1373 dwc2_enable_global_interrupts(hsotg); 1374 } else { 1375 /* A-Device connector (Host Mode) */ 1376 dev_dbg(hsotg->dev, "connId A\n"); 1377 while (!dwc2_is_host_mode(hsotg)) { 1378 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1379 dwc2_is_host_mode(hsotg) ? 1380 "Host" : "Peripheral"); 1381 usleep_range(20000, 40000); 1382 if (++count > 250) 1383 break; 1384 } 1385 if (count > 250) 1386 dev_err(hsotg->dev, 1387 "Connection id status change timed out\n"); 1388 hsotg->op_state = OTG_STATE_A_HOST; 1389 1390 /* Initialize the Core for Host mode */ 1391 dwc2_core_init(hsotg, false, -1); 1392 dwc2_enable_global_interrupts(hsotg); 1393 dwc2_hcd_start(hsotg); 1394 } 1395} 1396 1397static void dwc2_wakeup_detected(unsigned long data) 1398{ 1399 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1400 u32 hprt0; 1401 1402 dev_dbg(hsotg->dev, "%s()\n", __func__); 1403 1404 /* 1405 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1406 * so that OPT tests pass with all PHYs.) 1407 */ 1408 hprt0 = dwc2_read_hprt0(hsotg); 1409 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1410 hprt0 &= ~HPRT0_RES; 1411 writel(hprt0, hsotg->regs + HPRT0); 1412 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1413 readl(hsotg->regs + HPRT0)); 1414 1415 dwc2_hcd_rem_wakeup(hsotg); 1416 1417 /* Change to L0 state */ 1418 hsotg->lx_state = DWC2_L0; 1419} 1420 1421static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1422{ 1423 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1424 1425 return hcd->self.b_hnp_enable; 1426} 1427 1428/* Must NOT be called with interrupt disabled or spinlock held */ 1429static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1430{ 1431 unsigned long flags; 1432 u32 hprt0; 1433 u32 pcgctl; 1434 u32 gotgctl; 1435 1436 dev_dbg(hsotg->dev, "%s()\n", __func__); 1437 1438 spin_lock_irqsave(&hsotg->lock, flags); 1439 1440 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1441 gotgctl = readl(hsotg->regs + GOTGCTL); 1442 gotgctl |= GOTGCTL_HSTSETHNPEN; 1443 writel(gotgctl, hsotg->regs + GOTGCTL); 1444 hsotg->op_state = OTG_STATE_A_SUSPEND; 1445 } 1446 1447 hprt0 = dwc2_read_hprt0(hsotg); 1448 hprt0 |= HPRT0_SUSP; 1449 writel(hprt0, hsotg->regs + HPRT0); 1450 1451 /* Update lx_state */ 1452 hsotg->lx_state = DWC2_L2; 1453 1454 /* Suspend the Phy Clock */ 1455 pcgctl = readl(hsotg->regs + PCGCTL); 1456 pcgctl |= PCGCTL_STOPPCLK; 1457 writel(pcgctl, hsotg->regs + PCGCTL); 1458 udelay(10); 1459 1460 /* For HNP the bus must be suspended for at least 200ms */ 1461 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1462 pcgctl = readl(hsotg->regs + PCGCTL); 1463 pcgctl &= ~PCGCTL_STOPPCLK; 1464 writel(pcgctl, hsotg->regs + PCGCTL); 1465 1466 spin_unlock_irqrestore(&hsotg->lock, flags); 1467 1468 usleep_range(200000, 250000); 1469 } else { 1470 spin_unlock_irqrestore(&hsotg->lock, flags); 1471 } 1472} 1473 1474/* Handles hub class-specific requests */ 1475static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1476 u16 wvalue, u16 windex, char *buf, u16 wlength) 1477{ 1478 struct usb_hub_descriptor *hub_desc; 1479 int retval = 0; 1480 u32 hprt0; 1481 u32 port_status; 1482 u32 speed; 1483 u32 pcgctl; 1484 1485 switch (typereq) { 1486 case ClearHubFeature: 1487 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1488 1489 switch (wvalue) { 1490 case C_HUB_LOCAL_POWER: 1491 case C_HUB_OVER_CURRENT: 1492 /* Nothing required here */ 1493 break; 1494 1495 default: 1496 retval = -EINVAL; 1497 dev_err(hsotg->dev, 1498 "ClearHubFeature request %1xh unknown\n", 1499 wvalue); 1500 } 1501 break; 1502 1503 case ClearPortFeature: 1504 if (wvalue != USB_PORT_FEAT_L1) 1505 if (!windex || windex > 1) 1506 goto error; 1507 switch (wvalue) { 1508 case USB_PORT_FEAT_ENABLE: 1509 dev_dbg(hsotg->dev, 1510 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1511 hprt0 = dwc2_read_hprt0(hsotg); 1512 hprt0 |= HPRT0_ENA; 1513 writel(hprt0, hsotg->regs + HPRT0); 1514 break; 1515 1516 case USB_PORT_FEAT_SUSPEND: 1517 dev_dbg(hsotg->dev, 1518 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1519 writel(0, hsotg->regs + PCGCTL); 1520 usleep_range(20000, 40000); 1521 1522 hprt0 = dwc2_read_hprt0(hsotg); 1523 hprt0 |= HPRT0_RES; 1524 writel(hprt0, hsotg->regs + HPRT0); 1525 hprt0 &= ~HPRT0_SUSP; 1526 usleep_range(100000, 150000); 1527 1528 hprt0 &= ~HPRT0_RES; 1529 writel(hprt0, hsotg->regs + HPRT0); 1530 break; 1531 1532 case USB_PORT_FEAT_POWER: 1533 dev_dbg(hsotg->dev, 1534 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1535 hprt0 = dwc2_read_hprt0(hsotg); 1536 hprt0 &= ~HPRT0_PWR; 1537 writel(hprt0, hsotg->regs + HPRT0); 1538 break; 1539 1540 case USB_PORT_FEAT_INDICATOR: 1541 dev_dbg(hsotg->dev, 1542 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1543 /* Port indicator not supported */ 1544 break; 1545 1546 case USB_PORT_FEAT_C_CONNECTION: 1547 /* 1548 * Clears driver's internal Connect Status Change flag 1549 */ 1550 dev_dbg(hsotg->dev, 1551 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1552 hsotg->flags.b.port_connect_status_change = 0; 1553 break; 1554 1555 case USB_PORT_FEAT_C_RESET: 1556 /* Clears driver's internal Port Reset Change flag */ 1557 dev_dbg(hsotg->dev, 1558 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1559 hsotg->flags.b.port_reset_change = 0; 1560 break; 1561 1562 case USB_PORT_FEAT_C_ENABLE: 1563 /* 1564 * Clears the driver's internal Port Enable/Disable 1565 * Change flag 1566 */ 1567 dev_dbg(hsotg->dev, 1568 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1569 hsotg->flags.b.port_enable_change = 0; 1570 break; 1571 1572 case USB_PORT_FEAT_C_SUSPEND: 1573 /* 1574 * Clears the driver's internal Port Suspend Change 1575 * flag, which is set when resume signaling on the host 1576 * port is complete 1577 */ 1578 dev_dbg(hsotg->dev, 1579 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1580 hsotg->flags.b.port_suspend_change = 0; 1581 break; 1582 1583 case USB_PORT_FEAT_C_PORT_L1: 1584 dev_dbg(hsotg->dev, 1585 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1586 hsotg->flags.b.port_l1_change = 0; 1587 break; 1588 1589 case USB_PORT_FEAT_C_OVER_CURRENT: 1590 dev_dbg(hsotg->dev, 1591 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1592 hsotg->flags.b.port_over_current_change = 0; 1593 break; 1594 1595 default: 1596 retval = -EINVAL; 1597 dev_err(hsotg->dev, 1598 "ClearPortFeature request %1xh unknown or unsupported\n", 1599 wvalue); 1600 } 1601 break; 1602 1603 case GetHubDescriptor: 1604 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1605 hub_desc = (struct usb_hub_descriptor *)buf; 1606 hub_desc->bDescLength = 9; 1607 hub_desc->bDescriptorType = 0x29; 1608 hub_desc->bNbrPorts = 1; 1609 hub_desc->wHubCharacteristics = cpu_to_le16(0x08); 1610 hub_desc->bPwrOn2PwrGood = 1; 1611 hub_desc->bHubContrCurrent = 0; 1612 hub_desc->u.hs.DeviceRemovable[0] = 0; 1613 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1614 break; 1615 1616 case GetHubStatus: 1617 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1618 memset(buf, 0, 4); 1619 break; 1620 1621 case GetPortStatus: 1622 dev_vdbg(hsotg->dev, 1623 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1624 hsotg->flags.d32); 1625 if (!windex || windex > 1) 1626 goto error; 1627 1628 port_status = 0; 1629 if (hsotg->flags.b.port_connect_status_change) 1630 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1631 if (hsotg->flags.b.port_enable_change) 1632 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1633 if (hsotg->flags.b.port_suspend_change) 1634 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1635 if (hsotg->flags.b.port_l1_change) 1636 port_status |= USB_PORT_STAT_C_L1 << 16; 1637 if (hsotg->flags.b.port_reset_change) 1638 port_status |= USB_PORT_STAT_C_RESET << 16; 1639 if (hsotg->flags.b.port_over_current_change) { 1640 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1641 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1642 } 1643 1644 if (!hsotg->flags.b.port_connect_status) { 1645 /* 1646 * The port is disconnected, which means the core is 1647 * either in device mode or it soon will be. Just 1648 * return 0's for the remainder of the port status 1649 * since the port register can't be read if the core 1650 * is in device mode. 1651 */ 1652 *(__le32 *)buf = cpu_to_le32(port_status); 1653 break; 1654 } 1655 1656 hprt0 = readl(hsotg->regs + HPRT0); 1657 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1658 1659 if (hprt0 & HPRT0_CONNSTS) 1660 port_status |= USB_PORT_STAT_CONNECTION; 1661 if (hprt0 & HPRT0_ENA) 1662 port_status |= USB_PORT_STAT_ENABLE; 1663 if (hprt0 & HPRT0_SUSP) 1664 port_status |= USB_PORT_STAT_SUSPEND; 1665 if (hprt0 & HPRT0_OVRCURRACT) 1666 port_status |= USB_PORT_STAT_OVERCURRENT; 1667 if (hprt0 & HPRT0_RST) 1668 port_status |= USB_PORT_STAT_RESET; 1669 if (hprt0 & HPRT0_PWR) 1670 port_status |= USB_PORT_STAT_POWER; 1671 1672 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1673 if (speed == HPRT0_SPD_HIGH_SPEED) 1674 port_status |= USB_PORT_STAT_HIGH_SPEED; 1675 else if (speed == HPRT0_SPD_LOW_SPEED) 1676 port_status |= USB_PORT_STAT_LOW_SPEED; 1677 1678 if (hprt0 & HPRT0_TSTCTL_MASK) 1679 port_status |= USB_PORT_STAT_TEST; 1680 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1681 1682 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1683 *(__le32 *)buf = cpu_to_le32(port_status); 1684 break; 1685 1686 case SetHubFeature: 1687 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1688 /* No HUB features supported */ 1689 break; 1690 1691 case SetPortFeature: 1692 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1693 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1694 goto error; 1695 1696 if (!hsotg->flags.b.port_connect_status) { 1697 /* 1698 * The port is disconnected, which means the core is 1699 * either in device mode or it soon will be. Just 1700 * return without doing anything since the port 1701 * register can't be written if the core is in device 1702 * mode. 1703 */ 1704 break; 1705 } 1706 1707 switch (wvalue) { 1708 case USB_PORT_FEAT_SUSPEND: 1709 dev_dbg(hsotg->dev, 1710 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1711 if (windex != hsotg->otg_port) 1712 goto error; 1713 dwc2_port_suspend(hsotg, windex); 1714 break; 1715 1716 case USB_PORT_FEAT_POWER: 1717 dev_dbg(hsotg->dev, 1718 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1719 hprt0 = dwc2_read_hprt0(hsotg); 1720 hprt0 |= HPRT0_PWR; 1721 writel(hprt0, hsotg->regs + HPRT0); 1722 break; 1723 1724 case USB_PORT_FEAT_RESET: 1725 hprt0 = dwc2_read_hprt0(hsotg); 1726 dev_dbg(hsotg->dev, 1727 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1728 pcgctl = readl(hsotg->regs + PCGCTL); 1729 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1730 writel(pcgctl, hsotg->regs + PCGCTL); 1731 /* ??? Original driver does this */ 1732 writel(0, hsotg->regs + PCGCTL); 1733 1734 hprt0 = dwc2_read_hprt0(hsotg); 1735 /* Clear suspend bit if resetting from suspend state */ 1736 hprt0 &= ~HPRT0_SUSP; 1737 1738 /* 1739 * When B-Host the Port reset bit is set in the Start 1740 * HCD Callback function, so that the reset is started 1741 * within 1ms of the HNP success interrupt 1742 */ 1743 if (!dwc2_hcd_is_b_host(hsotg)) { 1744 hprt0 |= HPRT0_PWR | HPRT0_RST; 1745 dev_dbg(hsotg->dev, 1746 "In host mode, hprt0=%08x\n", hprt0); 1747 writel(hprt0, hsotg->regs + HPRT0); 1748 } 1749 1750 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1751 usleep_range(50000, 70000); 1752 hprt0 &= ~HPRT0_RST; 1753 writel(hprt0, hsotg->regs + HPRT0); 1754 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1755 break; 1756 1757 case USB_PORT_FEAT_INDICATOR: 1758 dev_dbg(hsotg->dev, 1759 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1760 /* Not supported */ 1761 break; 1762 1763 default: 1764 retval = -EINVAL; 1765 dev_err(hsotg->dev, 1766 "SetPortFeature %1xh unknown or unsupported\n", 1767 wvalue); 1768 break; 1769 } 1770 break; 1771 1772 default: 1773error: 1774 retval = -EINVAL; 1775 dev_dbg(hsotg->dev, 1776 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1777 typereq, windex, wvalue); 1778 break; 1779 } 1780 1781 return retval; 1782} 1783 1784static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1785{ 1786 int retval; 1787 1788 if (port != 1) 1789 return -EINVAL; 1790 1791 retval = (hsotg->flags.b.port_connect_status_change || 1792 hsotg->flags.b.port_reset_change || 1793 hsotg->flags.b.port_enable_change || 1794 hsotg->flags.b.port_suspend_change || 1795 hsotg->flags.b.port_over_current_change); 1796 1797 if (retval) { 1798 dev_dbg(hsotg->dev, 1799 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1800 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1801 hsotg->flags.b.port_connect_status_change); 1802 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1803 hsotg->flags.b.port_reset_change); 1804 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1805 hsotg->flags.b.port_enable_change); 1806 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1807 hsotg->flags.b.port_suspend_change); 1808 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1809 hsotg->flags.b.port_over_current_change); 1810 } 1811 1812 return retval; 1813} 1814 1815int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1816{ 1817 u32 hfnum = readl(hsotg->regs + HFNUM); 1818 1819#ifdef DWC2_DEBUG_SOF 1820 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1821 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1822#endif 1823 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1824} 1825 1826int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1827{ 1828 return hsotg->op_state == OTG_STATE_B_HOST; 1829} 1830 1831static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1832 int iso_desc_count, 1833 gfp_t mem_flags) 1834{ 1835 struct dwc2_hcd_urb *urb; 1836 u32 size = sizeof(*urb) + iso_desc_count * 1837 sizeof(struct dwc2_hcd_iso_packet_desc); 1838 1839 urb = kzalloc(size, mem_flags); 1840 if (urb) 1841 urb->packet_count = iso_desc_count; 1842 return urb; 1843} 1844 1845static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1846 struct dwc2_hcd_urb *urb, u8 dev_addr, 1847 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1848{ 1849 if (dbg_perio() || 1850 ep_type == USB_ENDPOINT_XFER_BULK || 1851 ep_type == USB_ENDPOINT_XFER_CONTROL) 1852 dev_vdbg(hsotg->dev, 1853 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1854 dev_addr, ep_num, ep_dir, ep_type, mps); 1855 urb->pipe_info.dev_addr = dev_addr; 1856 urb->pipe_info.ep_num = ep_num; 1857 urb->pipe_info.pipe_type = ep_type; 1858 urb->pipe_info.pipe_dir = ep_dir; 1859 urb->pipe_info.mps = mps; 1860} 1861 1862/* 1863 * NOTE: This function will be removed once the peripheral controller code 1864 * is integrated and the driver is stable 1865 */ 1866void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1867{ 1868#ifdef DEBUG 1869 struct dwc2_host_chan *chan; 1870 struct dwc2_hcd_urb *urb; 1871 struct dwc2_qtd *qtd; 1872 int num_channels; 1873 u32 np_tx_status; 1874 u32 p_tx_status; 1875 int i; 1876 1877 num_channels = hsotg->core_params->host_channels; 1878 dev_dbg(hsotg->dev, "\n"); 1879 dev_dbg(hsotg->dev, 1880 "************************************************************\n"); 1881 dev_dbg(hsotg->dev, "HCD State:\n"); 1882 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1883 1884 for (i = 0; i < num_channels; i++) { 1885 chan = hsotg->hc_ptr_array[i]; 1886 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1887 dev_dbg(hsotg->dev, 1888 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1889 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1890 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1891 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1892 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1893 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1894 chan->data_pid_start); 1895 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1896 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1897 chan->xfer_started); 1898 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1899 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1900 (unsigned long)chan->xfer_dma); 1901 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1902 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1903 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1904 chan->halt_on_queue); 1905 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1906 chan->halt_pending); 1907 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1908 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1909 dev_dbg(hsotg->dev, " complete_split: %d\n", 1910 chan->complete_split); 1911 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1912 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1913 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1914 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1915 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1916 1917 if (chan->xfer_started) { 1918 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1919 1920 hfnum = readl(hsotg->regs + HFNUM); 1921 hcchar = readl(hsotg->regs + HCCHAR(i)); 1922 hctsiz = readl(hsotg->regs + HCTSIZ(i)); 1923 hcint = readl(hsotg->regs + HCINT(i)); 1924 hcintmsk = readl(hsotg->regs + HCINTMSK(i)); 1925 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1926 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1927 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1928 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1929 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1930 } 1931 1932 if (!(chan->xfer_started && chan->qh)) 1933 continue; 1934 1935 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1936 if (!qtd->in_process) 1937 break; 1938 urb = qtd->urb; 1939 dev_dbg(hsotg->dev, " URB Info:\n"); 1940 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1941 qtd, urb); 1942 if (urb) { 1943 dev_dbg(hsotg->dev, 1944 " Dev: %d, EP: %d %s\n", 1945 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1946 dwc2_hcd_get_ep_num(&urb->pipe_info), 1947 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1948 "IN" : "OUT"); 1949 dev_dbg(hsotg->dev, 1950 " Max packet size: %d\n", 1951 dwc2_hcd_get_mps(&urb->pipe_info)); 1952 dev_dbg(hsotg->dev, 1953 " transfer_buffer: %p\n", 1954 urb->buf); 1955 dev_dbg(hsotg->dev, 1956 " transfer_dma: %08lx\n", 1957 (unsigned long)urb->dma); 1958 dev_dbg(hsotg->dev, 1959 " transfer_buffer_length: %d\n", 1960 urb->length); 1961 dev_dbg(hsotg->dev, " actual_length: %d\n", 1962 urb->actual_length); 1963 } 1964 } 1965 } 1966 1967 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1968 hsotg->non_periodic_channels); 1969 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1970 hsotg->periodic_channels); 1971 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 1972 np_tx_status = readl(hsotg->regs + GNPTXSTS); 1973 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 1974 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1975 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 1976 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1977 p_tx_status = readl(hsotg->regs + HPTXSTS); 1978 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 1979 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1980 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 1981 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1982 dwc2_hcd_dump_frrem(hsotg); 1983 dwc2_dump_global_registers(hsotg); 1984 dwc2_dump_host_registers(hsotg); 1985 dev_dbg(hsotg->dev, 1986 "************************************************************\n"); 1987 dev_dbg(hsotg->dev, "\n"); 1988#endif 1989} 1990 1991/* 1992 * NOTE: This function will be removed once the peripheral controller code 1993 * is integrated and the driver is stable 1994 */ 1995void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 1996{ 1997#ifdef DWC2_DUMP_FRREM 1998 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 1999 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2000 hsotg->frrem_samples, hsotg->frrem_accum, 2001 hsotg->frrem_samples > 0 ? 2002 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2003 dev_dbg(hsotg->dev, "\n"); 2004 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2005 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2006 hsotg->hfnum_7_samples, 2007 hsotg->hfnum_7_frrem_accum, 2008 hsotg->hfnum_7_samples > 0 ? 2009 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2010 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2011 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2012 hsotg->hfnum_0_samples, 2013 hsotg->hfnum_0_frrem_accum, 2014 hsotg->hfnum_0_samples > 0 ? 2015 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2016 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2017 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2018 hsotg->hfnum_other_samples, 2019 hsotg->hfnum_other_frrem_accum, 2020 hsotg->hfnum_other_samples > 0 ? 2021 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2022 0); 2023 dev_dbg(hsotg->dev, "\n"); 2024 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2025 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2026 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2027 hsotg->hfnum_7_samples_a > 0 ? 2028 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2029 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2030 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2031 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2032 hsotg->hfnum_0_samples_a > 0 ? 2033 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2034 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2035 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2036 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2037 hsotg->hfnum_other_samples_a > 0 ? 2038 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2039 : 0); 2040 dev_dbg(hsotg->dev, "\n"); 2041 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2042 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2043 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2044 hsotg->hfnum_7_samples_b > 0 ? 2045 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2046 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2047 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2048 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2049 (hsotg->hfnum_0_samples_b > 0) ? 2050 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2051 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2052 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2053 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2054 (hsotg->hfnum_other_samples_b > 0) ? 2055 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2056 : 0); 2057#endif 2058} 2059 2060struct wrapper_priv_data { 2061 struct dwc2_hsotg *hsotg; 2062}; 2063 2064/* Gets the dwc2_hsotg from a usb_hcd */ 2065static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2066{ 2067 struct wrapper_priv_data *p; 2068 2069 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2070 return p->hsotg; 2071} 2072 2073static int _dwc2_hcd_start(struct usb_hcd *hcd); 2074 2075void dwc2_host_start(struct dwc2_hsotg *hsotg) 2076{ 2077 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2078 2079 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2080 _dwc2_hcd_start(hcd); 2081} 2082 2083void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2084{ 2085 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2086 2087 hcd->self.is_b_host = 0; 2088} 2089 2090void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2091 int *hub_port) 2092{ 2093 struct urb *urb = context; 2094 2095 if (urb->dev->tt) 2096 *hub_addr = urb->dev->tt->hub->devnum; 2097 else 2098 *hub_addr = 0; 2099 *hub_port = urb->dev->ttport; 2100} 2101 2102int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2103{ 2104 struct urb *urb = context; 2105 2106 return urb->dev->speed; 2107} 2108 2109static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2110 struct urb *urb) 2111{ 2112 struct usb_bus *bus = hcd_to_bus(hcd); 2113 2114 if (urb->interval) 2115 bus->bandwidth_allocated += bw / urb->interval; 2116 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2117 bus->bandwidth_isoc_reqs++; 2118 else 2119 bus->bandwidth_int_reqs++; 2120} 2121 2122static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2123 struct urb *urb) 2124{ 2125 struct usb_bus *bus = hcd_to_bus(hcd); 2126 2127 if (urb->interval) 2128 bus->bandwidth_allocated -= bw / urb->interval; 2129 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2130 bus->bandwidth_isoc_reqs--; 2131 else 2132 bus->bandwidth_int_reqs--; 2133} 2134 2135/* 2136 * Sets the final status of an URB and returns it to the upper layer. Any 2137 * required cleanup of the URB is performed. 2138 * 2139 * Must be called with interrupt disabled and spinlock held 2140 */ 2141void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2142 int status) 2143{ 2144 struct urb *urb; 2145 int i; 2146 2147 if (!qtd) { 2148 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2149 return; 2150 } 2151 2152 if (!qtd->urb) { 2153 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2154 return; 2155 } 2156 2157 urb = qtd->urb->priv; 2158 if (!urb) { 2159 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2160 return; 2161 } 2162 2163 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2164 2165 if (dbg_urb(urb)) 2166 dev_vdbg(hsotg->dev, 2167 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2168 __func__, urb, usb_pipedevice(urb->pipe), 2169 usb_pipeendpoint(urb->pipe), 2170 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2171 urb->actual_length); 2172 2173 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2174 for (i = 0; i < urb->number_of_packets; i++) 2175 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2176 i, urb->iso_frame_desc[i].status); 2177 } 2178 2179 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2180 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2181 for (i = 0; i < urb->number_of_packets; ++i) { 2182 urb->iso_frame_desc[i].actual_length = 2183 dwc2_hcd_urb_get_iso_desc_actual_length( 2184 qtd->urb, i); 2185 urb->iso_frame_desc[i].status = 2186 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2187 } 2188 } 2189 2190 urb->status = status; 2191 if (!status) { 2192 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2193 urb->actual_length < urb->transfer_buffer_length) 2194 urb->status = -EREMOTEIO; 2195 } 2196 2197 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2198 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2199 struct usb_host_endpoint *ep = urb->ep; 2200 2201 if (ep) 2202 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2203 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2204 urb); 2205 } 2206 2207 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2208 urb->hcpriv = NULL; 2209 kfree(qtd->urb); 2210 qtd->urb = NULL; 2211 2212 spin_unlock(&hsotg->lock); 2213 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2214 spin_lock(&hsotg->lock); 2215} 2216 2217/* 2218 * Work queue function for starting the HCD when A-Cable is connected 2219 */ 2220static void dwc2_hcd_start_func(struct work_struct *work) 2221{ 2222 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2223 start_work.work); 2224 2225 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2226 dwc2_host_start(hsotg); 2227} 2228 2229/* 2230 * Reset work queue function 2231 */ 2232static void dwc2_hcd_reset_func(struct work_struct *work) 2233{ 2234 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2235 reset_work.work); 2236 u32 hprt0; 2237 2238 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2239 hprt0 = dwc2_read_hprt0(hsotg); 2240 hprt0 &= ~HPRT0_RST; 2241 writel(hprt0, hsotg->regs + HPRT0); 2242 hsotg->flags.b.port_reset_change = 1; 2243} 2244 2245/* 2246 * ========================================================================= 2247 * Linux HC Driver Functions 2248 * ========================================================================= 2249 */ 2250 2251/* 2252 * Initializes the DWC_otg controller and its root hub and prepares it for host 2253 * mode operation. Activates the root port. Returns 0 on success and a negative 2254 * error code on failure. 2255 */ 2256static int _dwc2_hcd_start(struct usb_hcd *hcd) 2257{ 2258 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2259 struct usb_bus *bus = hcd_to_bus(hcd); 2260 unsigned long flags; 2261 2262 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2263 2264 spin_lock_irqsave(&hsotg->lock, flags); 2265 2266 hcd->state = HC_STATE_RUNNING; 2267 2268 if (dwc2_is_device_mode(hsotg)) { 2269 spin_unlock_irqrestore(&hsotg->lock, flags); 2270 return 0; /* why 0 ?? */ 2271 } 2272 2273 dwc2_hcd_reinit(hsotg); 2274 2275 /* Initialize and connect root hub if one is not already attached */ 2276 if (bus->root_hub) { 2277 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2278 /* Inform the HUB driver to resume */ 2279 usb_hcd_resume_root_hub(hcd); 2280 } 2281 2282 spin_unlock_irqrestore(&hsotg->lock, flags); 2283 return 0; 2284} 2285 2286/* 2287 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2288 * stopped. 2289 */ 2290static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2291{ 2292 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2293 unsigned long flags; 2294 2295 spin_lock_irqsave(&hsotg->lock, flags); 2296 dwc2_hcd_stop(hsotg); 2297 spin_unlock_irqrestore(&hsotg->lock, flags); 2298 2299 usleep_range(1000, 3000); 2300} 2301 2302/* Returns the current frame number */ 2303static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2304{ 2305 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2306 2307 return dwc2_hcd_get_frame_number(hsotg); 2308} 2309 2310static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2311 char *fn_name) 2312{ 2313#ifdef VERBOSE_DEBUG 2314 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2315 char *pipetype; 2316 char *speed; 2317 2318 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2319 dev_vdbg(hsotg->dev, " Device address: %d\n", 2320 usb_pipedevice(urb->pipe)); 2321 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2322 usb_pipeendpoint(urb->pipe), 2323 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2324 2325 switch (usb_pipetype(urb->pipe)) { 2326 case PIPE_CONTROL: 2327 pipetype = "CONTROL"; 2328 break; 2329 case PIPE_BULK: 2330 pipetype = "BULK"; 2331 break; 2332 case PIPE_INTERRUPT: 2333 pipetype = "INTERRUPT"; 2334 break; 2335 case PIPE_ISOCHRONOUS: 2336 pipetype = "ISOCHRONOUS"; 2337 break; 2338 default: 2339 pipetype = "UNKNOWN"; 2340 break; 2341 } 2342 2343 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2344 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2345 "IN" : "OUT"); 2346 2347 switch (urb->dev->speed) { 2348 case USB_SPEED_HIGH: 2349 speed = "HIGH"; 2350 break; 2351 case USB_SPEED_FULL: 2352 speed = "FULL"; 2353 break; 2354 case USB_SPEED_LOW: 2355 speed = "LOW"; 2356 break; 2357 default: 2358 speed = "UNKNOWN"; 2359 break; 2360 } 2361 2362 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2363 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2364 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2365 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2366 urb->transfer_buffer_length); 2367 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2368 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2369 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2370 urb->setup_packet, (unsigned long)urb->setup_dma); 2371 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2372 2373 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2374 int i; 2375 2376 for (i = 0; i < urb->number_of_packets; i++) { 2377 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2378 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2379 urb->iso_frame_desc[i].offset, 2380 urb->iso_frame_desc[i].length); 2381 } 2382 } 2383#endif 2384} 2385 2386/* 2387 * Starts processing a USB transfer request specified by a USB Request Block 2388 * (URB). mem_flags indicates the type of memory allocation to use while 2389 * processing this URB. 2390 */ 2391static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2392 gfp_t mem_flags) 2393{ 2394 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2395 struct usb_host_endpoint *ep = urb->ep; 2396 struct dwc2_hcd_urb *dwc2_urb; 2397 int i; 2398 int retval; 2399 int alloc_bandwidth = 0; 2400 u8 ep_type = 0; 2401 u32 tflags = 0; 2402 void *buf; 2403 unsigned long flags; 2404 2405 if (dbg_urb(urb)) { 2406 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2407 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2408 } 2409 2410 if (ep == NULL) 2411 return -EINVAL; 2412 2413 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2414 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2415 spin_lock_irqsave(&hsotg->lock, flags); 2416 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2417 alloc_bandwidth = 1; 2418 spin_unlock_irqrestore(&hsotg->lock, flags); 2419 } 2420 2421 switch (usb_pipetype(urb->pipe)) { 2422 case PIPE_CONTROL: 2423 ep_type = USB_ENDPOINT_XFER_CONTROL; 2424 break; 2425 case PIPE_ISOCHRONOUS: 2426 ep_type = USB_ENDPOINT_XFER_ISOC; 2427 break; 2428 case PIPE_BULK: 2429 ep_type = USB_ENDPOINT_XFER_BULK; 2430 break; 2431 case PIPE_INTERRUPT: 2432 ep_type = USB_ENDPOINT_XFER_INT; 2433 break; 2434 default: 2435 dev_warn(hsotg->dev, "Wrong ep type\n"); 2436 } 2437 2438 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2439 mem_flags); 2440 if (!dwc2_urb) 2441 return -ENOMEM; 2442 2443 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2444 usb_pipeendpoint(urb->pipe), ep_type, 2445 usb_pipein(urb->pipe), 2446 usb_maxpacket(urb->dev, urb->pipe, 2447 !(usb_pipein(urb->pipe)))); 2448 2449 buf = urb->transfer_buffer; 2450 2451 if (hcd->self.uses_dma) { 2452 if (!buf && (urb->transfer_dma & 3)) { 2453 dev_err(hsotg->dev, 2454 "%s: unaligned transfer with no transfer_buffer", 2455 __func__); 2456 retval = -EINVAL; 2457 goto fail1; 2458 } 2459 } 2460 2461 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2462 tflags |= URB_GIVEBACK_ASAP; 2463 if (urb->transfer_flags & URB_ZERO_PACKET) 2464 tflags |= URB_SEND_ZERO_PACKET; 2465 2466 dwc2_urb->priv = urb; 2467 dwc2_urb->buf = buf; 2468 dwc2_urb->dma = urb->transfer_dma; 2469 dwc2_urb->length = urb->transfer_buffer_length; 2470 dwc2_urb->setup_packet = urb->setup_packet; 2471 dwc2_urb->setup_dma = urb->setup_dma; 2472 dwc2_urb->flags = tflags; 2473 dwc2_urb->interval = urb->interval; 2474 dwc2_urb->status = -EINPROGRESS; 2475 2476 for (i = 0; i < urb->number_of_packets; ++i) 2477 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2478 urb->iso_frame_desc[i].offset, 2479 urb->iso_frame_desc[i].length); 2480 2481 urb->hcpriv = dwc2_urb; 2482 2483 spin_lock_irqsave(&hsotg->lock, flags); 2484 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2485 spin_unlock_irqrestore(&hsotg->lock, flags); 2486 if (retval) 2487 goto fail1; 2488 2489 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags); 2490 if (retval) 2491 goto fail2; 2492 2493 if (alloc_bandwidth) { 2494 spin_lock_irqsave(&hsotg->lock, flags); 2495 dwc2_allocate_bus_bandwidth(hcd, 2496 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2497 urb); 2498 spin_unlock_irqrestore(&hsotg->lock, flags); 2499 } 2500 2501 return 0; 2502 2503fail2: 2504 spin_lock_irqsave(&hsotg->lock, flags); 2505 dwc2_urb->priv = NULL; 2506 usb_hcd_unlink_urb_from_ep(hcd, urb); 2507 spin_unlock_irqrestore(&hsotg->lock, flags); 2508fail1: 2509 urb->hcpriv = NULL; 2510 kfree(dwc2_urb); 2511 2512 return retval; 2513} 2514 2515/* 2516 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2517 */ 2518static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2519 int status) 2520{ 2521 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2522 int rc; 2523 unsigned long flags; 2524 2525 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2526 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2527 2528 spin_lock_irqsave(&hsotg->lock, flags); 2529 2530 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2531 if (rc) 2532 goto out; 2533 2534 if (!urb->hcpriv) { 2535 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2536 goto out; 2537 } 2538 2539 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2540 2541 usb_hcd_unlink_urb_from_ep(hcd, urb); 2542 2543 kfree(urb->hcpriv); 2544 urb->hcpriv = NULL; 2545 2546 /* Higher layer software sets URB status */ 2547 spin_unlock(&hsotg->lock); 2548 usb_hcd_giveback_urb(hcd, urb, status); 2549 spin_lock(&hsotg->lock); 2550 2551 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2552 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2553out: 2554 spin_unlock_irqrestore(&hsotg->lock, flags); 2555 2556 return rc; 2557} 2558 2559/* 2560 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2561 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2562 * must already be dequeued. 2563 */ 2564static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2565 struct usb_host_endpoint *ep) 2566{ 2567 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2568 2569 dev_dbg(hsotg->dev, 2570 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2571 ep->desc.bEndpointAddress, ep->hcpriv); 2572 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2573} 2574 2575/* 2576 * Resets endpoint specific parameter values, in current version used to reset 2577 * the data toggle (as a WA). This function can be called from usb_clear_halt 2578 * routine. 2579 */ 2580static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2581 struct usb_host_endpoint *ep) 2582{ 2583 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2584 unsigned long flags; 2585 2586 dev_dbg(hsotg->dev, 2587 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2588 ep->desc.bEndpointAddress); 2589 2590 spin_lock_irqsave(&hsotg->lock, flags); 2591 dwc2_hcd_endpoint_reset(hsotg, ep); 2592 spin_unlock_irqrestore(&hsotg->lock, flags); 2593} 2594 2595/* 2596 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2597 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2598 * interrupt. 2599 * 2600 * This function is called by the USB core when an interrupt occurs 2601 */ 2602static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2603{ 2604 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2605 2606 return dwc2_handle_hcd_intr(hsotg); 2607} 2608 2609/* 2610 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2611 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2612 * is the status change indicator for the single root port. Returns 1 if either 2613 * change indicator is 1, otherwise returns 0. 2614 */ 2615static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2616{ 2617 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2618 2619 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2620 return buf[0] != 0; 2621} 2622 2623/* Handles hub class-specific requests */ 2624static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2625 u16 windex, char *buf, u16 wlength) 2626{ 2627 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2628 wvalue, windex, buf, wlength); 2629 return retval; 2630} 2631 2632/* Handles hub TT buffer clear completions */ 2633static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2634 struct usb_host_endpoint *ep) 2635{ 2636 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2637 struct dwc2_qh *qh; 2638 unsigned long flags; 2639 2640 qh = ep->hcpriv; 2641 if (!qh) 2642 return; 2643 2644 spin_lock_irqsave(&hsotg->lock, flags); 2645 qh->tt_buffer_dirty = 0; 2646 2647 if (hsotg->flags.b.port_connect_status) 2648 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2649 2650 spin_unlock_irqrestore(&hsotg->lock, flags); 2651} 2652 2653static struct hc_driver dwc2_hc_driver = { 2654 .description = "dwc2_hsotg", 2655 .product_desc = "DWC OTG Controller", 2656 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2657 2658 .irq = _dwc2_hcd_irq, 2659 .flags = HCD_MEMORY | HCD_USB2, 2660 2661 .start = _dwc2_hcd_start, 2662 .stop = _dwc2_hcd_stop, 2663 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2664 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2665 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2666 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2667 .get_frame_number = _dwc2_hcd_get_frame_number, 2668 2669 .hub_status_data = _dwc2_hcd_hub_status_data, 2670 .hub_control = _dwc2_hcd_hub_control, 2671 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2672}; 2673 2674/* 2675 * Frees secondary storage associated with the dwc2_hsotg structure contained 2676 * in the struct usb_hcd field 2677 */ 2678static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2679{ 2680 u32 ahbcfg; 2681 u32 dctl; 2682 int i; 2683 2684 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2685 2686 /* Free memory for QH/QTD lists */ 2687 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2688 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2689 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2690 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2691 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2692 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2693 2694 /* Free memory for the host channels */ 2695 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2696 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2697 2698 if (chan != NULL) { 2699 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2700 i, chan); 2701 hsotg->hc_ptr_array[i] = NULL; 2702 kfree(chan); 2703 } 2704 } 2705 2706 if (hsotg->core_params->dma_enable > 0) { 2707 if (hsotg->status_buf) { 2708 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 2709 hsotg->status_buf, 2710 hsotg->status_buf_dma); 2711 hsotg->status_buf = NULL; 2712 } 2713 } else { 2714 kfree(hsotg->status_buf); 2715 hsotg->status_buf = NULL; 2716 } 2717 2718 ahbcfg = readl(hsotg->regs + GAHBCFG); 2719 2720 /* Disable all interrupts */ 2721 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2722 writel(ahbcfg, hsotg->regs + GAHBCFG); 2723 writel(0, hsotg->regs + GINTMSK); 2724 2725 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2726 dctl = readl(hsotg->regs + DCTL); 2727 dctl |= DCTL_SFTDISCON; 2728 writel(dctl, hsotg->regs + DCTL); 2729 } 2730 2731 if (hsotg->wq_otg) { 2732 if (!cancel_work_sync(&hsotg->wf_otg)) 2733 flush_workqueue(hsotg->wq_otg); 2734 destroy_workqueue(hsotg->wq_otg); 2735 } 2736 2737 kfree(hsotg->core_params); 2738 hsotg->core_params = NULL; 2739 del_timer(&hsotg->wkp_timer); 2740} 2741 2742static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2743{ 2744 /* Turn off all host-specific interrupts */ 2745 dwc2_disable_host_interrupts(hsotg); 2746 2747 dwc2_hcd_free(hsotg); 2748} 2749 2750/* 2751 * Sets all parameters to the given value. 2752 * 2753 * Assumes that the dwc2_core_params struct contains only integers. 2754 */ 2755void dwc2_set_all_params(struct dwc2_core_params *params, int value) 2756{ 2757 int *p = (int *)params; 2758 size_t size = sizeof(*params) / sizeof(*p); 2759 int i; 2760 2761 for (i = 0; i < size; i++) 2762 p[i] = value; 2763} 2764EXPORT_SYMBOL_GPL(dwc2_set_all_params); 2765 2766/* 2767 * Initializes the HCD. This function allocates memory for and initializes the 2768 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2769 * USB bus with the core and calls the hc_driver->start() function. It returns 2770 * a negative error on failure. 2771 */ 2772int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 2773 const struct dwc2_core_params *params) 2774{ 2775 struct usb_hcd *hcd; 2776 struct dwc2_host_chan *channel; 2777 u32 hcfg; 2778 int i, num_channels; 2779 int retval; 2780 2781 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2782 2783 /* Detect config values from hardware */ 2784 retval = dwc2_get_hwparams(hsotg); 2785 2786 if (retval) 2787 return retval; 2788 2789 retval = -ENOMEM; 2790 2791 hcfg = readl(hsotg->regs + HCFG); 2792 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 2793 2794#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2795 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 2796 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2797 if (!hsotg->frame_num_array) 2798 goto error1; 2799 hsotg->last_frame_num_array = kzalloc( 2800 sizeof(*hsotg->last_frame_num_array) * 2801 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2802 if (!hsotg->last_frame_num_array) 2803 goto error1; 2804 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2805#endif 2806 2807 hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL); 2808 if (!hsotg->core_params) 2809 goto error1; 2810 2811 dwc2_set_all_params(hsotg->core_params, -1); 2812 2813 /* Validate parameter values */ 2814 dwc2_set_parameters(hsotg, params); 2815 2816 /* Check if the bus driver or platform code has setup a dma_mask */ 2817 if (hsotg->core_params->dma_enable > 0 && 2818 hsotg->dev->dma_mask == NULL) { 2819 dev_warn(hsotg->dev, 2820 "dma_mask not set, disabling DMA\n"); 2821 hsotg->core_params->dma_enable = 0; 2822 hsotg->core_params->dma_desc_enable = 0; 2823 } 2824 2825 /* Set device flags indicating whether the HCD supports DMA */ 2826 if (hsotg->core_params->dma_enable > 0) { 2827 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2828 dev_warn(hsotg->dev, "can't set DMA mask\n"); 2829 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2830 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 2831 } 2832 2833 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 2834 if (!hcd) 2835 goto error1; 2836 2837 if (hsotg->core_params->dma_enable <= 0) 2838 hcd->self.uses_dma = 0; 2839 2840 hcd->has_tt = 1; 2841 2842 spin_lock_init(&hsotg->lock); 2843 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 2844 hsotg->priv = hcd; 2845 2846 /* 2847 * Disable the global interrupt until all the interrupt handlers are 2848 * installed 2849 */ 2850 dwc2_disable_global_interrupts(hsotg); 2851 2852 /* Initialize the DWC_otg core, and select the Phy type */ 2853 retval = dwc2_core_init(hsotg, true, irq); 2854 if (retval) 2855 goto error2; 2856 2857 /* Create new workqueue and init work */ 2858 retval = -ENOMEM; 2859 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 2860 if (!hsotg->wq_otg) { 2861 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2862 goto error2; 2863 } 2864 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 2865 2866 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 2867 (unsigned long)hsotg); 2868 2869 /* Initialize the non-periodic schedule */ 2870 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2871 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2872 2873 /* Initialize the periodic schedule */ 2874 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2875 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2876 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2877 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2878 2879 /* 2880 * Create a host channel descriptor for each host channel implemented 2881 * in the controller. Initialize the channel descriptor array. 2882 */ 2883 INIT_LIST_HEAD(&hsotg->free_hc_list); 2884 num_channels = hsotg->core_params->host_channels; 2885 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2886 2887 for (i = 0; i < num_channels; i++) { 2888 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 2889 if (channel == NULL) 2890 goto error3; 2891 channel->hc_num = i; 2892 hsotg->hc_ptr_array[i] = channel; 2893 } 2894 2895 if (hsotg->core_params->uframe_sched > 0) 2896 dwc2_hcd_init_usecs(hsotg); 2897 2898 /* Initialize hsotg start work */ 2899 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2900 2901 /* Initialize port reset work */ 2902 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2903 2904 /* 2905 * Allocate space for storing data on status transactions. Normally no 2906 * data is sent, but this space acts as a bit bucket. This must be 2907 * done after usb_add_hcd since that function allocates the DMA buffer 2908 * pool. 2909 */ 2910 if (hsotg->core_params->dma_enable > 0) 2911 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 2912 DWC2_HCD_STATUS_BUF_SIZE, 2913 &hsotg->status_buf_dma, GFP_KERNEL); 2914 else 2915 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 2916 GFP_KERNEL); 2917 2918 if (!hsotg->status_buf) 2919 goto error3; 2920 2921 hsotg->otg_port = 1; 2922 hsotg->frame_list = NULL; 2923 hsotg->frame_list_dma = 0; 2924 hsotg->periodic_qh_count = 0; 2925 2926 /* Initiate lx_state to L3 disconnected state */ 2927 hsotg->lx_state = DWC2_L3; 2928 2929 hcd->self.otg_port = hsotg->otg_port; 2930 2931 /* Don't support SG list at this point */ 2932 hcd->self.sg_tablesize = 0; 2933 2934 /* 2935 * Finish generic HCD initialization and start the HCD. This function 2936 * allocates the DMA buffer pool, registers the USB bus, requests the 2937 * IRQ line, and calls hcd_start method. 2938 */ 2939 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 2940 if (retval < 0) 2941 goto error3; 2942 2943 device_wakeup_enable(hcd->self.controller); 2944 2945 dwc2_hcd_dump_state(hsotg); 2946 2947 dwc2_enable_global_interrupts(hsotg); 2948 2949 return 0; 2950 2951error3: 2952 dwc2_hcd_release(hsotg); 2953error2: 2954 usb_put_hcd(hcd); 2955error1: 2956 kfree(hsotg->core_params); 2957 2958#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2959 kfree(hsotg->last_frame_num_array); 2960 kfree(hsotg->frame_num_array); 2961#endif 2962 2963 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2964 return retval; 2965} 2966EXPORT_SYMBOL_GPL(dwc2_hcd_init); 2967 2968/* 2969 * Removes the HCD. 2970 * Frees memory and resources associated with the HCD and deregisters the bus. 2971 */ 2972void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 2973{ 2974 struct usb_hcd *hcd; 2975 2976 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 2977 2978 hcd = dwc2_hsotg_to_hcd(hsotg); 2979 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 2980 2981 if (!hcd) { 2982 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 2983 __func__); 2984 return; 2985 } 2986 2987 usb_remove_hcd(hcd); 2988 hsotg->priv = NULL; 2989 dwc2_hcd_release(hsotg); 2990 usb_put_hcd(hcd); 2991 2992#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2993 kfree(hsotg->last_frame_num_array); 2994 kfree(hsotg->frame_num_array); 2995#endif 2996} 2997EXPORT_SYMBOL_GPL(dwc2_hcd_remove); 2998