1/* 2 * ca91c042.h 3 * 4 * Support for the Tundra Universe 1 and Universe II VME bridge chips 5 * 6 * Author: Tom Armistead 7 * Updated by Ajit Prem 8 * Copyright 2004 Motorola Inc. 9 * 10 * Further updated by Martyn Welch <martyn.welch@ge.com> 11 * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc. 12 * 13 * Derived from ca91c042.h by Michael Wyrick 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 21#ifndef _CA91CX42_H 22#define _CA91CX42_H 23 24#ifndef PCI_VENDOR_ID_TUNDRA 25#define PCI_VENDOR_ID_TUNDRA 0x10e3 26#endif 27 28#ifndef PCI_DEVICE_ID_TUNDRA_CA91C142 29#define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000 30#endif 31 32/* 33 * Define the number of each that the CA91C142 supports. 34 */ 35#define CA91C142_MAX_MASTER 8 /* Max Master Windows */ 36#define CA91C142_MAX_SLAVE 8 /* Max Slave Windows */ 37#define CA91C142_MAX_DMA 1 /* Max DMA Controllers */ 38#define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */ 39 40/* Structure used to hold driver specific information */ 41struct ca91cx42_driver { 42 void __iomem *base; /* Base Address of device registers */ 43 wait_queue_head_t dma_queue; 44 wait_queue_head_t iack_queue; 45 wait_queue_head_t mbox_queue; 46 void (*lm_callback[4])(int); /* Called in interrupt handler */ 47 void *crcsr_kernel; 48 dma_addr_t crcsr_bus; 49 struct mutex vme_rmw; /* Only one RMW cycle at a time */ 50 struct mutex vme_int; /* 51 * Only one VME interrupt can be 52 * generated at a time, provide locking 53 */ 54}; 55 56/* See Page 2-77 in the Universe User Manual */ 57struct ca91cx42_dma_descriptor { 58 unsigned int dctl; /* DMA Control */ 59 unsigned int dtbc; /* Transfer Byte Count */ 60 unsigned int dla; /* PCI Address */ 61 unsigned int res1; /* Reserved */ 62 unsigned int dva; /* Vme Address */ 63 unsigned int res2; /* Reserved */ 64 unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ 65 unsigned int res3; /* Reserved */ 66}; 67 68struct ca91cx42_dma_entry { 69 struct ca91cx42_dma_descriptor descriptor; 70 struct list_head list; 71}; 72 73/* Universe Register Offsets */ 74/* general PCI configuration registers */ 75#define CA91CX42_PCI_ID 0x000 76#define CA91CX42_PCI_CSR 0x004 77#define CA91CX42_PCI_CLASS 0x008 78#define CA91CX42_PCI_MISC0 0x00C 79#define CA91CX42_PCI_BS 0x010 80#define CA91CX42_PCI_MISC1 0x03C 81 82#define LSI0_CTL 0x0100 83#define LSI0_BS 0x0104 84#define LSI0_BD 0x0108 85#define LSI0_TO 0x010C 86 87#define LSI1_CTL 0x0114 88#define LSI1_BS 0x0118 89#define LSI1_BD 0x011C 90#define LSI1_TO 0x0120 91 92#define LSI2_CTL 0x0128 93#define LSI2_BS 0x012C 94#define LSI2_BD 0x0130 95#define LSI2_TO 0x0134 96 97#define LSI3_CTL 0x013C 98#define LSI3_BS 0x0140 99#define LSI3_BD 0x0144 100#define LSI3_TO 0x0148 101 102#define LSI4_CTL 0x01A0 103#define LSI4_BS 0x01A4 104#define LSI4_BD 0x01A8 105#define LSI4_TO 0x01AC 106 107#define LSI5_CTL 0x01B4 108#define LSI5_BS 0x01B8 109#define LSI5_BD 0x01BC 110#define LSI5_TO 0x01C0 111 112#define LSI6_CTL 0x01C8 113#define LSI6_BS 0x01CC 114#define LSI6_BD 0x01D0 115#define LSI6_TO 0x01D4 116 117#define LSI7_CTL 0x01DC 118#define LSI7_BS 0x01E0 119#define LSI7_BD 0x01E4 120#define LSI7_TO 0x01E8 121 122static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL, 123 LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL }; 124 125static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS, 126 LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS }; 127 128static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD, 129 LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD }; 130 131static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO, 132 LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO }; 133 134#define SCYC_CTL 0x0170 135#define SCYC_ADDR 0x0174 136#define SCYC_EN 0x0178 137#define SCYC_CMP 0x017C 138#define SCYC_SWP 0x0180 139#define LMISC 0x0184 140#define SLSI 0x0188 141#define L_CMDERR 0x018C 142#define LAERR 0x0190 143 144#define DCTL 0x0200 145#define DTBC 0x0204 146#define DLA 0x0208 147#define DVA 0x0210 148#define DCPP 0x0218 149#define DGCS 0x0220 150#define D_LLUE 0x0224 151 152#define LINT_EN 0x0300 153#define LINT_STAT 0x0304 154#define LINT_MAP0 0x0308 155#define LINT_MAP1 0x030C 156#define VINT_EN 0x0310 157#define VINT_STAT 0x0314 158#define VINT_MAP0 0x0318 159#define VINT_MAP1 0x031C 160#define STATID 0x0320 161 162#define V1_STATID 0x0324 163#define V2_STATID 0x0328 164#define V3_STATID 0x032C 165#define V4_STATID 0x0330 166#define V5_STATID 0x0334 167#define V6_STATID 0x0338 168#define V7_STATID 0x033C 169 170static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID, 171 V4_STATID, V5_STATID, V6_STATID, 172 V7_STATID }; 173 174#define LINT_MAP2 0x0340 175#define VINT_MAP2 0x0344 176 177#define MBOX0 0x0348 178#define MBOX1 0x034C 179#define MBOX2 0x0350 180#define MBOX3 0x0354 181#define SEMA0 0x0358 182#define SEMA1 0x035C 183 184#define MAST_CTL 0x0400 185#define MISC_CTL 0x0404 186#define MISC_STAT 0x0408 187#define USER_AM 0x040C 188 189#define VSI0_CTL 0x0F00 190#define VSI0_BS 0x0F04 191#define VSI0_BD 0x0F08 192#define VSI0_TO 0x0F0C 193 194#define VSI1_CTL 0x0F14 195#define VSI1_BS 0x0F18 196#define VSI1_BD 0x0F1C 197#define VSI1_TO 0x0F20 198 199#define VSI2_CTL 0x0F28 200#define VSI2_BS 0x0F2C 201#define VSI2_BD 0x0F30 202#define VSI2_TO 0x0F34 203 204#define VSI3_CTL 0x0F3C 205#define VSI3_BS 0x0F40 206#define VSI3_BD 0x0F44 207#define VSI3_TO 0x0F48 208 209#define LM_CTL 0x0F64 210#define LM_BS 0x0F68 211 212#define VRAI_CTL 0x0F70 213 214#define VRAI_BS 0x0F74 215#define VCSR_CTL 0x0F80 216#define VCSR_TO 0x0F84 217#define V_AMERR 0x0F88 218#define VAERR 0x0F8C 219 220#define VSI4_CTL 0x0F90 221#define VSI4_BS 0x0F94 222#define VSI4_BD 0x0F98 223#define VSI4_TO 0x0F9C 224 225#define VSI5_CTL 0x0FA4 226#define VSI5_BS 0x0FA8 227#define VSI5_BD 0x0FAC 228#define VSI5_TO 0x0FB0 229 230#define VSI6_CTL 0x0FB8 231#define VSI6_BS 0x0FBC 232#define VSI6_BD 0x0FC0 233#define VSI6_TO 0x0FC4 234 235#define VSI7_CTL 0x0FCC 236#define VSI7_BS 0x0FD0 237#define VSI7_BD 0x0FD4 238#define VSI7_TO 0x0FD8 239 240static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL, 241 VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL }; 242 243static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS, 244 VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS }; 245 246static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD, 247 VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD }; 248 249static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO, 250 VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO }; 251 252#define VCSR_CLR 0x0FF4 253#define VCSR_SET 0x0FF8 254#define VCSR_BS 0x0FFC 255 256/* 257 * PCI Class Register 258 * offset 008 259 */ 260#define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000 261#define CA91CX42_OF_PCI_CLASS_BASE 24 262#define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000 263#define CA91CX42_OF_PCI_CLASS_SUB 16 264#define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00 265#define CA91CX42_OF_PCI_CLASS_PROG 8 266#define CA91CX42_BM_PCI_CLASS_RID 0x000000FF 267#define CA91CX42_OF_PCI_CLASS_RID 0 268 269#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0 270#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1 271 272/* 273 * PCI Misc Register 274 * offset 00C 275 */ 276#define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000 277#define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000 278#define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000 279#define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000 280#define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000 281#define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00 282#define CA91CX42_OF_PCI_MISC0_LTIMER 8 283 284 285/* 286 * LSI Control Register 287 * offset 100 288 */ 289#define CA91CX42_LSI_CTL_EN (1<<31) 290#define CA91CX42_LSI_CTL_PWEN (1<<30) 291 292#define CA91CX42_LSI_CTL_VDW_M (3<<22) 293#define CA91CX42_LSI_CTL_VDW_D8 0 294#define CA91CX42_LSI_CTL_VDW_D16 (1<<22) 295#define CA91CX42_LSI_CTL_VDW_D32 (1<<23) 296#define CA91CX42_LSI_CTL_VDW_D64 (3<<22) 297 298#define CA91CX42_LSI_CTL_VAS_M (7<<16) 299#define CA91CX42_LSI_CTL_VAS_A16 0 300#define CA91CX42_LSI_CTL_VAS_A24 (1<<16) 301#define CA91CX42_LSI_CTL_VAS_A32 (1<<17) 302#define CA91CX42_LSI_CTL_VAS_CRCSR (5<<16) 303#define CA91CX42_LSI_CTL_VAS_USER1 (3<<17) 304#define CA91CX42_LSI_CTL_VAS_USER2 (7<<16) 305 306#define CA91CX42_LSI_CTL_PGM_M (1<<14) 307#define CA91CX42_LSI_CTL_PGM_DATA 0 308#define CA91CX42_LSI_CTL_PGM_PGM (1<<14) 309 310#define CA91CX42_LSI_CTL_SUPER_M (1<<12) 311#define CA91CX42_LSI_CTL_SUPER_NPRIV 0 312#define CA91CX42_LSI_CTL_SUPER_SUPR (1<<12) 313 314#define CA91CX42_LSI_CTL_VCT_M (1<<8) 315#define CA91CX42_LSI_CTL_VCT_BLT (1<<8) 316#define CA91CX42_LSI_CTL_VCT_MBLT (1<<8) 317#define CA91CX42_LSI_CTL_LAS (1<<0) 318 319/* 320 * SCYC_CTL Register 321 * offset 178 322 */ 323#define CA91CX42_SCYC_CTL_LAS_PCIMEM 0 324#define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2) 325 326#define CA91CX42_SCYC_CTL_CYC_M (3<<0) 327#define CA91CX42_SCYC_CTL_CYC_RMW (1<<0) 328#define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1) 329 330/* 331 * LMISC Register 332 * offset 184 333 */ 334#define CA91CX42_BM_LMISC_CRT 0xF0000000 335#define CA91CX42_OF_LMISC_CRT 28 336#define CA91CX42_BM_LMISC_CWT 0x0F000000 337#define CA91CX42_OF_LMISC_CWT 24 338 339/* 340 * SLSI Register 341 * offset 188 342 */ 343#define CA91CX42_BM_SLSI_EN 0x80000000 344#define CA91CX42_BM_SLSI_PWEN 0x40000000 345#define CA91CX42_BM_SLSI_VDW 0x00F00000 346#define CA91CX42_OF_SLSI_VDW 20 347#define CA91CX42_BM_SLSI_PGM 0x0000F000 348#define CA91CX42_OF_SLSI_PGM 12 349#define CA91CX42_BM_SLSI_SUPER 0x00000F00 350#define CA91CX42_OF_SLSI_SUPER 8 351#define CA91CX42_BM_SLSI_BS 0x000000F6 352#define CA91CX42_OF_SLSI_BS 2 353#define CA91CX42_BM_SLSI_LAS 0x00000003 354#define CA91CX42_OF_SLSI_LAS 0 355#define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000 356 357/* 358 * DCTL Register 359 * offset 200 360 */ 361#define CA91CX42_DCTL_L2V (1<<31) 362#define CA91CX42_DCTL_VDW_M (3<<22) 363#define CA91CX42_DCTL_VDW_D8 0 364#define CA91CX42_DCTL_VDW_D16 (1<<22) 365#define CA91CX42_DCTL_VDW_D32 (1<<23) 366#define CA91CX42_DCTL_VDW_D64 (3<<22) 367 368#define CA91CX42_DCTL_VAS_M (7<<16) 369#define CA91CX42_DCTL_VAS_A16 0 370#define CA91CX42_DCTL_VAS_A24 (1<<16) 371#define CA91CX42_DCTL_VAS_A32 (1<<17) 372#define CA91CX42_DCTL_VAS_USER1 (3<<17) 373#define CA91CX42_DCTL_VAS_USER2 (7<<16) 374 375#define CA91CX42_DCTL_PGM_M (1<<14) 376#define CA91CX42_DCTL_PGM_DATA 0 377#define CA91CX42_DCTL_PGM_PGM (1<<14) 378 379#define CA91CX42_DCTL_SUPER_M (1<<12) 380#define CA91CX42_DCTL_SUPER_NPRIV 0 381#define CA91CX42_DCTL_SUPER_SUPR (1<<12) 382 383#define CA91CX42_DCTL_VCT_M (1<<8) 384#define CA91CX42_DCTL_VCT_BLT (1<<8) 385#define CA91CX42_DCTL_LD64EN (1<<7) 386 387/* 388 * DCPP Register 389 * offset 218 390 */ 391#define CA91CX42_DCPP_M 0xf 392#define CA91CX42_DCPP_NULL (1<<0) 393 394/* 395 * DMA General Control/Status Register (DGCS) 396 * offset 220 397 */ 398#define CA91CX42_DGCS_GO (1<<31) 399#define CA91CX42_DGCS_STOP_REQ (1<<30) 400#define CA91CX42_DGCS_HALT_REQ (1<<29) 401#define CA91CX42_DGCS_CHAIN (1<<27) 402 403#define CA91CX42_DGCS_VON_M (7<<20) 404 405#define CA91CX42_DGCS_VOFF_M (0xf<<16) 406 407#define CA91CX42_DGCS_ACT (1<<15) 408#define CA91CX42_DGCS_STOP (1<<14) 409#define CA91CX42_DGCS_HALT (1<<13) 410#define CA91CX42_DGCS_DONE (1<<11) 411#define CA91CX42_DGCS_LERR (1<<10) 412#define CA91CX42_DGCS_VERR (1<<9) 413#define CA91CX42_DGCS_PERR (1<<8) 414#define CA91CX42_DGCS_INT_STOP (1<<6) 415#define CA91CX42_DGCS_INT_HALT (1<<5) 416#define CA91CX42_DGCS_INT_DONE (1<<3) 417#define CA91CX42_DGCS_INT_LERR (1<<2) 418#define CA91CX42_DGCS_INT_VERR (1<<1) 419#define CA91CX42_DGCS_INT_PERR (1<<0) 420 421/* 422 * PCI Interrupt Enable Register 423 * offset 300 424 */ 425#define CA91CX42_LINT_LM3 0x00800000 426#define CA91CX42_LINT_LM2 0x00400000 427#define CA91CX42_LINT_LM1 0x00200000 428#define CA91CX42_LINT_LM0 0x00100000 429#define CA91CX42_LINT_MBOX3 0x00080000 430#define CA91CX42_LINT_MBOX2 0x00040000 431#define CA91CX42_LINT_MBOX1 0x00020000 432#define CA91CX42_LINT_MBOX0 0x00010000 433#define CA91CX42_LINT_ACFAIL 0x00008000 434#define CA91CX42_LINT_SYSFAIL 0x00004000 435#define CA91CX42_LINT_SW_INT 0x00002000 436#define CA91CX42_LINT_SW_IACK 0x00001000 437 438#define CA91CX42_LINT_VERR 0x00000400 439#define CA91CX42_LINT_LERR 0x00000200 440#define CA91CX42_LINT_DMA 0x00000100 441#define CA91CX42_LINT_VIRQ7 0x00000080 442#define CA91CX42_LINT_VIRQ6 0x00000040 443#define CA91CX42_LINT_VIRQ5 0x00000020 444#define CA91CX42_LINT_VIRQ4 0x00000010 445#define CA91CX42_LINT_VIRQ3 0x00000008 446#define CA91CX42_LINT_VIRQ2 0x00000004 447#define CA91CX42_LINT_VIRQ1 0x00000002 448#define CA91CX42_LINT_VOWN 0x00000001 449 450static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1, 451 CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3, 452 CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5, 453 CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 }; 454 455#define CA91CX42_LINT_MBOX 0x000F0000 456 457static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1, 458 CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 }; 459 460/* 461 * MAST_CTL Register 462 * offset 400 463 */ 464#define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000 465#define CA91CX42_OF_MAST_CTL_MAXRTRY 28 466#define CA91CX42_BM_MAST_CTL_PWON 0x0F000000 467#define CA91CX42_OF_MAST_CTL_PWON 24 468#define CA91CX42_BM_MAST_CTL_VRL 0x00C00000 469#define CA91CX42_OF_MAST_CTL_VRL 22 470#define CA91CX42_BM_MAST_CTL_VRM 0x00200000 471#define CA91CX42_BM_MAST_CTL_VREL 0x00100000 472#define CA91CX42_BM_MAST_CTL_VOWN 0x00080000 473#define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000 474#define CA91CX42_BM_MAST_CTL_PABS 0x00001000 475#define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F 476#define CA91CX42_OF_MAST_CTL_BUS_NO 0 477 478/* 479 * MISC_CTL Register 480 * offset 404 481 */ 482#define CA91CX42_MISC_CTL_VBTO 0xF0000000 483#define CA91CX42_MISC_CTL_VARB 0x04000000 484#define CA91CX42_MISC_CTL_VARBTO 0x03000000 485#define CA91CX42_MISC_CTL_SW_LRST 0x00800000 486#define CA91CX42_MISC_CTL_SW_SRST 0x00400000 487#define CA91CX42_MISC_CTL_BI 0x00100000 488#define CA91CX42_MISC_CTL_ENGBI 0x00080000 489#define CA91CX42_MISC_CTL_RESCIND 0x00040000 490#define CA91CX42_MISC_CTL_SYSCON 0x00020000 491#define CA91CX42_MISC_CTL_V64AUTO 0x00010000 492#define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF 493 494#define CA91CX42_OF_MISC_CTL_VARBTO 24 495#define CA91CX42_OF_MISC_CTL_VBTO 28 496 497/* 498 * MISC_STAT Register 499 * offset 408 500 */ 501#define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000 502#define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000 503#define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000 504#define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000 505#define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000 506#define CA91CX42_BM_MISC_STAT_TXFE 0x00040000 507#define CA91CX42_BM_MISC_STAT_RXFE 0x00020000 508#define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00 509#define CA91CX42_OF_MISC_STAT_DY4AUTOID 8 510 511/* 512 * VSI Control Register 513 * offset F00 514 */ 515#define CA91CX42_VSI_CTL_EN (1<<31) 516#define CA91CX42_VSI_CTL_PWEN (1<<30) 517#define CA91CX42_VSI_CTL_PREN (1<<29) 518 519#define CA91CX42_VSI_CTL_PGM_M (3<<22) 520#define CA91CX42_VSI_CTL_PGM_DATA (1<<22) 521#define CA91CX42_VSI_CTL_PGM_PGM (1<<23) 522 523#define CA91CX42_VSI_CTL_SUPER_M (3<<20) 524#define CA91CX42_VSI_CTL_SUPER_NPRIV (1<<20) 525#define CA91CX42_VSI_CTL_SUPER_SUPR (1<<21) 526 527#define CA91CX42_VSI_CTL_VAS_M (7<<16) 528#define CA91CX42_VSI_CTL_VAS_A16 0 529#define CA91CX42_VSI_CTL_VAS_A24 (1<<16) 530#define CA91CX42_VSI_CTL_VAS_A32 (1<<17) 531#define CA91CX42_VSI_CTL_VAS_USER1 (3<<17) 532#define CA91CX42_VSI_CTL_VAS_USER2 (7<<16) 533 534#define CA91CX42_VSI_CTL_LD64EN (1<<7) 535#define CA91CX42_VSI_CTL_LLRMW (1<<6) 536 537#define CA91CX42_VSI_CTL_LAS_M (3<<0) 538#define CA91CX42_VSI_CTL_LAS_PCI_MS 0 539#define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0) 540#define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1) 541 542/* LM_CTL Register 543 * offset F64 544 */ 545#define CA91CX42_LM_CTL_EN (1<<31) 546#define CA91CX42_LM_CTL_PGM (1<<23) 547#define CA91CX42_LM_CTL_DATA (1<<22) 548#define CA91CX42_LM_CTL_SUPR (1<<21) 549#define CA91CX42_LM_CTL_NPRIV (1<<20) 550#define CA91CX42_LM_CTL_AS_M (5<<16) 551#define CA91CX42_LM_CTL_AS_A16 0 552#define CA91CX42_LM_CTL_AS_A24 (1<<16) 553#define CA91CX42_LM_CTL_AS_A32 (1<<17) 554 555/* 556 * VRAI_CTL Register 557 * offset F70 558 */ 559#define CA91CX42_BM_VRAI_CTL_EN 0x80000000 560#define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000 561#define CA91CX42_OF_VRAI_CTL_PGM 22 562#define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000 563#define CA91CX42_OF_VRAI_CTL_SUPER 20 564#define CA91CX42_BM_VRAI_CTL_VAS 0x00030000 565#define CA91CX42_OF_VRAI_CTL_VAS 16 566 567/* VCSR_CTL Register 568 * offset F80 569 */ 570#define CA91CX42_VCSR_CTL_EN (1<<31) 571 572#define CA91CX42_VCSR_CTL_LAS_M (3<<0) 573#define CA91CX42_VCSR_CTL_LAS_PCI_MS 0 574#define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0) 575#define CA91CX42_VCSR_CTL_LAS_PCI_CONF (1<<1) 576 577/* VCSR_BS Register 578 * offset FFC 579 */ 580#define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27) 581 582#endif /* _CA91CX42_H */ 583