1/*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
19#define __LINUX_IRQCHIP_ARM_GIC_V3_H
20
21#include <asm/sysreg.h>
22
23/*
24 * Distributor registers. We assume we're running non-secure, with ARE
25 * being set. Secure-only and non-ARE registers are not described.
26 */
27#define GICD_CTLR			0x0000
28#define GICD_TYPER			0x0004
29#define GICD_IIDR			0x0008
30#define GICD_STATUSR			0x0010
31#define GICD_SETSPI_NSR			0x0040
32#define GICD_CLRSPI_NSR			0x0048
33#define GICD_SETSPI_SR			0x0050
34#define GICD_CLRSPI_SR			0x0058
35#define GICD_SEIR			0x0068
36#define GICD_ISENABLER			0x0100
37#define GICD_ICENABLER			0x0180
38#define GICD_ISPENDR			0x0200
39#define GICD_ICPENDR			0x0280
40#define GICD_ISACTIVER			0x0300
41#define GICD_ICACTIVER			0x0380
42#define GICD_IPRIORITYR			0x0400
43#define GICD_ICFGR			0x0C00
44#define GICD_IROUTER			0x6000
45#define GICD_PIDR2			0xFFE8
46
47#define GICD_CTLR_RWP			(1U << 31)
48#define GICD_CTLR_ARE_NS		(1U << 4)
49#define GICD_CTLR_ENABLE_G1A		(1U << 1)
50#define GICD_CTLR_ENABLE_G1		(1U << 0)
51
52#define GICD_IROUTER_SPI_MODE_ONE	(0U << 31)
53#define GICD_IROUTER_SPI_MODE_ANY	(1U << 31)
54
55#define GIC_PIDR2_ARCH_MASK		0xf0
56#define GIC_PIDR2_ARCH_GICv3		0x30
57#define GIC_PIDR2_ARCH_GICv4		0x40
58
59/*
60 * Re-Distributor registers, offsets from RD_base
61 */
62#define GICR_CTLR			GICD_CTLR
63#define GICR_IIDR			0x0004
64#define GICR_TYPER			0x0008
65#define GICR_STATUSR			GICD_STATUSR
66#define GICR_WAKER			0x0014
67#define GICR_SETLPIR			0x0040
68#define GICR_CLRLPIR			0x0048
69#define GICR_SEIR			GICD_SEIR
70#define GICR_PROPBASER			0x0070
71#define GICR_PENDBASER			0x0078
72#define GICR_INVLPIR			0x00A0
73#define GICR_INVALLR			0x00B0
74#define GICR_SYNCR			0x00C0
75#define GICR_MOVLPIR			0x0100
76#define GICR_MOVALLR			0x0110
77#define GICR_PIDR2			GICD_PIDR2
78
79#define GICR_WAKER_ProcessorSleep	(1U << 1)
80#define GICR_WAKER_ChildrenAsleep	(1U << 2)
81
82/*
83 * Re-Distributor registers, offsets from SGI_base
84 */
85#define GICR_ISENABLER0			GICD_ISENABLER
86#define GICR_ICENABLER0			GICD_ICENABLER
87#define GICR_ISPENDR0			GICD_ISPENDR
88#define GICR_ICPENDR0			GICD_ICPENDR
89#define GICR_ISACTIVER0			GICD_ISACTIVER
90#define GICR_ICACTIVER0			GICD_ICACTIVER
91#define GICR_IPRIORITYR0		GICD_IPRIORITYR
92#define GICR_ICFGR0			GICD_ICFGR
93
94#define GICR_TYPER_VLPIS		(1U << 1)
95#define GICR_TYPER_LAST			(1U << 4)
96
97/*
98 * CPU interface registers
99 */
100#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << 1)
101#define ICC_CTLR_EL1_EOImode_drop	(1U << 1)
102#define ICC_SRE_EL1_SRE			(1U << 0)
103
104/*
105 * Hypervisor interface registers (SRE only)
106 */
107#define ICH_LR_VIRTUAL_ID_MASK		((1UL << 32) - 1)
108
109#define ICH_LR_EOI			(1UL << 41)
110#define ICH_LR_GROUP			(1UL << 60)
111#define ICH_LR_STATE			(3UL << 62)
112#define ICH_LR_PENDING_BIT		(1UL << 62)
113#define ICH_LR_ACTIVE_BIT		(1UL << 63)
114
115#define ICH_MISR_EOI			(1 << 0)
116#define ICH_MISR_U			(1 << 1)
117
118#define ICH_HCR_EN			(1 << 0)
119#define ICH_HCR_UIE			(1 << 1)
120
121#define ICH_VMCR_CTLR_SHIFT		0
122#define ICH_VMCR_CTLR_MASK		(0x21f << ICH_VMCR_CTLR_SHIFT)
123#define ICH_VMCR_BPR1_SHIFT		18
124#define ICH_VMCR_BPR1_MASK		(7 << ICH_VMCR_BPR1_SHIFT)
125#define ICH_VMCR_BPR0_SHIFT		21
126#define ICH_VMCR_BPR0_MASK		(7 << ICH_VMCR_BPR0_SHIFT)
127#define ICH_VMCR_PMR_SHIFT		24
128#define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)
129
130#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
131#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
132#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
133#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
134#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
135#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
136#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)
137
138#define ICC_IAR1_EL1_SPURIOUS		0x3ff
139
140#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
141
142#define ICC_SRE_EL2_SRE			(1 << 0)
143#define ICC_SRE_EL2_ENABLE		(1 << 3)
144
145/*
146 * System register definitions
147 */
148#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
149#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
150#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
151#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
152#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
153#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
154#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)
155
156#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
157#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)
158
159#define ICH_LR0_EL2			__LR0_EL2(0)
160#define ICH_LR1_EL2			__LR0_EL2(1)
161#define ICH_LR2_EL2			__LR0_EL2(2)
162#define ICH_LR3_EL2			__LR0_EL2(3)
163#define ICH_LR4_EL2			__LR0_EL2(4)
164#define ICH_LR5_EL2			__LR0_EL2(5)
165#define ICH_LR6_EL2			__LR0_EL2(6)
166#define ICH_LR7_EL2			__LR0_EL2(7)
167#define ICH_LR8_EL2			__LR8_EL2(0)
168#define ICH_LR9_EL2			__LR8_EL2(1)
169#define ICH_LR10_EL2			__LR8_EL2(2)
170#define ICH_LR11_EL2			__LR8_EL2(3)
171#define ICH_LR12_EL2			__LR8_EL2(4)
172#define ICH_LR13_EL2			__LR8_EL2(5)
173#define ICH_LR14_EL2			__LR8_EL2(6)
174#define ICH_LR15_EL2			__LR8_EL2(7)
175
176#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
177#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
178#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
179#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
180#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)
181
182#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
183#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
184#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
185#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
186#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)
187
188#ifndef __ASSEMBLY__
189
190#include <linux/stringify.h>
191
192static inline void gic_write_eoir(u64 irq)
193{
194	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
195	isb();
196}
197
198#endif
199
200#endif
201