1/*
2 * max77693-private.h - Voltage regulator driver for the Maxim 77693
3 *
4 *  Copyright (C) 2012 Samsung Electrnoics
5 *  SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22 */
23
24#ifndef __LINUX_MFD_MAX77693_PRIV_H
25#define __LINUX_MFD_MAX77693_PRIV_H
26
27#include <linux/i2c.h>
28
29#define MAX77693_NUM_IRQ_MUIC_REGS	3
30#define MAX77693_REG_INVALID		(0xff)
31
32/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
33enum max77693_pmic_reg {
34	MAX77693_LED_REG_IFLASH1			= 0x00,
35	MAX77693_LED_REG_IFLASH2			= 0x01,
36	MAX77693_LED_REG_ITORCH				= 0x02,
37	MAX77693_LED_REG_ITORCHTIMER			= 0x03,
38	MAX77693_LED_REG_FLASH_TIMER			= 0x04,
39	MAX77693_LED_REG_FLASH_EN			= 0x05,
40	MAX77693_LED_REG_MAX_FLASH1			= 0x06,
41	MAX77693_LED_REG_MAX_FLASH2			= 0x07,
42	MAX77693_LED_REG_MAX_FLASH3			= 0x08,
43	MAX77693_LED_REG_MAX_FLASH4			= 0x09,
44	MAX77693_LED_REG_VOUT_CNTL			= 0x0A,
45	MAX77693_LED_REG_VOUT_FLASH1			= 0x0B,
46	MAX77693_LED_REG_VOUT_FLASH2			= 0x0C,
47	MAX77693_LED_REG_FLASH_INT			= 0x0E,
48	MAX77693_LED_REG_FLASH_INT_MASK			= 0x0F,
49	MAX77693_LED_REG_FLASH_STATUS			= 0x10,
50
51	MAX77693_PMIC_REG_PMIC_ID1			= 0x20,
52	MAX77693_PMIC_REG_PMIC_ID2			= 0x21,
53	MAX77693_PMIC_REG_INTSRC			= 0x22,
54	MAX77693_PMIC_REG_INTSRC_MASK			= 0x23,
55	MAX77693_PMIC_REG_TOPSYS_INT			= 0x24,
56	MAX77693_PMIC_REG_TOPSYS_INT_MASK		= 0x26,
57	MAX77693_PMIC_REG_TOPSYS_STAT			= 0x28,
58	MAX77693_PMIC_REG_MAINCTRL1			= 0x2A,
59	MAX77693_PMIC_REG_LSCNFG			= 0x2B,
60
61	MAX77693_CHG_REG_CHG_INT			= 0xB0,
62	MAX77693_CHG_REG_CHG_INT_MASK			= 0xB1,
63	MAX77693_CHG_REG_CHG_INT_OK			= 0xB2,
64	MAX77693_CHG_REG_CHG_DETAILS_00			= 0xB3,
65	MAX77693_CHG_REG_CHG_DETAILS_01			= 0xB4,
66	MAX77693_CHG_REG_CHG_DETAILS_02			= 0xB5,
67	MAX77693_CHG_REG_CHG_DETAILS_03			= 0xB6,
68	MAX77693_CHG_REG_CHG_CNFG_00			= 0xB7,
69	MAX77693_CHG_REG_CHG_CNFG_01			= 0xB8,
70	MAX77693_CHG_REG_CHG_CNFG_02			= 0xB9,
71	MAX77693_CHG_REG_CHG_CNFG_03			= 0xBA,
72	MAX77693_CHG_REG_CHG_CNFG_04			= 0xBB,
73	MAX77693_CHG_REG_CHG_CNFG_05			= 0xBC,
74	MAX77693_CHG_REG_CHG_CNFG_06			= 0xBD,
75	MAX77693_CHG_REG_CHG_CNFG_07			= 0xBE,
76	MAX77693_CHG_REG_CHG_CNFG_08			= 0xBF,
77	MAX77693_CHG_REG_CHG_CNFG_09			= 0xC0,
78	MAX77693_CHG_REG_CHG_CNFG_10			= 0xC1,
79	MAX77693_CHG_REG_CHG_CNFG_11			= 0xC2,
80	MAX77693_CHG_REG_CHG_CNFG_12			= 0xC3,
81	MAX77693_CHG_REG_CHG_CNFG_13			= 0xC4,
82	MAX77693_CHG_REG_CHG_CNFG_14			= 0xC5,
83	MAX77693_CHG_REG_SAFEOUT_CTRL			= 0xC6,
84
85	MAX77693_PMIC_REG_END,
86};
87
88/* MAX77693 ITORCH register */
89#define TORCH_IOUT1_SHIFT	0
90#define TORCH_IOUT2_SHIFT	4
91#define TORCH_IOUT_MIN		15625
92#define TORCH_IOUT_MAX		250000
93#define TORCH_IOUT_STEP		15625
94
95/* MAX77693 IFLASH1 and IFLASH2 registers */
96#define FLASH_IOUT_MIN		15625
97#define FLASH_IOUT_MAX_1LED	1000000
98#define FLASH_IOUT_MAX_2LEDS	625000
99#define FLASH_IOUT_STEP		15625
100
101/* MAX77693 TORCH_TIMER register */
102#define TORCH_TMR_NO_TIMER	0x40
103#define TORCH_TIMEOUT_MIN	262000
104#define TORCH_TIMEOUT_MAX	15728000
105
106/* MAX77693 FLASH_TIMER register */
107#define FLASH_TMR_LEVEL		0x80
108#define FLASH_TIMEOUT_MIN	62500
109#define FLASH_TIMEOUT_MAX	1000000
110#define FLASH_TIMEOUT_STEP	62500
111
112/* MAX77693 FLASH_EN register */
113#define FLASH_EN_OFF		0x0
114#define FLASH_EN_FLASH		0x1
115#define FLASH_EN_TORCH		0x2
116#define FLASH_EN_ON		0x3
117#define FLASH_EN_SHIFT(x)	(6 - ((x) - 1) * 2)
118#define TORCH_EN_SHIFT(x)	(2 - ((x) - 1) * 2)
119
120/* MAX77693 MAX_FLASH1 register */
121#define MAX_FLASH1_MAX_FL_EN	0x80
122#define MAX_FLASH1_VSYS_MIN	2400
123#define MAX_FLASH1_VSYS_MAX	3400
124#define MAX_FLASH1_VSYS_STEP	33
125
126/* MAX77693 VOUT_CNTL register */
127#define FLASH_BOOST_FIXED	0x04
128#define FLASH_BOOST_LEDNUM_2	0x80
129
130/* MAX77693 VOUT_FLASH1 register */
131#define FLASH_VOUT_MIN		3300
132#define FLASH_VOUT_MAX		5500
133#define FLASH_VOUT_STEP		25
134#define FLASH_VOUT_RMIN		0x0c
135
136/* MAX77693 FLASH_STATUS register */
137#define FLASH_STATUS_FLASH_ON	BIT(3)
138#define FLASH_STATUS_TORCH_ON	BIT(2)
139
140/* MAX77693 FLASH_INT register */
141#define FLASH_INT_FLED2_OPEN	BIT(0)
142#define FLASH_INT_FLED2_SHORT	BIT(1)
143#define FLASH_INT_FLED1_OPEN	BIT(2)
144#define FLASH_INT_FLED1_SHORT	BIT(3)
145#define FLASH_INT_OVER_CURRENT	BIT(4)
146
147/* MAX77693 CHG_CNFG_00 register */
148#define CHG_CNFG_00_CHG_MASK		0x1
149#define CHG_CNFG_00_BUCK_MASK		0x4
150
151/* MAX77693 CHG_CNFG_09 Register */
152#define CHG_CNFG_09_CHGIN_ILIM_MASK	0x7F
153
154/* MAX77693 CHG_CTRL Register */
155#define SAFEOUT_CTRL_SAFEOUT1_MASK	0x3
156#define SAFEOUT_CTRL_SAFEOUT2_MASK	0xC
157#define SAFEOUT_CTRL_ENSAFEOUT1_MASK	0x40
158#define SAFEOUT_CTRL_ENSAFEOUT2_MASK	0x80
159
160/* Slave addr = 0x4A: MUIC */
161enum max77693_muic_reg {
162	MAX77693_MUIC_REG_ID		= 0x00,
163	MAX77693_MUIC_REG_INT1		= 0x01,
164	MAX77693_MUIC_REG_INT2		= 0x02,
165	MAX77693_MUIC_REG_INT3		= 0x03,
166	MAX77693_MUIC_REG_STATUS1	= 0x04,
167	MAX77693_MUIC_REG_STATUS2	= 0x05,
168	MAX77693_MUIC_REG_STATUS3	= 0x06,
169	MAX77693_MUIC_REG_INTMASK1	= 0x07,
170	MAX77693_MUIC_REG_INTMASK2	= 0x08,
171	MAX77693_MUIC_REG_INTMASK3	= 0x09,
172	MAX77693_MUIC_REG_CDETCTRL1	= 0x0A,
173	MAX77693_MUIC_REG_CDETCTRL2	= 0x0B,
174	MAX77693_MUIC_REG_CTRL1		= 0x0C,
175	MAX77693_MUIC_REG_CTRL2		= 0x0D,
176	MAX77693_MUIC_REG_CTRL3		= 0x0E,
177
178	MAX77693_MUIC_REG_END,
179};
180
181/* MAX77693 INTMASK1~2 Register */
182#define INTMASK1_ADC1K_SHIFT		3
183#define INTMASK1_ADCERR_SHIFT		2
184#define INTMASK1_ADCLOW_SHIFT		1
185#define INTMASK1_ADC_SHIFT		0
186#define INTMASK1_ADC1K_MASK		(1 << INTMASK1_ADC1K_SHIFT)
187#define INTMASK1_ADCERR_MASK		(1 << INTMASK1_ADCERR_SHIFT)
188#define INTMASK1_ADCLOW_MASK		(1 << INTMASK1_ADCLOW_SHIFT)
189#define INTMASK1_ADC_MASK		(1 << INTMASK1_ADC_SHIFT)
190
191#define INTMASK2_VIDRM_SHIFT		5
192#define INTMASK2_VBVOLT_SHIFT		4
193#define INTMASK2_DXOVP_SHIFT		3
194#define INTMASK2_DCDTMR_SHIFT		2
195#define INTMASK2_CHGDETRUN_SHIFT	1
196#define INTMASK2_CHGTYP_SHIFT		0
197#define INTMASK2_VIDRM_MASK		(1 << INTMASK2_VIDRM_SHIFT)
198#define INTMASK2_VBVOLT_MASK		(1 << INTMASK2_VBVOLT_SHIFT)
199#define INTMASK2_DXOVP_MASK		(1 << INTMASK2_DXOVP_SHIFT)
200#define INTMASK2_DCDTMR_MASK		(1 << INTMASK2_DCDTMR_SHIFT)
201#define INTMASK2_CHGDETRUN_MASK		(1 << INTMASK2_CHGDETRUN_SHIFT)
202#define INTMASK2_CHGTYP_MASK		(1 << INTMASK2_CHGTYP_SHIFT)
203
204/* MAX77693 MUIC - STATUS1~3 Register */
205#define STATUS1_ADC_SHIFT		(0)
206#define STATUS1_ADCLOW_SHIFT		(5)
207#define STATUS1_ADCERR_SHIFT		(6)
208#define STATUS1_ADC1K_SHIFT		(7)
209#define STATUS1_ADC_MASK		(0x1f << STATUS1_ADC_SHIFT)
210#define STATUS1_ADCLOW_MASK		(0x1 << STATUS1_ADCLOW_SHIFT)
211#define STATUS1_ADCERR_MASK		(0x1 << STATUS1_ADCERR_SHIFT)
212#define STATUS1_ADC1K_MASK		(0x1 << STATUS1_ADC1K_SHIFT)
213
214#define STATUS2_CHGTYP_SHIFT		(0)
215#define STATUS2_CHGDETRUN_SHIFT		(3)
216#define STATUS2_DCDTMR_SHIFT		(4)
217#define STATUS2_DXOVP_SHIFT		(5)
218#define STATUS2_VBVOLT_SHIFT		(6)
219#define STATUS2_VIDRM_SHIFT		(7)
220#define STATUS2_CHGTYP_MASK		(0x7 << STATUS2_CHGTYP_SHIFT)
221#define STATUS2_CHGDETRUN_MASK		(0x1 << STATUS2_CHGDETRUN_SHIFT)
222#define STATUS2_DCDTMR_MASK		(0x1 << STATUS2_DCDTMR_SHIFT)
223#define STATUS2_DXOVP_MASK		(0x1 << STATUS2_DXOVP_SHIFT)
224#define STATUS2_VBVOLT_MASK		(0x1 << STATUS2_VBVOLT_SHIFT)
225#define STATUS2_VIDRM_MASK		(0x1 << STATUS2_VIDRM_SHIFT)
226
227#define STATUS3_OVP_SHIFT		(2)
228#define STATUS3_OVP_MASK		(0x1 << STATUS3_OVP_SHIFT)
229
230/* MAX77693 CDETCTRL1~2 register */
231#define CDETCTRL1_CHGDETEN_SHIFT	(0)
232#define CDETCTRL1_CHGTYPMAN_SHIFT	(1)
233#define CDETCTRL1_DCDEN_SHIFT		(2)
234#define CDETCTRL1_DCD2SCT_SHIFT		(3)
235#define CDETCTRL1_CDDELAY_SHIFT		(4)
236#define CDETCTRL1_DCDCPL_SHIFT		(5)
237#define CDETCTRL1_CDPDET_SHIFT		(7)
238#define CDETCTRL1_CHGDETEN_MASK		(0x1 << CDETCTRL1_CHGDETEN_SHIFT)
239#define CDETCTRL1_CHGTYPMAN_MASK	(0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
240#define CDETCTRL1_DCDEN_MASK		(0x1 << CDETCTRL1_DCDEN_SHIFT)
241#define CDETCTRL1_DCD2SCT_MASK		(0x1 << CDETCTRL1_DCD2SCT_SHIFT)
242#define CDETCTRL1_CDDELAY_MASK		(0x1 << CDETCTRL1_CDDELAY_SHIFT)
243#define CDETCTRL1_DCDCPL_MASK		(0x1 << CDETCTRL1_DCDCPL_SHIFT)
244#define CDETCTRL1_CDPDET_MASK		(0x1 << CDETCTRL1_CDPDET_SHIFT)
245
246#define CDETCTRL2_VIDRMEN_SHIFT		(1)
247#define CDETCTRL2_DXOVPEN_SHIFT		(3)
248#define CDETCTRL2_VIDRMEN_MASK		(0x1 << CDETCTRL2_VIDRMEN_SHIFT)
249#define CDETCTRL2_DXOVPEN_MASK		(0x1 << CDETCTRL2_DXOVPEN_SHIFT)
250
251/* MAX77693 MUIC - CONTROL1~3 register */
252#define COMN1SW_SHIFT			(0)
253#define COMP2SW_SHIFT			(3)
254#define COMN1SW_MASK			(0x7 << COMN1SW_SHIFT)
255#define COMP2SW_MASK			(0x7 << COMP2SW_SHIFT)
256#define COMP_SW_MASK			(COMP2SW_MASK | COMN1SW_MASK)
257#define CONTROL1_SW_USB			((1 << COMP2SW_SHIFT) \
258						| (1 << COMN1SW_SHIFT))
259#define CONTROL1_SW_AUDIO		((2 << COMP2SW_SHIFT) \
260						| (2 << COMN1SW_SHIFT))
261#define CONTROL1_SW_UART		((3 << COMP2SW_SHIFT) \
262						| (3 << COMN1SW_SHIFT))
263#define CONTROL1_SW_OPEN		((0 << COMP2SW_SHIFT) \
264						| (0 << COMN1SW_SHIFT))
265
266#define CONTROL2_LOWPWR_SHIFT		(0)
267#define CONTROL2_ADCEN_SHIFT		(1)
268#define CONTROL2_CPEN_SHIFT		(2)
269#define CONTROL2_SFOUTASRT_SHIFT	(3)
270#define CONTROL2_SFOUTORD_SHIFT		(4)
271#define CONTROL2_ACCDET_SHIFT		(5)
272#define CONTROL2_USBCPINT_SHIFT		(6)
273#define CONTROL2_RCPS_SHIFT		(7)
274#define CONTROL2_LOWPWR_MASK		(0x1 << CONTROL2_LOWPWR_SHIFT)
275#define CONTROL2_ADCEN_MASK		(0x1 << CONTROL2_ADCEN_SHIFT)
276#define CONTROL2_CPEN_MASK		(0x1 << CONTROL2_CPEN_SHIFT)
277#define CONTROL2_SFOUTASRT_MASK		(0x1 << CONTROL2_SFOUTASRT_SHIFT)
278#define CONTROL2_SFOUTORD_MASK		(0x1 << CONTROL2_SFOUTORD_SHIFT)
279#define CONTROL2_ACCDET_MASK		(0x1 << CONTROL2_ACCDET_SHIFT)
280#define CONTROL2_USBCPINT_MASK		(0x1 << CONTROL2_USBCPINT_SHIFT)
281#define CONTROL2_RCPS_MASK		(0x1 << CONTROL2_RCPS_SHIFT)
282
283#define CONTROL3_JIGSET_SHIFT		(0)
284#define CONTROL3_BTLDSET_SHIFT		(2)
285#define CONTROL3_ADCDBSET_SHIFT		(4)
286#define CONTROL3_JIGSET_MASK		(0x3 << CONTROL3_JIGSET_SHIFT)
287#define CONTROL3_BTLDSET_MASK		(0x3 << CONTROL3_BTLDSET_SHIFT)
288#define CONTROL3_ADCDBSET_MASK		(0x3 << CONTROL3_ADCDBSET_SHIFT)
289
290/* Slave addr = 0x90: Haptic */
291enum max77693_haptic_reg {
292	MAX77693_HAPTIC_REG_STATUS		= 0x00,
293	MAX77693_HAPTIC_REG_CONFIG1		= 0x01,
294	MAX77693_HAPTIC_REG_CONFIG2		= 0x02,
295	MAX77693_HAPTIC_REG_CONFIG_CHNL		= 0x03,
296	MAX77693_HAPTIC_REG_CONFG_CYC1		= 0x04,
297	MAX77693_HAPTIC_REG_CONFG_CYC2		= 0x05,
298	MAX77693_HAPTIC_REG_CONFIG_PER1		= 0x06,
299	MAX77693_HAPTIC_REG_CONFIG_PER2		= 0x07,
300	MAX77693_HAPTIC_REG_CONFIG_PER3		= 0x08,
301	MAX77693_HAPTIC_REG_CONFIG_PER4		= 0x09,
302	MAX77693_HAPTIC_REG_CONFIG_DUTY1	= 0x0A,
303	MAX77693_HAPTIC_REG_CONFIG_DUTY2	= 0x0B,
304	MAX77693_HAPTIC_REG_CONFIG_PWM1		= 0x0C,
305	MAX77693_HAPTIC_REG_CONFIG_PWM2		= 0x0D,
306	MAX77693_HAPTIC_REG_CONFIG_PWM3		= 0x0E,
307	MAX77693_HAPTIC_REG_CONFIG_PWM4		= 0x0F,
308	MAX77693_HAPTIC_REG_REV			= 0x10,
309
310	MAX77693_HAPTIC_REG_END,
311};
312
313/* max77693-pmic LSCNFG configuraton register */
314#define MAX77693_PMIC_LOW_SYS_MASK      0x80
315#define MAX77693_PMIC_LOW_SYS_SHIFT     7
316
317/* max77693-haptic configuration register */
318#define MAX77693_CONFIG2_MODE           7
319#define MAX77693_CONFIG2_MEN            6
320#define MAX77693_CONFIG2_HTYP           5
321
322enum max77693_irq_source {
323	LED_INT = 0,
324	TOPSYS_INT,
325	CHG_INT,
326	MUIC_INT1,
327	MUIC_INT2,
328	MUIC_INT3,
329
330	MAX77693_IRQ_GROUP_NR,
331};
332
333#define SRC_IRQ_CHARGER			BIT(0)
334#define SRC_IRQ_TOP			BIT(1)
335#define SRC_IRQ_FLASH			BIT(2)
336#define SRC_IRQ_MUIC			BIT(3)
337#define SRC_IRQ_ALL			(SRC_IRQ_CHARGER | SRC_IRQ_TOP \
338						| SRC_IRQ_FLASH | SRC_IRQ_MUIC)
339
340#define LED_IRQ_FLED2_OPEN		BIT(0)
341#define LED_IRQ_FLED2_SHORT		BIT(1)
342#define LED_IRQ_FLED1_OPEN		BIT(2)
343#define LED_IRQ_FLED1_SHORT		BIT(3)
344#define LED_IRQ_MAX_FLASH		BIT(4)
345
346#define TOPSYS_IRQ_T120C_INT		BIT(0)
347#define TOPSYS_IRQ_T140C_INT		BIT(1)
348#define TOPSYS_IRQ_LOWSYS_INT		BIT(3)
349
350#define CHG_IRQ_BYP_I			BIT(0)
351#define CHG_IRQ_THM_I			BIT(2)
352#define CHG_IRQ_BAT_I			BIT(3)
353#define CHG_IRQ_CHG_I			BIT(4)
354#define CHG_IRQ_CHGIN_I			BIT(6)
355
356#define MUIC_IRQ_INT1_ADC		BIT(0)
357#define MUIC_IRQ_INT1_ADC_LOW		BIT(1)
358#define MUIC_IRQ_INT1_ADC_ERR		BIT(2)
359#define MUIC_IRQ_INT1_ADC1K		BIT(3)
360
361#define MUIC_IRQ_INT2_CHGTYP		BIT(0)
362#define MUIC_IRQ_INT2_CHGDETREUN	BIT(1)
363#define MUIC_IRQ_INT2_DCDTMR		BIT(2)
364#define MUIC_IRQ_INT2_DXOVP		BIT(3)
365#define MUIC_IRQ_INT2_VBVOLT		BIT(4)
366#define MUIC_IRQ_INT2_VIDRM		BIT(5)
367
368#define MUIC_IRQ_INT3_EOC		BIT(0)
369#define MUIC_IRQ_INT3_CGMBC		BIT(1)
370#define MUIC_IRQ_INT3_OVP		BIT(2)
371#define MUIC_IRQ_INT3_MBCCHG_ERR	BIT(3)
372#define MUIC_IRQ_INT3_CHG_ENABLED	BIT(4)
373#define MUIC_IRQ_INT3_BAT_DET		BIT(5)
374
375enum max77693_irq {
376	/* PMIC - FLASH */
377	MAX77693_LED_IRQ_FLED2_OPEN,
378	MAX77693_LED_IRQ_FLED2_SHORT,
379	MAX77693_LED_IRQ_FLED1_OPEN,
380	MAX77693_LED_IRQ_FLED1_SHORT,
381	MAX77693_LED_IRQ_MAX_FLASH,
382
383	/* PMIC - TOPSYS */
384	MAX77693_TOPSYS_IRQ_T120C_INT,
385	MAX77693_TOPSYS_IRQ_T140C_INT,
386	MAX77693_TOPSYS_IRQ_LOWSYS_INT,
387
388	/* PMIC - Charger */
389	MAX77693_CHG_IRQ_BYP_I,
390	MAX77693_CHG_IRQ_THM_I,
391	MAX77693_CHG_IRQ_BAT_I,
392	MAX77693_CHG_IRQ_CHG_I,
393	MAX77693_CHG_IRQ_CHGIN_I,
394
395	MAX77693_IRQ_NR,
396};
397
398enum max77693_irq_muic {
399	/* MUIC INT1 */
400	MAX77693_MUIC_IRQ_INT1_ADC,
401	MAX77693_MUIC_IRQ_INT1_ADC_LOW,
402	MAX77693_MUIC_IRQ_INT1_ADC_ERR,
403	MAX77693_MUIC_IRQ_INT1_ADC1K,
404
405	/* MUIC INT2 */
406	MAX77693_MUIC_IRQ_INT2_CHGTYP,
407	MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
408	MAX77693_MUIC_IRQ_INT2_DCDTMR,
409	MAX77693_MUIC_IRQ_INT2_DXOVP,
410	MAX77693_MUIC_IRQ_INT2_VBVOLT,
411	MAX77693_MUIC_IRQ_INT2_VIDRM,
412
413	/* MUIC INT3 */
414	MAX77693_MUIC_IRQ_INT3_EOC,
415	MAX77693_MUIC_IRQ_INT3_CGMBC,
416	MAX77693_MUIC_IRQ_INT3_OVP,
417	MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
418	MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
419	MAX77693_MUIC_IRQ_INT3_BAT_DET,
420
421	MAX77693_MUIC_IRQ_NR,
422};
423
424struct max77693_dev {
425	struct device *dev;
426	struct i2c_client *i2c;		/* 0xCC , PMIC, Charger, Flash LED */
427	struct i2c_client *muic;	/* 0x4A , MUIC */
428	struct i2c_client *haptic;	/* 0x90 , Haptic */
429
430	int type;
431
432	struct regmap *regmap;
433	struct regmap *regmap_muic;
434	struct regmap *regmap_haptic;
435
436	struct regmap_irq_chip_data *irq_data_led;
437	struct regmap_irq_chip_data *irq_data_topsys;
438	struct regmap_irq_chip_data *irq_data_charger;
439	struct regmap_irq_chip_data *irq_data_muic;
440
441	int irq;
442	int irq_gpio;
443	struct mutex irqlock;
444	int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
445	int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
446};
447
448enum max77693_types {
449	TYPE_MAX77693,
450};
451
452extern int max77693_irq_init(struct max77693_dev *max77686);
453extern void max77693_irq_exit(struct max77693_dev *max77686);
454extern int max77693_irq_resume(struct max77693_dev *max77686);
455
456#endif /*  __LINUX_MFD_MAX77693_PRIV_H */
457