| bda3a47c886664e86ee14eb79e9072b9e341f575 |
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17-Jan-2012 |
Nikolaus Voss <n.voss@weinmann.de> |
at_hdmac: bugfix for enabling channel irq
commit 463894705e4089d0ff69e7d877312d496ac70e5b deleted redundant
chan_id and chancnt initialization in dma drivers as this is done
in dma_async_device_register().
However, atc_enable_irq() relied on chan_id set before registering
the device, what left only channel 0 functional for this driver.
This patch introduces atc_enable/disable_chan_irq() as a variant
of atc_enable/disable_irq() with the channel as explicit argument.
Signed-off-by: Nikolaus Voss <n.voss@weinmann.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/at_hdmac_regs.h
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| 02f88be9488a3d831f073c1161b1e5feacb9d3ec |
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22-Nov-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: simplify device selection from platform data or DT
Using a configuration structure simplify the finding of SoC
dependent parameters. Both platform data and device tree ids are
using these structures.
This will separate data from code and remove the need for an enum.
Idea from Grant Likely.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/at_hdmac_regs.h
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| 67348450b86cb1b42aa4dd55cf7cde19c2e53461 |
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17-Oct-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: platform data move to use .id_table
We remove the use of platform data from DMA controller driver.
We now use of .id_table to distinguish between compatible
types. The two implementations allow to determine the
number of channels and the capabilities of the controller.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/at_hdmac_regs.h
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| 3c477482bb9f976e5451c50be7d3d60ea6f88646 |
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25-Jul-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: add wrappers for testing channel state
Cyclic property and paused state are encoded as bits in the channel status
bitfield. Tests of those bits are wrapped in convenient helper functions.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/at_hdmac_regs.h
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| c0ba5947370a0900b1823922fc4faf41515bc901 |
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27-Jul-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: improve power management routines
Save/restore dma controller state across a suspend-resume sequence.
The prepare() function will wait for the non-cyclic channels to become idle.
It also deals with cyclic operations with the start at next period while
resuming.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/at_hdmac_regs.h
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| 23b5e3ad68a3c26a6a36039ea907997664aedcab |
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06-May-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: implement pause and resume in atc_control
Pause and resume controls are useful for audio devices. This also returns
correct status from atc_tx_status() in case chan is paused.
Idea from dw_dmac patch by Linus Walleij.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/at_hdmac_regs.h
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| ae14d4b5e0a4ebc4e674831cbb97b73ba66dba08 |
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30-Apr-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: specialize AHB interfaces to optimize transfers
DMA controller has two AHB interfaces on the SOC internal
matrix.
It is more efficient to specialize each interface as the
access to memory can introduce latencies that are not compatible
with peripheral accesses requirements.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/at_hdmac_regs.h
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| 53830cc75974a199b6b654c062ff8c54c58caa0b |
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30-Apr-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: add cyclic DMA operation support
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/at_hdmac_regs.h
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| 9b3aa589eaa1366200062ce1f9cc7ddca8d1d578 |
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30-Apr-2011 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: modify way to use interrupts
Now we use Buffer Transfer Completed interrupts. If we
want a chained buffer completed information, we setup the
ATC_IEN bit in CTRLB register in the lli.
This is done by set_desc_eol() function and used by
memcpy/slave_sg functions.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/at_hdmac_regs.h
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| 285a3c71640ad7101b7237b8fbaa4ead22c6551c |
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09-Sep-2009 |
Dan Williams <dan.j.williams@intel.com> |
at_hdmac: implement a private tx_list
Drop at_hdmac's use of tx_list from struct dma_async_tx_descriptor in
preparation for removal of this field.
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/at_hdmac_regs.h
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| 808347f6a31792079e345ec865e9cfcb6e8ae6b2 |
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22-Jul-2009 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: add DMA slave transfers
This patch for at_hdmac adds the slave transfers capability to the Atmel DMA
controller available on some AT91 SOCs. This allow peripheral to memory and
memory to peripheral transfers with hardware handshaking.
Slave structure for controller specific information is passed through channel
private data. This at_dma_slave structure is defined in at_hdmac.h header file
and relative hardware definition are moved to this file from at_hdmac_regs.h.
Doing this we allow the channel configuration from platform definition code.
This work is intensively based on dw_dmac and several slave implementations.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/at_hdmac_regs.h
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| dc78baa2b90b289590911b40b6800f77d0dc935a |
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03-Jul-2009 |
Nicolas Ferre <nicolas.ferre@atmel.com> |
dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller
This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on
at91sam9rl chip. It will be used on other products in the future.
This first release covers only the memory-to-memory tranfer type. This is the
only tranfer type supported by this chip. On other products, it will be used
also for peripheral DMA transfer (slave API support to come).
I used dmatest client without problem in different configurations to test it.
Full documentation for this controller can be found in the SAM9RL datasheet:
http://www.atmel.com/dyn/products/product_card.asp?part_id=4243
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/at_hdmac_regs.h
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