| 5c0422878fcdc279ae9a8e8b66972a15b5efb67f |
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18-Oct-2011 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: ILK + VT-d workaround
Idle the GPU before doing any unmaps. We know if VT-d is in use through
an exported variable from iommu code.
This should avoid a known HW issue.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| e4ffd173a1c2f96b43127c2537dd99d89e759bba |
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04-Apr-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Add an interface to dynamically change the cache level
[anholt v2: Don't forget that when going from cached to uncached, we
haven't been tracking the write domain from the CPU perspective, since
we haven't needed it for GPU coherency.]
[ickle v3: We also need to make sure we relinquish any fences on older
chipsets and clear the GTT for sane domain tracking.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| d5bd144959e639443f387c34989cec7c9efff091 |
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14-Apr-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/gtt: Split out i915_gem_gtt_rebind_object()
... in preparation for changing the cache level (and thus the flags upon
the PTEs) dynamically.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| 93dfb40cd887c4f39e38f047c4d9ea0b7188a58a |
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30-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Rename agp_type to cache_level
... to clarify just how we use it inside the driver and remove the
confusion of the poorly matching agp_type names. We still need to
translate through agp_type for interface into the fake AGP driver.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| bee4a186c16bed0d7e91425ca9356c2e8c015f8d |
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21-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915,agp/intel: Do not clear stolen entries
We can only utilize the stolen portion of the GTT if we are in sole
charge of the hardware. This is only true if using GEM and KMS,
otherwise VESA continues to access stolen memory.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Reported-by: Frederic Weisbecker <fweisbec@gmail.com>
Tested-by: Jiri Olsa <jolsa@redhat.com>
Tested-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| d9126400580e2caada85fa68799952956a6062fd |
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11-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/gtt: Unmap the PCI pages after unbinding them from the GTT
Dave Airlie spotted that his ILK laptop with DMAR enabled was generating
the occasional DMAR warning.
"The ordering in the previous code was to rewrite the GTT table before
unmapping the pages and that makes sense to me."
This is his stable patch ported to d-i-n.
Reported-by: Dave Airlie <airlied@redhat.com>
Original-patch-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| a8e93126a6f10d0a14ba8407ec112b1b3a5e2e97 |
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08-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/gtt: Clear the cachelines upon resume
Required for my pineview system to not barf after resuming.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| 05394f3975dceb107a5e1393e2244946e5b43660 |
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08-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use drm_i915_gem_object as the preferred type
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and
many characters!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| 185cbcb304ba4dee55e39593fd86dcd7813f62ec |
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06-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: no more agp for gem
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| 7c2e6fdf452cddeff6a8ee5156edba39e53246fc |
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06-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: move gtt handling to i915_gem_gtt.c
No more drm_*_agp in i915_gem.c!
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_gem_gtt.c
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| 76aaf22016caa7764f40e792aaca7b4918312b22 |
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05-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: restore gtt on resume in the drm instead of in intel-gtt.ko
This still uses the agp functions to actually reinstate the mappings
(with a gross hack to make agp cooperate), but it wires everything
up correctly for the switchover.
The call to agp_rebind_memory can be dropped because all non-kms drivers
do all their rebinding on EnterVT.
v2: Be more paranoid and flush the chipset cache after restoring gtt
mappings.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_gem_gtt.c
|