Lines Matching refs:pModal
306 struct modal_eep_4k_header *pModal = &eep->modalHeader;
314 return pModal->noiseFloorThreshCh[0];
330 return pModal->ob_0;
332 return pModal->db1_1;
344 return pModal->version;
346 return pModal->antdiv_ctl1;
350 return pModal->antennaGainCh[0];
657 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
666 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
760 struct modal_eep_4k_header *pModal,
765 pModal->antCtrlChain[0]);
771 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
772 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
776 txRxAttenLocal = pModal->txRxAttenCh[0];
779 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
781 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
784 pModal->xatten2Margin[0]);
786 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
791 pModal->bswMargin[0]);
793 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
796 pModal->xatten2Margin[0]);
799 pModal->xatten2Db[0]);
805 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
810 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
820 struct modal_eep_4k_header *pModal;
829 pModal = &eep->modalHeader;
832 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
835 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
838 if (pModal->version >= 3) {
839 ant_div_control1 = pModal->antdiv_ctl1;
840 ant_div_control2 = pModal->antdiv_ctl2;
868 if (pModal->version >= 2) {
869 ob[0] = pModal->ob_0;
870 ob[1] = pModal->ob_1;
871 ob[2] = pModal->ob_2;
872 ob[3] = pModal->ob_3;
873 ob[4] = pModal->ob_4;
875 db1[0] = pModal->db1_0;
876 db1[1] = pModal->db1_1;
877 db1[2] = pModal->db1_2;
878 db1[3] = pModal->db1_3;
879 db1[4] = pModal->db1_4;
881 db2[0] = pModal->db2_0;
882 db2[1] = pModal->db2_1;
883 db2[2] = pModal->db2_2;
884 db2[3] = pModal->db2_3;
885 db2[4] = pModal->db2_4;
886 } else if (pModal->version == 1) {
887 ob[0] = pModal->ob_0;
888 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
889 db1[0] = pModal->db1_0;
890 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
891 db2[0] = pModal->db2_0;
892 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
897 ob[i] = pModal->ob_0;
898 db1[i] = pModal->db1_0;
899 db2[i] = pModal->db1_0;
1010 pModal->switchSettling);
1012 pModal->adcDesiredSize);
1015 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1016 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1017 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1018 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1021 pModal->txEndToRxOn);
1025 pModal->txEndToRxOn);
1027 pModal->thresh62);
1029 pModal->thresh62);
1034 pModal->txFrameToDataStart);
1036 pModal->txFrameToPaOn);
1044 pModal->swSettleHt40);
1047 bb_desired_scale = (pModal->bb_scale_smrt_antenna &