/drivers/scsi/ |
H A D | vmw_pvscsi.h | 33 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro 341 #define PVSCSI_INTR_CMPL_MASK MASK(2) 345 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2) 347 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
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H A D | vmw_pvscsi.c | 596 MASK(cmp_entries)); 646 e = adapter->req_ring + (s->reqProdIdx & MASK(req_entries)); 993 MASK(msg_entries));
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/drivers/gpu/drm/nouveau/ |
H A D | nv04_cursor.c | 46 MASK(NV_CIO_CRE_HCUR_ASI) | 52 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
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H A D | nouveau_hw.h | 29 #define MASK(field) ( \ macro 33 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield)) 445 *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); 447 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
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H A D | nv04_display.c | 60 MASK(NV_CIO_CRE_LCD_LCD_SELECT)); 66 MASK(NV_CIO_CRE_LCD_LCD_SELECT));
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H A D | nv04_crtc.c | 354 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 384 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 705 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
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H A D | nv04_dac.c | 153 saved_pi & ~(0x80 | MASK(NV_CIO_CRE_PIXEL_FORMAT)));
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/drivers/scsi/sym53c8xx_2/ |
H A D | sym_fw2.h | 241 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 329 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)), 361 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 451 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 475 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), 534 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), 694 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 911 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 917 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 1086 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_I [all...] |
H A D | sym_fw1.h | 249 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 376 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 466 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 491 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), 551 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), 717 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 962 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 968 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 1200 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1220 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_I [all...] |
/drivers/dma/ |
H A D | dw_dmac.c | 194 channel_set_bit(dw, MASK.XFER, dwc->mask); 195 channel_set_bit(dw, MASK.BLOCK, dwc->mask); 196 channel_set_bit(dw, MASK.ERROR, dwc->mask); 568 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); 569 channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask); 570 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); 585 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 586 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 587 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 596 channel_clear_bit(dw, MASK [all...] |
H A D | dw_dmac_regs.h | 54 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ member in struct:dw_dma_regs
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/drivers/staging/omapdrm/ |
H A D | omap_dmm_tiler.h | 63 #define MASK(bits) ((1 << (bits)) - 1) macro
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H A D | omap_dmm_tiler.c | 412 x_mask = MASK(x_bits); 413 y_mask = MASK(y_bits);
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/drivers/staging/xgifb/ |
H A D | vb_struct.h | 131 unsigned short MASK; member in struct:XGI_LCDDataTablStruct 184 unsigned short MASK; member in struct:XGI330_LCDDataTablStruct 190 unsigned short MASK; member in struct:XGI330_TVDataTablStruct
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/drivers/char/xilinx_hwicap/ |
H A D | xilinx_hwicap.h | 123 u32 MASK; member in struct:config_registers
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H A D | xilinx_hwicap.c | 129 .MASK = 6, 154 .MASK = 6, 178 .MASK = 6,
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/drivers/scsi/aic7xxx/aicasm/ |
H A D | aicasm_symbol.h | 59 MASK, enumerator in enum:__anon4015
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H A D | aicasm_symbol.c | 105 case MASK: 247 case MASK: 505 case MASK: 632 case MASK:
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H A D | aicasm_gram.y | 532 process_field(MASK, $2, $3.value); 711 case MASK: 1440 if (field_type != MASK && value == 0) { 1514 case MASK: 1899 if ((node->symbol->type == MASK
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/drivers/gpio/ |
H A D | gpio-ab8500.c | 72 MASK, enumerator in enum:ab8500_gpio_action 297 case MASK: 322 ab8500_gpio->irq_action = MASK;
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/drivers/mfd/ |
H A D | asic3.c | 542 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); 543 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); 544 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); 545 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
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/drivers/platform/x86/ |
H A D | compal-laptop.c | 381 #define SIMPLE_MASKED_STORE_SHOW(NAME, ADDR, MASK) \ 385 return sprintf(buf, "%d\n", ((ec_read_u8(ADDR) & MASK) != 0)); \ 394 ec_write(ADDR, state ? (old_val | MASK) : (old_val & ~MASK)); \
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/drivers/staging/keucr/ |
H A D | smil.h | 139 #define MASK 0x00 /* .00. .... NAND MASK ROM Model */ macro
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/drivers/net/ethernet/qlogic/netxen/ |
H A D | netxen_nic_hw.c | 32 #define MASK(n) ((1ULL<<(n))-1) macro 37 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 1156 (off & MASK(16));
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/drivers/net/ethernet/qlogic/qlcnic/ |
H A D | qlcnic_hw.c | 14 #define MASK(n) ((1ULL<<(n))-1) macro 17 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 891 *addr = adapter->ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
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