Searched refs:NCR5380_read (Results 1 - 20 of 20) sorted by relevance

/drivers/scsi/
H A Dmac_scsi.c344 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
352 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
449 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
450 && !(NCR5380_read(STATUS_REG) & SR_REQ))
452 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
453 && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {
541 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
542 && (!(NCR5380_read(STATUS_REG) & SR_REQ)
543 || (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)))
545 if (!(NCR5380_read(BUS_AND_STATUS_RE
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H A Dmac_scsi.h65 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro
H A DNCR5380.c250 * NCR5380_read(register) - read from the specified register
336 r = NCR5380_read(reg);
345 r = NCR5380_read(reg);
424 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
425 status = NCR5380_read(STATUS_REG);
426 mr = NCR5380_read(MODE_REG);
427 icr = NCR5380_read(INITIATOR_COMMAND_REG);
428 basr = NCR5380_read(BUS_AND_STATUS_REG);
466 status = NCR5380_read(STATUS_REG);
905 for (pass = 1; (NCR5380_read(STATUS_RE
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H A Dsun3_NCR5380.c209 * NCR5380_read(register) - read from the specified register
519 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
520 status = NCR5380_read(STATUS_REG);
521 mr = NCR5380_read(MODE_REG);
522 icr = NCR5380_read(INITIATOR_COMMAND_REG);
523 basr = NCR5380_read(BUS_AND_STATUS_REG);
565 status = NCR5380_read(STATUS_REG);
1161 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG),
1162 NCR5380_read(STATUS_REG));
1172 if((NCR5380_read(BUS_AND_STATUS_RE
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H A Ddtc.h73 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
76 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
H A Dg_NCR5380.c585 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) {
588 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) {
592 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY);
598 dst[start + i] = NCR5380_read(C400_HOST_BUFFER);
609 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)
618 dst[start + i] = NCR5380_read(C400_HOST_BUFFER);
628 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ))
636 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG)
639 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER))
643 NCR5380_read(RESET_PARITY_INTERRUPT_RE
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H A Datari_NCR5380.c222 * NCR5380_read(register) - read from the specified register
571 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
572 status = NCR5380_read(STATUS_REG);
573 mr = NCR5380_read(MODE_REG);
574 icr = NCR5380_read(INITIATOR_COMMAND_REG);
575 basr = NCR5380_read(BUS_AND_STATUS_REG);
618 status = NCR5380_read(STATUS_REG);
1227 if ((NCR5380_read(BUS_AND_STATUS_REG) &
1230 saved_data = NCR5380_read(INPUT_DATA_REG);
1238 HOSTNO, NCR5380_read(BUS_AND_STATUS_RE
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H A Ddtc.c370 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
380 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
391 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))
395 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
420 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
431 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
439 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))
443 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT))
H A Dg_NCR5380.h81 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro
106 #define NCR5380_read(reg) readb(iomem + NCR53C400_mem_base + (reg)) macro
H A Dpas16.h146 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro
149 #define NCR5380_read(reg) \ macro
H A Dt128.h124 #define NCR5380_read(reg) readb(T128_address(reg)) macro
127 #define NCR5380_read(reg) \ macro
H A Dsun3_scsi.c349 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
359 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
579 if(count && (NCR5380_read(BUS_AND_STATUS_REG) &
582 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG));
H A Dpas16.c254 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
331 if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */
334 if( NCR5380_read( MODE_REG ) != 0x00 )
H A Ddmx3191d.c38 #define NCR5380_read(reg) inb(port + reg) macro
H A Datari_scsi.h49 #define NCR5380_read(reg) atari_scsi_reg_read( reg ) macro
H A Dsun3_scsi_vme.c318 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
328 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
H A Dsun3_scsi.h96 #define NCR5380_read(reg) sun3scsi_read(reg) macro
H A Datari_scsi.c836 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG)));
844 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
1063 * methods are quite different. The calling macros NCR5380_read and
/drivers/scsi/arm/
H A Doak.c30 #define NCR5380_read(reg) readb(_base + ((reg) << 2)) macro
H A Dcumana_1.c30 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro

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