Searched refs:PAR (Results 1 - 8 of 8) sorted by relevance

/drivers/net/wireless/
H A Dadm8211.c1093 reg = ADM8211_CSR_READ(PAR);
1113 ADM8211_CSR_WRITE(PAR, reg);
1219 tmp = ADM8211_CSR_READ(PAR);
1220 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1222 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1228 ADM8211_CSR_WRITE(PAR, tmp);
H A Dadm8211.h15 __le32 PAR; /* 0x00 CSR0 */ member in struct:adm8211_csr
85 /* CSR0 - PAR (PCI Address Register) */
/drivers/scsi/sym53c8xx_2/
H A Dsym_defs.h268 #define PAR 0x01 /* sta: scsi parity error */ macro
H A Dsym_hipd.c1865 OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
2302 * The chip will then interrupt with both PAR and MA
2768 * - SCSI parity error + Phase mismatch (PAR|MA)
2772 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
2775 * - Some combinations of STO, PAR, UDC, ...
2849 * PAR and MA interrupts may occur at the same time,
2897 * A SCSI parity error (PAR) may be combined with a phase
2906 if (sist & PAR) sym_int_par (np, sist);
/drivers/scsi/
H A Dncr53c8xx.h794 #define PAR 0x01 /* sta: scsi parity error */ macro
H A Dncr53c8xx.c5316 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
5954 ** We try to deal with PAR and SBMC combined with
5963 if ((sist & PAR) && ncr_int_par (np))
5976 if (!(sist & (SBMC|PAR)) && !(dstat & SSI)) {
/drivers/net/ethernet/via/
H A Dvia-velocity.c1352 writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
2787 dev->dev_addr[i] = readb(&regs->PAR[i]);
H A Dvia-velocity.h978 volatile u8 PAR[6]; /* 0x00 */ member in struct:mac_regs

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