Searched refs:RADEON_MM_INDEX (Results 1 - 6 of 6) sorted by relevance

/drivers/gpu/drm/radeon/
H A Dradeon_cursor.c69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
72 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
77 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
80 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
95 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
99 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
105 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
108 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
H A Dradeon_drv.h486 #define RADEON_MM_INDEX 0x0000 macro
1857 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
H A Dr100.c4108 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4118 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4128 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4138 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
H A Dradeon_cp.c128 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
H A Dradeon_combios.c3168 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3171 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
H A Dradeon_reg.h1225 #define RADEON_MM_INDEX 0x0000 macro

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