1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/seq_file.h> 29#include <linux/slab.h> 30#include "drmP.h" 31#include "drm.h" 32#include "radeon_drm.h" 33#include "radeon_reg.h" 34#include "radeon.h" 35#include "radeon_asic.h" 36#include "r100d.h" 37#include "rs100d.h" 38#include "rv200d.h" 39#include "rv250d.h" 40#include "atom.h" 41 42#include <linux/firmware.h> 43#include <linux/platform_device.h> 44#include <linux/module.h> 45 46#include "r100_reg_safe.h" 47#include "rn50_reg_safe.h" 48 49/* Firmware Names */ 50#define FIRMWARE_R100 "radeon/R100_cp.bin" 51#define FIRMWARE_R200 "radeon/R200_cp.bin" 52#define FIRMWARE_R300 "radeon/R300_cp.bin" 53#define FIRMWARE_R420 "radeon/R420_cp.bin" 54#define FIRMWARE_RS690 "radeon/RS690_cp.bin" 55#define FIRMWARE_RS600 "radeon/RS600_cp.bin" 56#define FIRMWARE_R520 "radeon/R520_cp.bin" 57 58MODULE_FIRMWARE(FIRMWARE_R100); 59MODULE_FIRMWARE(FIRMWARE_R200); 60MODULE_FIRMWARE(FIRMWARE_R300); 61MODULE_FIRMWARE(FIRMWARE_R420); 62MODULE_FIRMWARE(FIRMWARE_RS690); 63MODULE_FIRMWARE(FIRMWARE_RS600); 64MODULE_FIRMWARE(FIRMWARE_R520); 65 66#include "r100_track.h" 67 68/* This files gather functions specifics to: 69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 70 */ 71 72int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 73 struct radeon_cs_packet *pkt, 74 unsigned idx, 75 unsigned reg) 76{ 77 int r; 78 u32 tile_flags = 0; 79 u32 tmp; 80 struct radeon_cs_reloc *reloc; 81 u32 value; 82 83 r = r100_cs_packet_next_reloc(p, &reloc); 84 if (r) { 85 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 86 idx, reg); 87 r100_cs_dump_packet(p, pkt); 88 return r; 89 } 90 value = radeon_get_ib_value(p, idx); 91 tmp = value & 0x003fffff; 92 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 93 94 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 95 tile_flags |= RADEON_DST_TILE_MACRO; 96 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 97 if (reg == RADEON_SRC_PITCH_OFFSET) { 98 DRM_ERROR("Cannot src blit from microtiled surface\n"); 99 r100_cs_dump_packet(p, pkt); 100 return -EINVAL; 101 } 102 tile_flags |= RADEON_DST_TILE_MICRO; 103 } 104 105 tmp |= tile_flags; 106 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; 107 return 0; 108} 109 110int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 111 struct radeon_cs_packet *pkt, 112 int idx) 113{ 114 unsigned c, i; 115 struct radeon_cs_reloc *reloc; 116 struct r100_cs_track *track; 117 int r = 0; 118 volatile uint32_t *ib; 119 u32 idx_value; 120 121 ib = p->ib->ptr; 122 track = (struct r100_cs_track *)p->track; 123 c = radeon_get_ib_value(p, idx++) & 0x1F; 124 if (c > 16) { 125 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 126 pkt->opcode); 127 r100_cs_dump_packet(p, pkt); 128 return -EINVAL; 129 } 130 track->num_arrays = c; 131 for (i = 0; i < (c - 1); i+=2, idx+=3) { 132 r = r100_cs_packet_next_reloc(p, &reloc); 133 if (r) { 134 DRM_ERROR("No reloc for packet3 %d\n", 135 pkt->opcode); 136 r100_cs_dump_packet(p, pkt); 137 return r; 138 } 139 idx_value = radeon_get_ib_value(p, idx); 140 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 141 142 track->arrays[i + 0].esize = idx_value >> 8; 143 track->arrays[i + 0].robj = reloc->robj; 144 track->arrays[i + 0].esize &= 0x7F; 145 r = r100_cs_packet_next_reloc(p, &reloc); 146 if (r) { 147 DRM_ERROR("No reloc for packet3 %d\n", 148 pkt->opcode); 149 r100_cs_dump_packet(p, pkt); 150 return r; 151 } 152 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 153 track->arrays[i + 1].robj = reloc->robj; 154 track->arrays[i + 1].esize = idx_value >> 24; 155 track->arrays[i + 1].esize &= 0x7F; 156 } 157 if (c & 1) { 158 r = r100_cs_packet_next_reloc(p, &reloc); 159 if (r) { 160 DRM_ERROR("No reloc for packet3 %d\n", 161 pkt->opcode); 162 r100_cs_dump_packet(p, pkt); 163 return r; 164 } 165 idx_value = radeon_get_ib_value(p, idx); 166 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 167 track->arrays[i + 0].robj = reloc->robj; 168 track->arrays[i + 0].esize = idx_value >> 8; 169 track->arrays[i + 0].esize &= 0x7F; 170 } 171 return r; 172} 173 174void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 175{ 176 /* enable the pflip int */ 177 radeon_irq_kms_pflip_irq_get(rdev, crtc); 178} 179 180void r100_post_page_flip(struct radeon_device *rdev, int crtc) 181{ 182 /* disable the pflip int */ 183 radeon_irq_kms_pflip_irq_put(rdev, crtc); 184} 185 186u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 187{ 188 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 189 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 190 int i; 191 192 /* Lock the graphics update lock */ 193 /* update the scanout addresses */ 194 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 195 196 /* Wait for update_pending to go high. */ 197 for (i = 0; i < rdev->usec_timeout; i++) { 198 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 199 break; 200 udelay(1); 201 } 202 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 203 204 /* Unlock the lock, so double-buffering can take place inside vblank */ 205 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 206 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 207 208 /* Return current update_pending status: */ 209 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 210} 211 212void r100_pm_get_dynpm_state(struct radeon_device *rdev) 213{ 214 int i; 215 rdev->pm.dynpm_can_upclock = true; 216 rdev->pm.dynpm_can_downclock = true; 217 218 switch (rdev->pm.dynpm_planned_action) { 219 case DYNPM_ACTION_MINIMUM: 220 rdev->pm.requested_power_state_index = 0; 221 rdev->pm.dynpm_can_downclock = false; 222 break; 223 case DYNPM_ACTION_DOWNCLOCK: 224 if (rdev->pm.current_power_state_index == 0) { 225 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 226 rdev->pm.dynpm_can_downclock = false; 227 } else { 228 if (rdev->pm.active_crtc_count > 1) { 229 for (i = 0; i < rdev->pm.num_power_states; i++) { 230 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 231 continue; 232 else if (i >= rdev->pm.current_power_state_index) { 233 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 234 break; 235 } else { 236 rdev->pm.requested_power_state_index = i; 237 break; 238 } 239 } 240 } else 241 rdev->pm.requested_power_state_index = 242 rdev->pm.current_power_state_index - 1; 243 } 244 /* don't use the power state if crtcs are active and no display flag is set */ 245 if ((rdev->pm.active_crtc_count > 0) && 246 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 247 RADEON_PM_MODE_NO_DISPLAY)) { 248 rdev->pm.requested_power_state_index++; 249 } 250 break; 251 case DYNPM_ACTION_UPCLOCK: 252 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 253 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 254 rdev->pm.dynpm_can_upclock = false; 255 } else { 256 if (rdev->pm.active_crtc_count > 1) { 257 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 258 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 259 continue; 260 else if (i <= rdev->pm.current_power_state_index) { 261 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 262 break; 263 } else { 264 rdev->pm.requested_power_state_index = i; 265 break; 266 } 267 } 268 } else 269 rdev->pm.requested_power_state_index = 270 rdev->pm.current_power_state_index + 1; 271 } 272 break; 273 case DYNPM_ACTION_DEFAULT: 274 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 275 rdev->pm.dynpm_can_upclock = false; 276 break; 277 case DYNPM_ACTION_NONE: 278 default: 279 DRM_ERROR("Requested mode for not defined action\n"); 280 return; 281 } 282 /* only one clock mode per power state */ 283 rdev->pm.requested_clock_mode_index = 0; 284 285 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 286 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 287 clock_info[rdev->pm.requested_clock_mode_index].sclk, 288 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 289 clock_info[rdev->pm.requested_clock_mode_index].mclk, 290 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 291 pcie_lanes); 292} 293 294void r100_pm_init_profile(struct radeon_device *rdev) 295{ 296 /* default */ 297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 300 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 301 /* low sh */ 302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 305 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 306 /* mid sh */ 307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 310 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 311 /* high sh */ 312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 315 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 316 /* low mh */ 317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 321 /* mid mh */ 322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 326 /* high mh */ 327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 330 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 331} 332 333void r100_pm_misc(struct radeon_device *rdev) 334{ 335 int requested_index = rdev->pm.requested_power_state_index; 336 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 337 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 338 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 339 340 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 341 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 342 tmp = RREG32(voltage->gpio.reg); 343 if (voltage->active_high) 344 tmp |= voltage->gpio.mask; 345 else 346 tmp &= ~(voltage->gpio.mask); 347 WREG32(voltage->gpio.reg, tmp); 348 if (voltage->delay) 349 udelay(voltage->delay); 350 } else { 351 tmp = RREG32(voltage->gpio.reg); 352 if (voltage->active_high) 353 tmp &= ~voltage->gpio.mask; 354 else 355 tmp |= voltage->gpio.mask; 356 WREG32(voltage->gpio.reg, tmp); 357 if (voltage->delay) 358 udelay(voltage->delay); 359 } 360 } 361 362 sclk_cntl = RREG32_PLL(SCLK_CNTL); 363 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 364 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 365 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 366 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 367 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 368 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 369 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 370 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 371 else 372 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 373 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 374 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 375 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 376 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 377 } else 378 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 379 380 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 381 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 382 if (voltage->delay) { 383 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 384 switch (voltage->delay) { 385 case 33: 386 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 387 break; 388 case 66: 389 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 390 break; 391 case 99: 392 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 393 break; 394 case 132: 395 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 396 break; 397 } 398 } else 399 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 400 } else 401 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 402 403 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 404 sclk_cntl &= ~FORCE_HDP; 405 else 406 sclk_cntl |= FORCE_HDP; 407 408 WREG32_PLL(SCLK_CNTL, sclk_cntl); 409 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 410 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 411 412 /* set pcie lanes */ 413 if ((rdev->flags & RADEON_IS_PCIE) && 414 !(rdev->flags & RADEON_IS_IGP) && 415 rdev->asic->set_pcie_lanes && 416 (ps->pcie_lanes != 417 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 418 radeon_set_pcie_lanes(rdev, 419 ps->pcie_lanes); 420 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 421 } 422} 423 424void r100_pm_prepare(struct radeon_device *rdev) 425{ 426 struct drm_device *ddev = rdev->ddev; 427 struct drm_crtc *crtc; 428 struct radeon_crtc *radeon_crtc; 429 u32 tmp; 430 431 /* disable any active CRTCs */ 432 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 433 radeon_crtc = to_radeon_crtc(crtc); 434 if (radeon_crtc->enabled) { 435 if (radeon_crtc->crtc_id) { 436 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 437 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 438 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 439 } else { 440 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 441 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 442 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 443 } 444 } 445 } 446} 447 448void r100_pm_finish(struct radeon_device *rdev) 449{ 450 struct drm_device *ddev = rdev->ddev; 451 struct drm_crtc *crtc; 452 struct radeon_crtc *radeon_crtc; 453 u32 tmp; 454 455 /* enable any active CRTCs */ 456 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 457 radeon_crtc = to_radeon_crtc(crtc); 458 if (radeon_crtc->enabled) { 459 if (radeon_crtc->crtc_id) { 460 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 461 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 462 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 463 } else { 464 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 465 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 466 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 467 } 468 } 469 } 470} 471 472bool r100_gui_idle(struct radeon_device *rdev) 473{ 474 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 475 return false; 476 else 477 return true; 478} 479 480/* hpd for digital panel detect/disconnect */ 481bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 482{ 483 bool connected = false; 484 485 switch (hpd) { 486 case RADEON_HPD_1: 487 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 488 connected = true; 489 break; 490 case RADEON_HPD_2: 491 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 492 connected = true; 493 break; 494 default: 495 break; 496 } 497 return connected; 498} 499 500void r100_hpd_set_polarity(struct radeon_device *rdev, 501 enum radeon_hpd_id hpd) 502{ 503 u32 tmp; 504 bool connected = r100_hpd_sense(rdev, hpd); 505 506 switch (hpd) { 507 case RADEON_HPD_1: 508 tmp = RREG32(RADEON_FP_GEN_CNTL); 509 if (connected) 510 tmp &= ~RADEON_FP_DETECT_INT_POL; 511 else 512 tmp |= RADEON_FP_DETECT_INT_POL; 513 WREG32(RADEON_FP_GEN_CNTL, tmp); 514 break; 515 case RADEON_HPD_2: 516 tmp = RREG32(RADEON_FP2_GEN_CNTL); 517 if (connected) 518 tmp &= ~RADEON_FP2_DETECT_INT_POL; 519 else 520 tmp |= RADEON_FP2_DETECT_INT_POL; 521 WREG32(RADEON_FP2_GEN_CNTL, tmp); 522 break; 523 default: 524 break; 525 } 526} 527 528void r100_hpd_init(struct radeon_device *rdev) 529{ 530 struct drm_device *dev = rdev->ddev; 531 struct drm_connector *connector; 532 533 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 534 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 535 switch (radeon_connector->hpd.hpd) { 536 case RADEON_HPD_1: 537 rdev->irq.hpd[0] = true; 538 break; 539 case RADEON_HPD_2: 540 rdev->irq.hpd[1] = true; 541 break; 542 default: 543 break; 544 } 545 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 546 } 547 if (rdev->irq.installed) 548 r100_irq_set(rdev); 549} 550 551void r100_hpd_fini(struct radeon_device *rdev) 552{ 553 struct drm_device *dev = rdev->ddev; 554 struct drm_connector *connector; 555 556 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 557 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 558 switch (radeon_connector->hpd.hpd) { 559 case RADEON_HPD_1: 560 rdev->irq.hpd[0] = false; 561 break; 562 case RADEON_HPD_2: 563 rdev->irq.hpd[1] = false; 564 break; 565 default: 566 break; 567 } 568 } 569} 570 571/* 572 * PCI GART 573 */ 574void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 575{ 576 /* TODO: can we do somethings here ? */ 577 /* It seems hw only cache one entry so we should discard this 578 * entry otherwise if first GPU GART read hit this entry it 579 * could end up in wrong address. */ 580} 581 582int r100_pci_gart_init(struct radeon_device *rdev) 583{ 584 int r; 585 586 if (rdev->gart.ptr) { 587 WARN(1, "R100 PCI GART already initialized\n"); 588 return 0; 589 } 590 /* Initialize common gart structure */ 591 r = radeon_gart_init(rdev); 592 if (r) 593 return r; 594 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 595 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 596 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 597 return radeon_gart_table_ram_alloc(rdev); 598} 599 600/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 601void r100_enable_bm(struct radeon_device *rdev) 602{ 603 uint32_t tmp; 604 /* Enable bus mastering */ 605 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 606 WREG32(RADEON_BUS_CNTL, tmp); 607} 608 609int r100_pci_gart_enable(struct radeon_device *rdev) 610{ 611 uint32_t tmp; 612 613 radeon_gart_restore(rdev); 614 /* discard memory request outside of configured range */ 615 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 616 WREG32(RADEON_AIC_CNTL, tmp); 617 /* set address range for PCI address translate */ 618 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 619 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 620 /* set PCI GART page-table base address */ 621 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 622 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 623 WREG32(RADEON_AIC_CNTL, tmp); 624 r100_pci_gart_tlb_flush(rdev); 625 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 626 (unsigned)(rdev->mc.gtt_size >> 20), 627 (unsigned long long)rdev->gart.table_addr); 628 rdev->gart.ready = true; 629 return 0; 630} 631 632void r100_pci_gart_disable(struct radeon_device *rdev) 633{ 634 uint32_t tmp; 635 636 /* discard memory request outside of configured range */ 637 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 638 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 639 WREG32(RADEON_AIC_LO_ADDR, 0); 640 WREG32(RADEON_AIC_HI_ADDR, 0); 641} 642 643int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 644{ 645 u32 *gtt = rdev->gart.ptr; 646 647 if (i < 0 || i > rdev->gart.num_gpu_pages) { 648 return -EINVAL; 649 } 650 gtt[i] = cpu_to_le32(lower_32_bits(addr)); 651 return 0; 652} 653 654void r100_pci_gart_fini(struct radeon_device *rdev) 655{ 656 radeon_gart_fini(rdev); 657 r100_pci_gart_disable(rdev); 658 radeon_gart_table_ram_free(rdev); 659} 660 661int r100_irq_set(struct radeon_device *rdev) 662{ 663 uint32_t tmp = 0; 664 665 if (!rdev->irq.installed) { 666 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 667 WREG32(R_000040_GEN_INT_CNTL, 0); 668 return -EINVAL; 669 } 670 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { 671 tmp |= RADEON_SW_INT_ENABLE; 672 } 673 if (rdev->irq.gui_idle) { 674 tmp |= RADEON_GUI_IDLE_MASK; 675 } 676 if (rdev->irq.crtc_vblank_int[0] || 677 rdev->irq.pflip[0]) { 678 tmp |= RADEON_CRTC_VBLANK_MASK; 679 } 680 if (rdev->irq.crtc_vblank_int[1] || 681 rdev->irq.pflip[1]) { 682 tmp |= RADEON_CRTC2_VBLANK_MASK; 683 } 684 if (rdev->irq.hpd[0]) { 685 tmp |= RADEON_FP_DETECT_MASK; 686 } 687 if (rdev->irq.hpd[1]) { 688 tmp |= RADEON_FP2_DETECT_MASK; 689 } 690 WREG32(RADEON_GEN_INT_CNTL, tmp); 691 return 0; 692} 693 694void r100_irq_disable(struct radeon_device *rdev) 695{ 696 u32 tmp; 697 698 WREG32(R_000040_GEN_INT_CNTL, 0); 699 /* Wait and acknowledge irq */ 700 mdelay(1); 701 tmp = RREG32(R_000044_GEN_INT_STATUS); 702 WREG32(R_000044_GEN_INT_STATUS, tmp); 703} 704 705static uint32_t r100_irq_ack(struct radeon_device *rdev) 706{ 707 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 708 uint32_t irq_mask = RADEON_SW_INT_TEST | 709 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 710 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 711 712 /* the interrupt works, but the status bit is permanently asserted */ 713 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { 714 if (!rdev->irq.gui_idle_acked) 715 irq_mask |= RADEON_GUI_IDLE_STAT; 716 } 717 718 if (irqs) { 719 WREG32(RADEON_GEN_INT_STATUS, irqs); 720 } 721 return irqs & irq_mask; 722} 723 724int r100_irq_process(struct radeon_device *rdev) 725{ 726 uint32_t status, msi_rearm; 727 bool queue_hotplug = false; 728 729 /* reset gui idle ack. the status bit is broken */ 730 rdev->irq.gui_idle_acked = false; 731 732 status = r100_irq_ack(rdev); 733 if (!status) { 734 return IRQ_NONE; 735 } 736 if (rdev->shutdown) { 737 return IRQ_NONE; 738 } 739 while (status) { 740 /* SW interrupt */ 741 if (status & RADEON_SW_INT_TEST) { 742 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 743 } 744 /* gui idle interrupt */ 745 if (status & RADEON_GUI_IDLE_STAT) { 746 rdev->irq.gui_idle_acked = true; 747 rdev->pm.gui_idle = true; 748 wake_up(&rdev->irq.idle_queue); 749 } 750 /* Vertical blank interrupts */ 751 if (status & RADEON_CRTC_VBLANK_STAT) { 752 if (rdev->irq.crtc_vblank_int[0]) { 753 drm_handle_vblank(rdev->ddev, 0); 754 rdev->pm.vblank_sync = true; 755 wake_up(&rdev->irq.vblank_queue); 756 } 757 if (rdev->irq.pflip[0]) 758 radeon_crtc_handle_flip(rdev, 0); 759 } 760 if (status & RADEON_CRTC2_VBLANK_STAT) { 761 if (rdev->irq.crtc_vblank_int[1]) { 762 drm_handle_vblank(rdev->ddev, 1); 763 rdev->pm.vblank_sync = true; 764 wake_up(&rdev->irq.vblank_queue); 765 } 766 if (rdev->irq.pflip[1]) 767 radeon_crtc_handle_flip(rdev, 1); 768 } 769 if (status & RADEON_FP_DETECT_STAT) { 770 queue_hotplug = true; 771 DRM_DEBUG("HPD1\n"); 772 } 773 if (status & RADEON_FP2_DETECT_STAT) { 774 queue_hotplug = true; 775 DRM_DEBUG("HPD2\n"); 776 } 777 status = r100_irq_ack(rdev); 778 } 779 /* reset gui idle ack. the status bit is broken */ 780 rdev->irq.gui_idle_acked = false; 781 if (queue_hotplug) 782 schedule_work(&rdev->hotplug_work); 783 if (rdev->msi_enabled) { 784 switch (rdev->family) { 785 case CHIP_RS400: 786 case CHIP_RS480: 787 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 788 WREG32(RADEON_AIC_CNTL, msi_rearm); 789 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 790 break; 791 default: 792 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 793 break; 794 } 795 } 796 return IRQ_HANDLED; 797} 798 799u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 800{ 801 if (crtc == 0) 802 return RREG32(RADEON_CRTC_CRNT_FRAME); 803 else 804 return RREG32(RADEON_CRTC2_CRNT_FRAME); 805} 806 807/* Who ever call radeon_fence_emit should call ring_lock and ask 808 * for enough space (today caller are ib schedule and buffer move) */ 809void r100_fence_ring_emit(struct radeon_device *rdev, 810 struct radeon_fence *fence) 811{ 812 struct radeon_ring *ring = &rdev->ring[fence->ring]; 813 814 /* We have to make sure that caches are flushed before 815 * CPU might read something from VRAM. */ 816 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 817 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 818 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 819 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 820 /* Wait until IDLE & CLEAN */ 821 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 822 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 823 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 824 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 825 RADEON_HDP_READ_BUFFER_INVALIDATE); 826 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 827 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 828 /* Emit fence sequence & fire IRQ */ 829 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 830 radeon_ring_write(ring, fence->seq); 831 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 832 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 833} 834 835void r100_semaphore_ring_emit(struct radeon_device *rdev, 836 struct radeon_ring *ring, 837 struct radeon_semaphore *semaphore, 838 bool emit_wait) 839{ 840 /* Unused on older asics, since we don't have semaphores or multiple rings */ 841 BUG(); 842} 843 844int r100_copy_blit(struct radeon_device *rdev, 845 uint64_t src_offset, 846 uint64_t dst_offset, 847 unsigned num_gpu_pages, 848 struct radeon_fence *fence) 849{ 850 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 851 uint32_t cur_pages; 852 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 853 uint32_t pitch; 854 uint32_t stride_pixels; 855 unsigned ndw; 856 int num_loops; 857 int r = 0; 858 859 /* radeon limited to 16k stride */ 860 stride_bytes &= 0x3fff; 861 /* radeon pitch is /64 */ 862 pitch = stride_bytes / 64; 863 stride_pixels = stride_bytes / 4; 864 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 865 866 /* Ask for enough room for blit + flush + fence */ 867 ndw = 64 + (10 * num_loops); 868 r = radeon_ring_lock(rdev, ring, ndw); 869 if (r) { 870 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 871 return -EINVAL; 872 } 873 while (num_gpu_pages > 0) { 874 cur_pages = num_gpu_pages; 875 if (cur_pages > 8191) { 876 cur_pages = 8191; 877 } 878 num_gpu_pages -= cur_pages; 879 880 /* pages are in Y direction - height 881 page width in X direction - width */ 882 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 883 radeon_ring_write(ring, 884 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 885 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 886 RADEON_GMC_SRC_CLIPPING | 887 RADEON_GMC_DST_CLIPPING | 888 RADEON_GMC_BRUSH_NONE | 889 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 890 RADEON_GMC_SRC_DATATYPE_COLOR | 891 RADEON_ROP3_S | 892 RADEON_DP_SRC_SOURCE_MEMORY | 893 RADEON_GMC_CLR_CMP_CNTL_DIS | 894 RADEON_GMC_WR_MSK_DIS); 895 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 896 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 897 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 898 radeon_ring_write(ring, 0); 899 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 900 radeon_ring_write(ring, num_gpu_pages); 901 radeon_ring_write(ring, num_gpu_pages); 902 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 903 } 904 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 905 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 906 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 907 radeon_ring_write(ring, 908 RADEON_WAIT_2D_IDLECLEAN | 909 RADEON_WAIT_HOST_IDLECLEAN | 910 RADEON_WAIT_DMA_GUI_IDLE); 911 if (fence) { 912 r = radeon_fence_emit(rdev, fence); 913 } 914 radeon_ring_unlock_commit(rdev, ring); 915 return r; 916} 917 918static int r100_cp_wait_for_idle(struct radeon_device *rdev) 919{ 920 unsigned i; 921 u32 tmp; 922 923 for (i = 0; i < rdev->usec_timeout; i++) { 924 tmp = RREG32(R_000E40_RBBM_STATUS); 925 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 926 return 0; 927 } 928 udelay(1); 929 } 930 return -1; 931} 932 933void r100_ring_start(struct radeon_device *rdev) 934{ 935 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 936 int r; 937 938 r = radeon_ring_lock(rdev, ring, 2); 939 if (r) { 940 return; 941 } 942 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 943 radeon_ring_write(ring, 944 RADEON_ISYNC_ANY2D_IDLE3D | 945 RADEON_ISYNC_ANY3D_IDLE2D | 946 RADEON_ISYNC_WAIT_IDLEGUI | 947 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 948 radeon_ring_unlock_commit(rdev, ring); 949} 950 951 952/* Load the microcode for the CP */ 953static int r100_cp_init_microcode(struct radeon_device *rdev) 954{ 955 struct platform_device *pdev; 956 const char *fw_name = NULL; 957 int err; 958 959 DRM_DEBUG_KMS("\n"); 960 961 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 962 err = IS_ERR(pdev); 963 if (err) { 964 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 965 return -EINVAL; 966 } 967 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 968 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 969 (rdev->family == CHIP_RS200)) { 970 DRM_INFO("Loading R100 Microcode\n"); 971 fw_name = FIRMWARE_R100; 972 } else if ((rdev->family == CHIP_R200) || 973 (rdev->family == CHIP_RV250) || 974 (rdev->family == CHIP_RV280) || 975 (rdev->family == CHIP_RS300)) { 976 DRM_INFO("Loading R200 Microcode\n"); 977 fw_name = FIRMWARE_R200; 978 } else if ((rdev->family == CHIP_R300) || 979 (rdev->family == CHIP_R350) || 980 (rdev->family == CHIP_RV350) || 981 (rdev->family == CHIP_RV380) || 982 (rdev->family == CHIP_RS400) || 983 (rdev->family == CHIP_RS480)) { 984 DRM_INFO("Loading R300 Microcode\n"); 985 fw_name = FIRMWARE_R300; 986 } else if ((rdev->family == CHIP_R420) || 987 (rdev->family == CHIP_R423) || 988 (rdev->family == CHIP_RV410)) { 989 DRM_INFO("Loading R400 Microcode\n"); 990 fw_name = FIRMWARE_R420; 991 } else if ((rdev->family == CHIP_RS690) || 992 (rdev->family == CHIP_RS740)) { 993 DRM_INFO("Loading RS690/RS740 Microcode\n"); 994 fw_name = FIRMWARE_RS690; 995 } else if (rdev->family == CHIP_RS600) { 996 DRM_INFO("Loading RS600 Microcode\n"); 997 fw_name = FIRMWARE_RS600; 998 } else if ((rdev->family == CHIP_RV515) || 999 (rdev->family == CHIP_R520) || 1000 (rdev->family == CHIP_RV530) || 1001 (rdev->family == CHIP_R580) || 1002 (rdev->family == CHIP_RV560) || 1003 (rdev->family == CHIP_RV570)) { 1004 DRM_INFO("Loading R500 Microcode\n"); 1005 fw_name = FIRMWARE_R520; 1006 } 1007 1008 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 1009 platform_device_unregister(pdev); 1010 if (err) { 1011 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 1012 fw_name); 1013 } else if (rdev->me_fw->size % 8) { 1014 printk(KERN_ERR 1015 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1016 rdev->me_fw->size, fw_name); 1017 err = -EINVAL; 1018 release_firmware(rdev->me_fw); 1019 rdev->me_fw = NULL; 1020 } 1021 return err; 1022} 1023 1024static void r100_cp_load_microcode(struct radeon_device *rdev) 1025{ 1026 const __be32 *fw_data; 1027 int i, size; 1028 1029 if (r100_gui_wait_for_idle(rdev)) { 1030 printk(KERN_WARNING "Failed to wait GUI idle while " 1031 "programming pipes. Bad things might happen.\n"); 1032 } 1033 1034 if (rdev->me_fw) { 1035 size = rdev->me_fw->size / 4; 1036 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1037 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1038 for (i = 0; i < size; i += 2) { 1039 WREG32(RADEON_CP_ME_RAM_DATAH, 1040 be32_to_cpup(&fw_data[i])); 1041 WREG32(RADEON_CP_ME_RAM_DATAL, 1042 be32_to_cpup(&fw_data[i + 1])); 1043 } 1044 } 1045} 1046 1047int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1048{ 1049 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1050 unsigned rb_bufsz; 1051 unsigned rb_blksz; 1052 unsigned max_fetch; 1053 unsigned pre_write_timer; 1054 unsigned pre_write_limit; 1055 unsigned indirect2_start; 1056 unsigned indirect1_start; 1057 uint32_t tmp; 1058 int r; 1059 1060 if (r100_debugfs_cp_init(rdev)) { 1061 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1062 } 1063 if (!rdev->me_fw) { 1064 r = r100_cp_init_microcode(rdev); 1065 if (r) { 1066 DRM_ERROR("Failed to load firmware!\n"); 1067 return r; 1068 } 1069 } 1070 1071 /* Align ring size */ 1072 rb_bufsz = drm_order(ring_size / 8); 1073 ring_size = (1 << (rb_bufsz + 1)) * 4; 1074 r100_cp_load_microcode(rdev); 1075 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1076 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, 1077 0, 0x7fffff, RADEON_CP_PACKET2); 1078 if (r) { 1079 return r; 1080 } 1081 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1082 * the rptr copy in system ram */ 1083 rb_blksz = 9; 1084 /* cp will read 128bytes at a time (4 dwords) */ 1085 max_fetch = 1; 1086 ring->align_mask = 16 - 1; 1087 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1088 pre_write_timer = 64; 1089 /* Force CP_RB_WPTR write if written more than one time before the 1090 * delay expire 1091 */ 1092 pre_write_limit = 0; 1093 /* Setup the cp cache like this (cache size is 96 dwords) : 1094 * RING 0 to 15 1095 * INDIRECT1 16 to 79 1096 * INDIRECT2 80 to 95 1097 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1098 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1099 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1100 * Idea being that most of the gpu cmd will be through indirect1 buffer 1101 * so it gets the bigger cache. 1102 */ 1103 indirect2_start = 80; 1104 indirect1_start = 16; 1105 /* cp setup */ 1106 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1107 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1108 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1109 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1110#ifdef __BIG_ENDIAN 1111 tmp |= RADEON_BUF_SWAP_32BIT; 1112#endif 1113 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1114 1115 /* Set ring address */ 1116 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1117 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1118 /* Force read & write ptr to 0 */ 1119 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1120 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1121 ring->wptr = 0; 1122 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1123 1124 /* set the wb address whether it's enabled or not */ 1125 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1126 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1127 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1128 1129 if (rdev->wb.enabled) 1130 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1131 else { 1132 tmp |= RADEON_RB_NO_UPDATE; 1133 WREG32(R_000770_SCRATCH_UMSK, 0); 1134 } 1135 1136 WREG32(RADEON_CP_RB_CNTL, tmp); 1137 udelay(10); 1138 ring->rptr = RREG32(RADEON_CP_RB_RPTR); 1139 /* Set cp mode to bus mastering & enable cp*/ 1140 WREG32(RADEON_CP_CSQ_MODE, 1141 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1142 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1143 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1144 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1145 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1146 radeon_ring_start(rdev); 1147 r = radeon_ring_test(rdev, ring); 1148 if (r) { 1149 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1150 return r; 1151 } 1152 ring->ready = true; 1153 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1154 return 0; 1155} 1156 1157void r100_cp_fini(struct radeon_device *rdev) 1158{ 1159 if (r100_cp_wait_for_idle(rdev)) { 1160 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1161 } 1162 /* Disable ring */ 1163 r100_cp_disable(rdev); 1164 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1165 DRM_INFO("radeon: cp finalized\n"); 1166} 1167 1168void r100_cp_disable(struct radeon_device *rdev) 1169{ 1170 /* Disable ring */ 1171 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1172 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1173 WREG32(RADEON_CP_CSQ_MODE, 0); 1174 WREG32(RADEON_CP_CSQ_CNTL, 0); 1175 WREG32(R_000770_SCRATCH_UMSK, 0); 1176 if (r100_gui_wait_for_idle(rdev)) { 1177 printk(KERN_WARNING "Failed to wait GUI idle while " 1178 "programming pipes. Bad things might happen.\n"); 1179 } 1180} 1181 1182/* 1183 * CS functions 1184 */ 1185int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1186 struct radeon_cs_packet *pkt, 1187 const unsigned *auth, unsigned n, 1188 radeon_packet0_check_t check) 1189{ 1190 unsigned reg; 1191 unsigned i, j, m; 1192 unsigned idx; 1193 int r; 1194 1195 idx = pkt->idx + 1; 1196 reg = pkt->reg; 1197 /* Check that register fall into register range 1198 * determined by the number of entry (n) in the 1199 * safe register bitmap. 1200 */ 1201 if (pkt->one_reg_wr) { 1202 if ((reg >> 7) > n) { 1203 return -EINVAL; 1204 } 1205 } else { 1206 if (((reg + (pkt->count << 2)) >> 7) > n) { 1207 return -EINVAL; 1208 } 1209 } 1210 for (i = 0; i <= pkt->count; i++, idx++) { 1211 j = (reg >> 7); 1212 m = 1 << ((reg >> 2) & 31); 1213 if (auth[j] & m) { 1214 r = check(p, pkt, idx, reg); 1215 if (r) { 1216 return r; 1217 } 1218 } 1219 if (pkt->one_reg_wr) { 1220 if (!(auth[j] & m)) { 1221 break; 1222 } 1223 } else { 1224 reg += 4; 1225 } 1226 } 1227 return 0; 1228} 1229 1230void r100_cs_dump_packet(struct radeon_cs_parser *p, 1231 struct radeon_cs_packet *pkt) 1232{ 1233 volatile uint32_t *ib; 1234 unsigned i; 1235 unsigned idx; 1236 1237 ib = p->ib->ptr; 1238 idx = pkt->idx; 1239 for (i = 0; i <= (pkt->count + 1); i++, idx++) { 1240 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 1241 } 1242} 1243 1244/** 1245 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 1246 * @parser: parser structure holding parsing context. 1247 * @pkt: where to store packet informations 1248 * 1249 * Assume that chunk_ib_index is properly set. Will return -EINVAL 1250 * if packet is bigger than remaining ib size. or if packets is unknown. 1251 **/ 1252int r100_cs_packet_parse(struct radeon_cs_parser *p, 1253 struct radeon_cs_packet *pkt, 1254 unsigned idx) 1255{ 1256 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 1257 uint32_t header; 1258 1259 if (idx >= ib_chunk->length_dw) { 1260 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 1261 idx, ib_chunk->length_dw); 1262 return -EINVAL; 1263 } 1264 header = radeon_get_ib_value(p, idx); 1265 pkt->idx = idx; 1266 pkt->type = CP_PACKET_GET_TYPE(header); 1267 pkt->count = CP_PACKET_GET_COUNT(header); 1268 switch (pkt->type) { 1269 case PACKET_TYPE0: 1270 pkt->reg = CP_PACKET0_GET_REG(header); 1271 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 1272 break; 1273 case PACKET_TYPE3: 1274 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 1275 break; 1276 case PACKET_TYPE2: 1277 pkt->count = -1; 1278 break; 1279 default: 1280 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 1281 return -EINVAL; 1282 } 1283 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 1284 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 1285 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 1286 return -EINVAL; 1287 } 1288 return 0; 1289} 1290 1291/** 1292 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1293 * @parser: parser structure holding parsing context. 1294 * 1295 * Userspace sends a special sequence for VLINE waits. 1296 * PACKET0 - VLINE_START_END + value 1297 * PACKET0 - WAIT_UNTIL +_value 1298 * RELOC (P3) - crtc_id in reloc. 1299 * 1300 * This function parses this and relocates the VLINE START END 1301 * and WAIT UNTIL packets to the correct crtc. 1302 * It also detects a switched off crtc and nulls out the 1303 * wait in that case. 1304 */ 1305int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1306{ 1307 struct drm_mode_object *obj; 1308 struct drm_crtc *crtc; 1309 struct radeon_crtc *radeon_crtc; 1310 struct radeon_cs_packet p3reloc, waitreloc; 1311 int crtc_id; 1312 int r; 1313 uint32_t header, h_idx, reg; 1314 volatile uint32_t *ib; 1315 1316 ib = p->ib->ptr; 1317 1318 /* parse the wait until */ 1319 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 1320 if (r) 1321 return r; 1322 1323 /* check its a wait until and only 1 count */ 1324 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1325 waitreloc.count != 0) { 1326 DRM_ERROR("vline wait had illegal wait until segment\n"); 1327 return -EINVAL; 1328 } 1329 1330 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1331 DRM_ERROR("vline wait had illegal wait until\n"); 1332 return -EINVAL; 1333 } 1334 1335 /* jump over the NOP */ 1336 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1337 if (r) 1338 return r; 1339 1340 h_idx = p->idx - 2; 1341 p->idx += waitreloc.count + 2; 1342 p->idx += p3reloc.count + 2; 1343 1344 header = radeon_get_ib_value(p, h_idx); 1345 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1346 reg = CP_PACKET0_GET_REG(header); 1347 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1348 if (!obj) { 1349 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1350 return -EINVAL; 1351 } 1352 crtc = obj_to_crtc(obj); 1353 radeon_crtc = to_radeon_crtc(crtc); 1354 crtc_id = radeon_crtc->crtc_id; 1355 1356 if (!crtc->enabled) { 1357 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1358 ib[h_idx + 2] = PACKET2(0); 1359 ib[h_idx + 3] = PACKET2(0); 1360 } else if (crtc_id == 1) { 1361 switch (reg) { 1362 case AVIVO_D1MODE_VLINE_START_END: 1363 header &= ~R300_CP_PACKET0_REG_MASK; 1364 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1365 break; 1366 case RADEON_CRTC_GUI_TRIG_VLINE: 1367 header &= ~R300_CP_PACKET0_REG_MASK; 1368 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1369 break; 1370 default: 1371 DRM_ERROR("unknown crtc reloc\n"); 1372 return -EINVAL; 1373 } 1374 ib[h_idx] = header; 1375 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1376 } 1377 1378 return 0; 1379} 1380 1381/** 1382 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1383 * @parser: parser structure holding parsing context. 1384 * @data: pointer to relocation data 1385 * @offset_start: starting offset 1386 * @offset_mask: offset mask (to align start offset on) 1387 * @reloc: reloc informations 1388 * 1389 * Check next packet is relocation packet3, do bo validation and compute 1390 * GPU offset using the provided start. 1391 **/ 1392int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1393 struct radeon_cs_reloc **cs_reloc) 1394{ 1395 struct radeon_cs_chunk *relocs_chunk; 1396 struct radeon_cs_packet p3reloc; 1397 unsigned idx; 1398 int r; 1399 1400 if (p->chunk_relocs_idx == -1) { 1401 DRM_ERROR("No relocation chunk !\n"); 1402 return -EINVAL; 1403 } 1404 *cs_reloc = NULL; 1405 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1406 r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1407 if (r) { 1408 return r; 1409 } 1410 p->idx += p3reloc.count + 2; 1411 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1412 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1413 p3reloc.idx); 1414 r100_cs_dump_packet(p, &p3reloc); 1415 return -EINVAL; 1416 } 1417 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1418 if (idx >= relocs_chunk->length_dw) { 1419 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1420 idx, relocs_chunk->length_dw); 1421 r100_cs_dump_packet(p, &p3reloc); 1422 return -EINVAL; 1423 } 1424 /* FIXME: we assume reloc size is 4 dwords */ 1425 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1426 return 0; 1427} 1428 1429static int r100_get_vtx_size(uint32_t vtx_fmt) 1430{ 1431 int vtx_size; 1432 vtx_size = 2; 1433 /* ordered according to bits in spec */ 1434 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1435 vtx_size++; 1436 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1437 vtx_size += 3; 1438 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1439 vtx_size++; 1440 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1441 vtx_size++; 1442 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1443 vtx_size += 3; 1444 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1445 vtx_size++; 1446 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1447 vtx_size++; 1448 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1449 vtx_size += 2; 1450 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1451 vtx_size += 2; 1452 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1453 vtx_size++; 1454 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1455 vtx_size += 2; 1456 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1457 vtx_size++; 1458 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1459 vtx_size += 2; 1460 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1461 vtx_size++; 1462 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1463 vtx_size++; 1464 /* blend weight */ 1465 if (vtx_fmt & (0x7 << 15)) 1466 vtx_size += (vtx_fmt >> 15) & 0x7; 1467 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1468 vtx_size += 3; 1469 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1470 vtx_size += 2; 1471 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1472 vtx_size++; 1473 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1474 vtx_size++; 1475 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1476 vtx_size++; 1477 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1478 vtx_size++; 1479 return vtx_size; 1480} 1481 1482static int r100_packet0_check(struct radeon_cs_parser *p, 1483 struct radeon_cs_packet *pkt, 1484 unsigned idx, unsigned reg) 1485{ 1486 struct radeon_cs_reloc *reloc; 1487 struct r100_cs_track *track; 1488 volatile uint32_t *ib; 1489 uint32_t tmp; 1490 int r; 1491 int i, face; 1492 u32 tile_flags = 0; 1493 u32 idx_value; 1494 1495 ib = p->ib->ptr; 1496 track = (struct r100_cs_track *)p->track; 1497 1498 idx_value = radeon_get_ib_value(p, idx); 1499 1500 switch (reg) { 1501 case RADEON_CRTC_GUI_TRIG_VLINE: 1502 r = r100_cs_packet_parse_vline(p); 1503 if (r) { 1504 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1505 idx, reg); 1506 r100_cs_dump_packet(p, pkt); 1507 return r; 1508 } 1509 break; 1510 /* FIXME: only allow PACKET3 blit? easier to check for out of 1511 * range access */ 1512 case RADEON_DST_PITCH_OFFSET: 1513 case RADEON_SRC_PITCH_OFFSET: 1514 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1515 if (r) 1516 return r; 1517 break; 1518 case RADEON_RB3D_DEPTHOFFSET: 1519 r = r100_cs_packet_next_reloc(p, &reloc); 1520 if (r) { 1521 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1522 idx, reg); 1523 r100_cs_dump_packet(p, pkt); 1524 return r; 1525 } 1526 track->zb.robj = reloc->robj; 1527 track->zb.offset = idx_value; 1528 track->zb_dirty = true; 1529 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1530 break; 1531 case RADEON_RB3D_COLOROFFSET: 1532 r = r100_cs_packet_next_reloc(p, &reloc); 1533 if (r) { 1534 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1535 idx, reg); 1536 r100_cs_dump_packet(p, pkt); 1537 return r; 1538 } 1539 track->cb[0].robj = reloc->robj; 1540 track->cb[0].offset = idx_value; 1541 track->cb_dirty = true; 1542 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1543 break; 1544 case RADEON_PP_TXOFFSET_0: 1545 case RADEON_PP_TXOFFSET_1: 1546 case RADEON_PP_TXOFFSET_2: 1547 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1548 r = r100_cs_packet_next_reloc(p, &reloc); 1549 if (r) { 1550 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1551 idx, reg); 1552 r100_cs_dump_packet(p, pkt); 1553 return r; 1554 } 1555 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1556 track->textures[i].robj = reloc->robj; 1557 track->tex_dirty = true; 1558 break; 1559 case RADEON_PP_CUBIC_OFFSET_T0_0: 1560 case RADEON_PP_CUBIC_OFFSET_T0_1: 1561 case RADEON_PP_CUBIC_OFFSET_T0_2: 1562 case RADEON_PP_CUBIC_OFFSET_T0_3: 1563 case RADEON_PP_CUBIC_OFFSET_T0_4: 1564 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1565 r = r100_cs_packet_next_reloc(p, &reloc); 1566 if (r) { 1567 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1568 idx, reg); 1569 r100_cs_dump_packet(p, pkt); 1570 return r; 1571 } 1572 track->textures[0].cube_info[i].offset = idx_value; 1573 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1574 track->textures[0].cube_info[i].robj = reloc->robj; 1575 track->tex_dirty = true; 1576 break; 1577 case RADEON_PP_CUBIC_OFFSET_T1_0: 1578 case RADEON_PP_CUBIC_OFFSET_T1_1: 1579 case RADEON_PP_CUBIC_OFFSET_T1_2: 1580 case RADEON_PP_CUBIC_OFFSET_T1_3: 1581 case RADEON_PP_CUBIC_OFFSET_T1_4: 1582 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1583 r = r100_cs_packet_next_reloc(p, &reloc); 1584 if (r) { 1585 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1586 idx, reg); 1587 r100_cs_dump_packet(p, pkt); 1588 return r; 1589 } 1590 track->textures[1].cube_info[i].offset = idx_value; 1591 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1592 track->textures[1].cube_info[i].robj = reloc->robj; 1593 track->tex_dirty = true; 1594 break; 1595 case RADEON_PP_CUBIC_OFFSET_T2_0: 1596 case RADEON_PP_CUBIC_OFFSET_T2_1: 1597 case RADEON_PP_CUBIC_OFFSET_T2_2: 1598 case RADEON_PP_CUBIC_OFFSET_T2_3: 1599 case RADEON_PP_CUBIC_OFFSET_T2_4: 1600 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1601 r = r100_cs_packet_next_reloc(p, &reloc); 1602 if (r) { 1603 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1604 idx, reg); 1605 r100_cs_dump_packet(p, pkt); 1606 return r; 1607 } 1608 track->textures[2].cube_info[i].offset = idx_value; 1609 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1610 track->textures[2].cube_info[i].robj = reloc->robj; 1611 track->tex_dirty = true; 1612 break; 1613 case RADEON_RE_WIDTH_HEIGHT: 1614 track->maxy = ((idx_value >> 16) & 0x7FF); 1615 track->cb_dirty = true; 1616 track->zb_dirty = true; 1617 break; 1618 case RADEON_RB3D_COLORPITCH: 1619 r = r100_cs_packet_next_reloc(p, &reloc); 1620 if (r) { 1621 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1622 idx, reg); 1623 r100_cs_dump_packet(p, pkt); 1624 return r; 1625 } 1626 1627 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1628 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1629 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1630 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1631 1632 tmp = idx_value & ~(0x7 << 16); 1633 tmp |= tile_flags; 1634 ib[idx] = tmp; 1635 1636 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1637 track->cb_dirty = true; 1638 break; 1639 case RADEON_RB3D_DEPTHPITCH: 1640 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1641 track->zb_dirty = true; 1642 break; 1643 case RADEON_RB3D_CNTL: 1644 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1645 case 7: 1646 case 8: 1647 case 9: 1648 case 11: 1649 case 12: 1650 track->cb[0].cpp = 1; 1651 break; 1652 case 3: 1653 case 4: 1654 case 15: 1655 track->cb[0].cpp = 2; 1656 break; 1657 case 6: 1658 track->cb[0].cpp = 4; 1659 break; 1660 default: 1661 DRM_ERROR("Invalid color buffer format (%d) !\n", 1662 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1663 return -EINVAL; 1664 } 1665 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1666 track->cb_dirty = true; 1667 track->zb_dirty = true; 1668 break; 1669 case RADEON_RB3D_ZSTENCILCNTL: 1670 switch (idx_value & 0xf) { 1671 case 0: 1672 track->zb.cpp = 2; 1673 break; 1674 case 2: 1675 case 3: 1676 case 4: 1677 case 5: 1678 case 9: 1679 case 11: 1680 track->zb.cpp = 4; 1681 break; 1682 default: 1683 break; 1684 } 1685 track->zb_dirty = true; 1686 break; 1687 case RADEON_RB3D_ZPASS_ADDR: 1688 r = r100_cs_packet_next_reloc(p, &reloc); 1689 if (r) { 1690 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1691 idx, reg); 1692 r100_cs_dump_packet(p, pkt); 1693 return r; 1694 } 1695 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1696 break; 1697 case RADEON_PP_CNTL: 1698 { 1699 uint32_t temp = idx_value >> 4; 1700 for (i = 0; i < track->num_texture; i++) 1701 track->textures[i].enabled = !!(temp & (1 << i)); 1702 track->tex_dirty = true; 1703 } 1704 break; 1705 case RADEON_SE_VF_CNTL: 1706 track->vap_vf_cntl = idx_value; 1707 break; 1708 case RADEON_SE_VTX_FMT: 1709 track->vtx_size = r100_get_vtx_size(idx_value); 1710 break; 1711 case RADEON_PP_TEX_SIZE_0: 1712 case RADEON_PP_TEX_SIZE_1: 1713 case RADEON_PP_TEX_SIZE_2: 1714 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1715 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1716 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1717 track->tex_dirty = true; 1718 break; 1719 case RADEON_PP_TEX_PITCH_0: 1720 case RADEON_PP_TEX_PITCH_1: 1721 case RADEON_PP_TEX_PITCH_2: 1722 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1723 track->textures[i].pitch = idx_value + 32; 1724 track->tex_dirty = true; 1725 break; 1726 case RADEON_PP_TXFILTER_0: 1727 case RADEON_PP_TXFILTER_1: 1728 case RADEON_PP_TXFILTER_2: 1729 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1730 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1731 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1732 tmp = (idx_value >> 23) & 0x7; 1733 if (tmp == 2 || tmp == 6) 1734 track->textures[i].roundup_w = false; 1735 tmp = (idx_value >> 27) & 0x7; 1736 if (tmp == 2 || tmp == 6) 1737 track->textures[i].roundup_h = false; 1738 track->tex_dirty = true; 1739 break; 1740 case RADEON_PP_TXFORMAT_0: 1741 case RADEON_PP_TXFORMAT_1: 1742 case RADEON_PP_TXFORMAT_2: 1743 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1744 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1745 track->textures[i].use_pitch = 1; 1746 } else { 1747 track->textures[i].use_pitch = 0; 1748 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1749 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1750 } 1751 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1752 track->textures[i].tex_coord_type = 2; 1753 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1754 case RADEON_TXFORMAT_I8: 1755 case RADEON_TXFORMAT_RGB332: 1756 case RADEON_TXFORMAT_Y8: 1757 track->textures[i].cpp = 1; 1758 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1759 break; 1760 case RADEON_TXFORMAT_AI88: 1761 case RADEON_TXFORMAT_ARGB1555: 1762 case RADEON_TXFORMAT_RGB565: 1763 case RADEON_TXFORMAT_ARGB4444: 1764 case RADEON_TXFORMAT_VYUY422: 1765 case RADEON_TXFORMAT_YVYU422: 1766 case RADEON_TXFORMAT_SHADOW16: 1767 case RADEON_TXFORMAT_LDUDV655: 1768 case RADEON_TXFORMAT_DUDV88: 1769 track->textures[i].cpp = 2; 1770 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1771 break; 1772 case RADEON_TXFORMAT_ARGB8888: 1773 case RADEON_TXFORMAT_RGBA8888: 1774 case RADEON_TXFORMAT_SHADOW32: 1775 case RADEON_TXFORMAT_LDUDUV8888: 1776 track->textures[i].cpp = 4; 1777 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1778 break; 1779 case RADEON_TXFORMAT_DXT1: 1780 track->textures[i].cpp = 1; 1781 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1782 break; 1783 case RADEON_TXFORMAT_DXT23: 1784 case RADEON_TXFORMAT_DXT45: 1785 track->textures[i].cpp = 1; 1786 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1787 break; 1788 } 1789 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1790 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1791 track->tex_dirty = true; 1792 break; 1793 case RADEON_PP_CUBIC_FACES_0: 1794 case RADEON_PP_CUBIC_FACES_1: 1795 case RADEON_PP_CUBIC_FACES_2: 1796 tmp = idx_value; 1797 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1798 for (face = 0; face < 4; face++) { 1799 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1800 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1801 } 1802 track->tex_dirty = true; 1803 break; 1804 default: 1805 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1806 reg, idx); 1807 return -EINVAL; 1808 } 1809 return 0; 1810} 1811 1812int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1813 struct radeon_cs_packet *pkt, 1814 struct radeon_bo *robj) 1815{ 1816 unsigned idx; 1817 u32 value; 1818 idx = pkt->idx + 1; 1819 value = radeon_get_ib_value(p, idx + 2); 1820 if ((value + 1) > radeon_bo_size(robj)) { 1821 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1822 "(need %u have %lu) !\n", 1823 value + 1, 1824 radeon_bo_size(robj)); 1825 return -EINVAL; 1826 } 1827 return 0; 1828} 1829 1830static int r100_packet3_check(struct radeon_cs_parser *p, 1831 struct radeon_cs_packet *pkt) 1832{ 1833 struct radeon_cs_reloc *reloc; 1834 struct r100_cs_track *track; 1835 unsigned idx; 1836 volatile uint32_t *ib; 1837 int r; 1838 1839 ib = p->ib->ptr; 1840 idx = pkt->idx + 1; 1841 track = (struct r100_cs_track *)p->track; 1842 switch (pkt->opcode) { 1843 case PACKET3_3D_LOAD_VBPNTR: 1844 r = r100_packet3_load_vbpntr(p, pkt, idx); 1845 if (r) 1846 return r; 1847 break; 1848 case PACKET3_INDX_BUFFER: 1849 r = r100_cs_packet_next_reloc(p, &reloc); 1850 if (r) { 1851 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1852 r100_cs_dump_packet(p, pkt); 1853 return r; 1854 } 1855 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1856 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1857 if (r) { 1858 return r; 1859 } 1860 break; 1861 case 0x23: 1862 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1863 r = r100_cs_packet_next_reloc(p, &reloc); 1864 if (r) { 1865 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1866 r100_cs_dump_packet(p, pkt); 1867 return r; 1868 } 1869 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1870 track->num_arrays = 1; 1871 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1872 1873 track->arrays[0].robj = reloc->robj; 1874 track->arrays[0].esize = track->vtx_size; 1875 1876 track->max_indx = radeon_get_ib_value(p, idx+1); 1877 1878 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1879 track->immd_dwords = pkt->count - 1; 1880 r = r100_cs_track_check(p->rdev, track); 1881 if (r) 1882 return r; 1883 break; 1884 case PACKET3_3D_DRAW_IMMD: 1885 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1886 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1887 return -EINVAL; 1888 } 1889 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1890 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1891 track->immd_dwords = pkt->count - 1; 1892 r = r100_cs_track_check(p->rdev, track); 1893 if (r) 1894 return r; 1895 break; 1896 /* triggers drawing using in-packet vertex data */ 1897 case PACKET3_3D_DRAW_IMMD_2: 1898 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1899 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1900 return -EINVAL; 1901 } 1902 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1903 track->immd_dwords = pkt->count; 1904 r = r100_cs_track_check(p->rdev, track); 1905 if (r) 1906 return r; 1907 break; 1908 /* triggers drawing using in-packet vertex data */ 1909 case PACKET3_3D_DRAW_VBUF_2: 1910 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1911 r = r100_cs_track_check(p->rdev, track); 1912 if (r) 1913 return r; 1914 break; 1915 /* triggers drawing of vertex buffers setup elsewhere */ 1916 case PACKET3_3D_DRAW_INDX_2: 1917 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1918 r = r100_cs_track_check(p->rdev, track); 1919 if (r) 1920 return r; 1921 break; 1922 /* triggers drawing using indices to vertex buffer */ 1923 case PACKET3_3D_DRAW_VBUF: 1924 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1925 r = r100_cs_track_check(p->rdev, track); 1926 if (r) 1927 return r; 1928 break; 1929 /* triggers drawing of vertex buffers setup elsewhere */ 1930 case PACKET3_3D_DRAW_INDX: 1931 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1932 r = r100_cs_track_check(p->rdev, track); 1933 if (r) 1934 return r; 1935 break; 1936 /* triggers drawing using indices to vertex buffer */ 1937 case PACKET3_3D_CLEAR_HIZ: 1938 case PACKET3_3D_CLEAR_ZMASK: 1939 if (p->rdev->hyperz_filp != p->filp) 1940 return -EINVAL; 1941 break; 1942 case PACKET3_NOP: 1943 break; 1944 default: 1945 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1946 return -EINVAL; 1947 } 1948 return 0; 1949} 1950 1951int r100_cs_parse(struct radeon_cs_parser *p) 1952{ 1953 struct radeon_cs_packet pkt; 1954 struct r100_cs_track *track; 1955 int r; 1956 1957 track = kzalloc(sizeof(*track), GFP_KERNEL); 1958 r100_cs_track_clear(p->rdev, track); 1959 p->track = track; 1960 do { 1961 r = r100_cs_packet_parse(p, &pkt, p->idx); 1962 if (r) { 1963 return r; 1964 } 1965 p->idx += pkt.count + 2; 1966 switch (pkt.type) { 1967 case PACKET_TYPE0: 1968 if (p->rdev->family >= CHIP_R200) 1969 r = r100_cs_parse_packet0(p, &pkt, 1970 p->rdev->config.r100.reg_safe_bm, 1971 p->rdev->config.r100.reg_safe_bm_size, 1972 &r200_packet0_check); 1973 else 1974 r = r100_cs_parse_packet0(p, &pkt, 1975 p->rdev->config.r100.reg_safe_bm, 1976 p->rdev->config.r100.reg_safe_bm_size, 1977 &r100_packet0_check); 1978 break; 1979 case PACKET_TYPE2: 1980 break; 1981 case PACKET_TYPE3: 1982 r = r100_packet3_check(p, &pkt); 1983 break; 1984 default: 1985 DRM_ERROR("Unknown packet type %d !\n", 1986 pkt.type); 1987 return -EINVAL; 1988 } 1989 if (r) { 1990 return r; 1991 } 1992 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1993 return 0; 1994} 1995 1996 1997/* 1998 * Global GPU functions 1999 */ 2000void r100_errata(struct radeon_device *rdev) 2001{ 2002 rdev->pll_errata = 0; 2003 2004 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2005 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2006 } 2007 2008 if (rdev->family == CHIP_RV100 || 2009 rdev->family == CHIP_RS100 || 2010 rdev->family == CHIP_RS200) { 2011 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2012 } 2013} 2014 2015/* Wait for vertical sync on primary CRTC */ 2016void r100_gpu_wait_for_vsync(struct radeon_device *rdev) 2017{ 2018 uint32_t crtc_gen_cntl, tmp; 2019 int i; 2020 2021 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 2022 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 2023 !(crtc_gen_cntl & RADEON_CRTC_EN)) { 2024 return; 2025 } 2026 /* Clear the CRTC_VBLANK_SAVE bit */ 2027 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 2028 for (i = 0; i < rdev->usec_timeout; i++) { 2029 tmp = RREG32(RADEON_CRTC_STATUS); 2030 if (tmp & RADEON_CRTC_VBLANK_SAVE) { 2031 return; 2032 } 2033 DRM_UDELAY(1); 2034 } 2035} 2036 2037/* Wait for vertical sync on secondary CRTC */ 2038void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) 2039{ 2040 uint32_t crtc2_gen_cntl, tmp; 2041 int i; 2042 2043 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 2044 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 2045 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 2046 return; 2047 2048 /* Clear the CRTC_VBLANK_SAVE bit */ 2049 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 2050 for (i = 0; i < rdev->usec_timeout; i++) { 2051 tmp = RREG32(RADEON_CRTC2_STATUS); 2052 if (tmp & RADEON_CRTC2_VBLANK_SAVE) { 2053 return; 2054 } 2055 DRM_UDELAY(1); 2056 } 2057} 2058 2059int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2060{ 2061 unsigned i; 2062 uint32_t tmp; 2063 2064 for (i = 0; i < rdev->usec_timeout; i++) { 2065 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2066 if (tmp >= n) { 2067 return 0; 2068 } 2069 DRM_UDELAY(1); 2070 } 2071 return -1; 2072} 2073 2074int r100_gui_wait_for_idle(struct radeon_device *rdev) 2075{ 2076 unsigned i; 2077 uint32_t tmp; 2078 2079 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2080 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2081 " Bad things might happen.\n"); 2082 } 2083 for (i = 0; i < rdev->usec_timeout; i++) { 2084 tmp = RREG32(RADEON_RBBM_STATUS); 2085 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2086 return 0; 2087 } 2088 DRM_UDELAY(1); 2089 } 2090 return -1; 2091} 2092 2093int r100_mc_wait_for_idle(struct radeon_device *rdev) 2094{ 2095 unsigned i; 2096 uint32_t tmp; 2097 2098 for (i = 0; i < rdev->usec_timeout; i++) { 2099 /* read MC_STATUS */ 2100 tmp = RREG32(RADEON_MC_STATUS); 2101 if (tmp & RADEON_MC_IDLE) { 2102 return 0; 2103 } 2104 DRM_UDELAY(1); 2105 } 2106 return -1; 2107} 2108 2109void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_ring *ring) 2110{ 2111 lockup->last_cp_rptr = ring->rptr; 2112 lockup->last_jiffies = jiffies; 2113} 2114 2115/** 2116 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information 2117 * @rdev: radeon device structure 2118 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations 2119 * @cp: radeon_cp structure holding CP information 2120 * 2121 * We don't need to initialize the lockup tracking information as we will either 2122 * have CP rptr to a different value of jiffies wrap around which will force 2123 * initialization of the lockup tracking informations. 2124 * 2125 * A possible false positivie is if we get call after while and last_cp_rptr == 2126 * the current CP rptr, even if it's unlikely it might happen. To avoid this 2127 * if the elapsed time since last call is bigger than 2 second than we return 2128 * false and update the tracking information. Due to this the caller must call 2129 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported 2130 * the fencing code should be cautious about that. 2131 * 2132 * Caller should write to the ring to force CP to do something so we don't get 2133 * false positive when CP is just gived nothing to do. 2134 * 2135 **/ 2136bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_ring *ring) 2137{ 2138 unsigned long cjiffies, elapsed; 2139 2140 cjiffies = jiffies; 2141 if (!time_after(cjiffies, lockup->last_jiffies)) { 2142 /* likely a wrap around */ 2143 lockup->last_cp_rptr = ring->rptr; 2144 lockup->last_jiffies = jiffies; 2145 return false; 2146 } 2147 if (ring->rptr != lockup->last_cp_rptr) { 2148 /* CP is still working no lockup */ 2149 lockup->last_cp_rptr = ring->rptr; 2150 lockup->last_jiffies = jiffies; 2151 return false; 2152 } 2153 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); 2154 if (elapsed >= 10000) { 2155 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 2156 return true; 2157 } 2158 /* give a chance to the GPU ... */ 2159 return false; 2160} 2161 2162bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2163{ 2164 u32 rbbm_status; 2165 int r; 2166 2167 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2168 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2169 r100_gpu_lockup_update(&rdev->config.r100.lockup, ring); 2170 return false; 2171 } 2172 /* force CP activities */ 2173 r = radeon_ring_lock(rdev, ring, 2); 2174 if (!r) { 2175 /* PACKET2 NOP */ 2176 radeon_ring_write(ring, 0x80000000); 2177 radeon_ring_write(ring, 0x80000000); 2178 radeon_ring_unlock_commit(rdev, ring); 2179 } 2180 ring->rptr = RREG32(ring->rptr_reg); 2181 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, ring); 2182} 2183 2184void r100_bm_disable(struct radeon_device *rdev) 2185{ 2186 u32 tmp; 2187 2188 /* disable bus mastering */ 2189 tmp = RREG32(R_000030_BUS_CNTL); 2190 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2191 mdelay(1); 2192 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2193 mdelay(1); 2194 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2195 tmp = RREG32(RADEON_BUS_CNTL); 2196 mdelay(1); 2197 pci_clear_master(rdev->pdev); 2198 mdelay(1); 2199} 2200 2201int r100_asic_reset(struct radeon_device *rdev) 2202{ 2203 struct r100_mc_save save; 2204 u32 status, tmp; 2205 int ret = 0; 2206 2207 status = RREG32(R_000E40_RBBM_STATUS); 2208 if (!G_000E40_GUI_ACTIVE(status)) { 2209 return 0; 2210 } 2211 r100_mc_stop(rdev, &save); 2212 status = RREG32(R_000E40_RBBM_STATUS); 2213 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2214 /* stop CP */ 2215 WREG32(RADEON_CP_CSQ_CNTL, 0); 2216 tmp = RREG32(RADEON_CP_RB_CNTL); 2217 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2218 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2219 WREG32(RADEON_CP_RB_WPTR, 0); 2220 WREG32(RADEON_CP_RB_CNTL, tmp); 2221 /* save PCI state */ 2222 pci_save_state(rdev->pdev); 2223 /* disable bus mastering */ 2224 r100_bm_disable(rdev); 2225 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2226 S_0000F0_SOFT_RESET_RE(1) | 2227 S_0000F0_SOFT_RESET_PP(1) | 2228 S_0000F0_SOFT_RESET_RB(1)); 2229 RREG32(R_0000F0_RBBM_SOFT_RESET); 2230 mdelay(500); 2231 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2232 mdelay(1); 2233 status = RREG32(R_000E40_RBBM_STATUS); 2234 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2235 /* reset CP */ 2236 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2237 RREG32(R_0000F0_RBBM_SOFT_RESET); 2238 mdelay(500); 2239 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2240 mdelay(1); 2241 status = RREG32(R_000E40_RBBM_STATUS); 2242 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2243 /* restore PCI & busmastering */ 2244 pci_restore_state(rdev->pdev); 2245 r100_enable_bm(rdev); 2246 /* Check if GPU is idle */ 2247 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2248 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2249 dev_err(rdev->dev, "failed to reset GPU\n"); 2250 rdev->gpu_lockup = true; 2251 ret = -1; 2252 } else 2253 dev_info(rdev->dev, "GPU reset succeed\n"); 2254 r100_mc_resume(rdev, &save); 2255 return ret; 2256} 2257 2258void r100_set_common_regs(struct radeon_device *rdev) 2259{ 2260 struct drm_device *dev = rdev->ddev; 2261 bool force_dac2 = false; 2262 u32 tmp; 2263 2264 /* set these so they don't interfere with anything */ 2265 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2266 WREG32(RADEON_SUBPIC_CNTL, 0); 2267 WREG32(RADEON_VIPH_CONTROL, 0); 2268 WREG32(RADEON_I2C_CNTL_1, 0); 2269 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2270 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2271 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2272 2273 /* always set up dac2 on rn50 and some rv100 as lots 2274 * of servers seem to wire it up to a VGA port but 2275 * don't report it in the bios connector 2276 * table. 2277 */ 2278 switch (dev->pdev->device) { 2279 /* RN50 */ 2280 case 0x515e: 2281 case 0x5969: 2282 force_dac2 = true; 2283 break; 2284 /* RV100*/ 2285 case 0x5159: 2286 case 0x515a: 2287 /* DELL triple head servers */ 2288 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2289 ((dev->pdev->subsystem_device == 0x016c) || 2290 (dev->pdev->subsystem_device == 0x016d) || 2291 (dev->pdev->subsystem_device == 0x016e) || 2292 (dev->pdev->subsystem_device == 0x016f) || 2293 (dev->pdev->subsystem_device == 0x0170) || 2294 (dev->pdev->subsystem_device == 0x017d) || 2295 (dev->pdev->subsystem_device == 0x017e) || 2296 (dev->pdev->subsystem_device == 0x0183) || 2297 (dev->pdev->subsystem_device == 0x018a) || 2298 (dev->pdev->subsystem_device == 0x019a))) 2299 force_dac2 = true; 2300 break; 2301 } 2302 2303 if (force_dac2) { 2304 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2305 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2306 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2307 2308 /* For CRT on DAC2, don't turn it on if BIOS didn't 2309 enable it, even it's detected. 2310 */ 2311 2312 /* force it to crtc0 */ 2313 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2314 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2315 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2316 2317 /* set up the TV DAC */ 2318 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2319 RADEON_TV_DAC_STD_MASK | 2320 RADEON_TV_DAC_RDACPD | 2321 RADEON_TV_DAC_GDACPD | 2322 RADEON_TV_DAC_BDACPD | 2323 RADEON_TV_DAC_BGADJ_MASK | 2324 RADEON_TV_DAC_DACADJ_MASK); 2325 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2326 RADEON_TV_DAC_NHOLD | 2327 RADEON_TV_DAC_STD_PS2 | 2328 (0x58 << 16)); 2329 2330 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2331 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2332 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2333 } 2334 2335 /* switch PM block to ACPI mode */ 2336 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2337 tmp &= ~RADEON_PM_MODE_SEL; 2338 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2339 2340} 2341 2342/* 2343 * VRAM info 2344 */ 2345static void r100_vram_get_type(struct radeon_device *rdev) 2346{ 2347 uint32_t tmp; 2348 2349 rdev->mc.vram_is_ddr = false; 2350 if (rdev->flags & RADEON_IS_IGP) 2351 rdev->mc.vram_is_ddr = true; 2352 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2353 rdev->mc.vram_is_ddr = true; 2354 if ((rdev->family == CHIP_RV100) || 2355 (rdev->family == CHIP_RS100) || 2356 (rdev->family == CHIP_RS200)) { 2357 tmp = RREG32(RADEON_MEM_CNTL); 2358 if (tmp & RV100_HALF_MODE) { 2359 rdev->mc.vram_width = 32; 2360 } else { 2361 rdev->mc.vram_width = 64; 2362 } 2363 if (rdev->flags & RADEON_SINGLE_CRTC) { 2364 rdev->mc.vram_width /= 4; 2365 rdev->mc.vram_is_ddr = true; 2366 } 2367 } else if (rdev->family <= CHIP_RV280) { 2368 tmp = RREG32(RADEON_MEM_CNTL); 2369 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2370 rdev->mc.vram_width = 128; 2371 } else { 2372 rdev->mc.vram_width = 64; 2373 } 2374 } else { 2375 /* newer IGPs */ 2376 rdev->mc.vram_width = 128; 2377 } 2378} 2379 2380static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2381{ 2382 u32 aper_size; 2383 u8 byte; 2384 2385 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2386 2387 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2388 * that is has the 2nd generation multifunction PCI interface 2389 */ 2390 if (rdev->family == CHIP_RV280 || 2391 rdev->family >= CHIP_RV350) { 2392 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2393 ~RADEON_HDP_APER_CNTL); 2394 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2395 return aper_size * 2; 2396 } 2397 2398 /* Older cards have all sorts of funny issues to deal with. First 2399 * check if it's a multifunction card by reading the PCI config 2400 * header type... Limit those to one aperture size 2401 */ 2402 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2403 if (byte & 0x80) { 2404 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2405 DRM_INFO("Limiting VRAM to one aperture\n"); 2406 return aper_size; 2407 } 2408 2409 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2410 * have set it up. We don't write this as it's broken on some ASICs but 2411 * we expect the BIOS to have done the right thing (might be too optimistic...) 2412 */ 2413 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2414 return aper_size * 2; 2415 return aper_size; 2416} 2417 2418void r100_vram_init_sizes(struct radeon_device *rdev) 2419{ 2420 u64 config_aper_size; 2421 2422 /* work out accessible VRAM */ 2423 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2424 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2425 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2426 /* FIXME we don't use the second aperture yet when we could use it */ 2427 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2428 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2429 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2430 if (rdev->flags & RADEON_IS_IGP) { 2431 uint32_t tom; 2432 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2433 tom = RREG32(RADEON_NB_TOM); 2434 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2435 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2436 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2437 } else { 2438 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2439 /* Some production boards of m6 will report 0 2440 * if it's 8 MB 2441 */ 2442 if (rdev->mc.real_vram_size == 0) { 2443 rdev->mc.real_vram_size = 8192 * 1024; 2444 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2445 } 2446 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2447 * Novell bug 204882 + along with lots of ubuntu ones 2448 */ 2449 if (rdev->mc.aper_size > config_aper_size) 2450 config_aper_size = rdev->mc.aper_size; 2451 2452 if (config_aper_size > rdev->mc.real_vram_size) 2453 rdev->mc.mc_vram_size = config_aper_size; 2454 else 2455 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2456 } 2457} 2458 2459void r100_vga_set_state(struct radeon_device *rdev, bool state) 2460{ 2461 uint32_t temp; 2462 2463 temp = RREG32(RADEON_CONFIG_CNTL); 2464 if (state == false) { 2465 temp &= ~RADEON_CFG_VGA_RAM_EN; 2466 temp |= RADEON_CFG_VGA_IO_DIS; 2467 } else { 2468 temp &= ~RADEON_CFG_VGA_IO_DIS; 2469 } 2470 WREG32(RADEON_CONFIG_CNTL, temp); 2471} 2472 2473void r100_mc_init(struct radeon_device *rdev) 2474{ 2475 u64 base; 2476 2477 r100_vram_get_type(rdev); 2478 r100_vram_init_sizes(rdev); 2479 base = rdev->mc.aper_base; 2480 if (rdev->flags & RADEON_IS_IGP) 2481 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2482 radeon_vram_location(rdev, &rdev->mc, base); 2483 rdev->mc.gtt_base_align = 0; 2484 if (!(rdev->flags & RADEON_IS_AGP)) 2485 radeon_gtt_location(rdev, &rdev->mc); 2486 radeon_update_bandwidth_info(rdev); 2487} 2488 2489 2490/* 2491 * Indirect registers accessor 2492 */ 2493void r100_pll_errata_after_index(struct radeon_device *rdev) 2494{ 2495 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2496 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2497 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2498 } 2499} 2500 2501static void r100_pll_errata_after_data(struct radeon_device *rdev) 2502{ 2503 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2504 * or the chip could hang on a subsequent access 2505 */ 2506 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2507 udelay(5000); 2508 } 2509 2510 /* This function is required to workaround a hardware bug in some (all?) 2511 * revisions of the R300. This workaround should be called after every 2512 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2513 * may not be correct. 2514 */ 2515 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2516 uint32_t save, tmp; 2517 2518 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2519 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2520 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2521 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2522 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2523 } 2524} 2525 2526uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2527{ 2528 uint32_t data; 2529 2530 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2531 r100_pll_errata_after_index(rdev); 2532 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2533 r100_pll_errata_after_data(rdev); 2534 return data; 2535} 2536 2537void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2538{ 2539 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2540 r100_pll_errata_after_index(rdev); 2541 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2542 r100_pll_errata_after_data(rdev); 2543} 2544 2545void r100_set_safe_registers(struct radeon_device *rdev) 2546{ 2547 if (ASIC_IS_RN50(rdev)) { 2548 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2549 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2550 } else if (rdev->family < CHIP_R200) { 2551 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2552 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2553 } else { 2554 r200_set_safe_registers(rdev); 2555 } 2556} 2557 2558/* 2559 * Debugfs info 2560 */ 2561#if defined(CONFIG_DEBUG_FS) 2562static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2563{ 2564 struct drm_info_node *node = (struct drm_info_node *) m->private; 2565 struct drm_device *dev = node->minor->dev; 2566 struct radeon_device *rdev = dev->dev_private; 2567 uint32_t reg, value; 2568 unsigned i; 2569 2570 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2571 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2572 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2573 for (i = 0; i < 64; i++) { 2574 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2575 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2576 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2577 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2578 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2579 } 2580 return 0; 2581} 2582 2583static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2584{ 2585 struct drm_info_node *node = (struct drm_info_node *) m->private; 2586 struct drm_device *dev = node->minor->dev; 2587 struct radeon_device *rdev = dev->dev_private; 2588 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2589 uint32_t rdp, wdp; 2590 unsigned count, i, j; 2591 2592 radeon_ring_free_size(rdev, ring); 2593 rdp = RREG32(RADEON_CP_RB_RPTR); 2594 wdp = RREG32(RADEON_CP_RB_WPTR); 2595 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2596 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2597 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2598 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2599 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2600 seq_printf(m, "%u dwords in ring\n", count); 2601 for (j = 0; j <= count; j++) { 2602 i = (rdp + j) & ring->ptr_mask; 2603 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2604 } 2605 return 0; 2606} 2607 2608 2609static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2610{ 2611 struct drm_info_node *node = (struct drm_info_node *) m->private; 2612 struct drm_device *dev = node->minor->dev; 2613 struct radeon_device *rdev = dev->dev_private; 2614 uint32_t csq_stat, csq2_stat, tmp; 2615 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2616 unsigned i; 2617 2618 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2619 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2620 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2621 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2622 r_rptr = (csq_stat >> 0) & 0x3ff; 2623 r_wptr = (csq_stat >> 10) & 0x3ff; 2624 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2625 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2626 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2627 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2628 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2629 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2630 seq_printf(m, "Ring rptr %u\n", r_rptr); 2631 seq_printf(m, "Ring wptr %u\n", r_wptr); 2632 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2633 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2634 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2635 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2636 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2637 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2638 seq_printf(m, "Ring fifo:\n"); 2639 for (i = 0; i < 256; i++) { 2640 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2641 tmp = RREG32(RADEON_CP_CSQ_DATA); 2642 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2643 } 2644 seq_printf(m, "Indirect1 fifo:\n"); 2645 for (i = 256; i <= 512; i++) { 2646 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2647 tmp = RREG32(RADEON_CP_CSQ_DATA); 2648 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2649 } 2650 seq_printf(m, "Indirect2 fifo:\n"); 2651 for (i = 640; i < ib1_wptr; i++) { 2652 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2653 tmp = RREG32(RADEON_CP_CSQ_DATA); 2654 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2655 } 2656 return 0; 2657} 2658 2659static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2660{ 2661 struct drm_info_node *node = (struct drm_info_node *) m->private; 2662 struct drm_device *dev = node->minor->dev; 2663 struct radeon_device *rdev = dev->dev_private; 2664 uint32_t tmp; 2665 2666 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2667 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2668 tmp = RREG32(RADEON_MC_FB_LOCATION); 2669 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2670 tmp = RREG32(RADEON_BUS_CNTL); 2671 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2672 tmp = RREG32(RADEON_MC_AGP_LOCATION); 2673 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2674 tmp = RREG32(RADEON_AGP_BASE); 2675 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2676 tmp = RREG32(RADEON_HOST_PATH_CNTL); 2677 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2678 tmp = RREG32(0x01D0); 2679 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2680 tmp = RREG32(RADEON_AIC_LO_ADDR); 2681 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2682 tmp = RREG32(RADEON_AIC_HI_ADDR); 2683 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 2684 tmp = RREG32(0x01E4); 2685 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 2686 return 0; 2687} 2688 2689static struct drm_info_list r100_debugfs_rbbm_list[] = { 2690 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 2691}; 2692 2693static struct drm_info_list r100_debugfs_cp_list[] = { 2694 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 2695 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 2696}; 2697 2698static struct drm_info_list r100_debugfs_mc_info_list[] = { 2699 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 2700}; 2701#endif 2702 2703int r100_debugfs_rbbm_init(struct radeon_device *rdev) 2704{ 2705#if defined(CONFIG_DEBUG_FS) 2706 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 2707#else 2708 return 0; 2709#endif 2710} 2711 2712int r100_debugfs_cp_init(struct radeon_device *rdev) 2713{ 2714#if defined(CONFIG_DEBUG_FS) 2715 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 2716#else 2717 return 0; 2718#endif 2719} 2720 2721int r100_debugfs_mc_info_init(struct radeon_device *rdev) 2722{ 2723#if defined(CONFIG_DEBUG_FS) 2724 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 2725#else 2726 return 0; 2727#endif 2728} 2729 2730int r100_set_surface_reg(struct radeon_device *rdev, int reg, 2731 uint32_t tiling_flags, uint32_t pitch, 2732 uint32_t offset, uint32_t obj_size) 2733{ 2734 int surf_index = reg * 16; 2735 int flags = 0; 2736 2737 if (rdev->family <= CHIP_RS200) { 2738 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2739 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2740 flags |= RADEON_SURF_TILE_COLOR_BOTH; 2741 if (tiling_flags & RADEON_TILING_MACRO) 2742 flags |= RADEON_SURF_TILE_COLOR_MACRO; 2743 } else if (rdev->family <= CHIP_RV280) { 2744 if (tiling_flags & (RADEON_TILING_MACRO)) 2745 flags |= R200_SURF_TILE_COLOR_MACRO; 2746 if (tiling_flags & RADEON_TILING_MICRO) 2747 flags |= R200_SURF_TILE_COLOR_MICRO; 2748 } else { 2749 if (tiling_flags & RADEON_TILING_MACRO) 2750 flags |= R300_SURF_TILE_MACRO; 2751 if (tiling_flags & RADEON_TILING_MICRO) 2752 flags |= R300_SURF_TILE_MICRO; 2753 } 2754 2755 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 2756 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 2757 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 2758 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 2759 2760 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ 2761 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { 2762 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) 2763 if (ASIC_IS_RN50(rdev)) 2764 pitch /= 16; 2765 } 2766 2767 /* r100/r200 divide by 16 */ 2768 if (rdev->family < CHIP_R300) 2769 flags |= pitch / 16; 2770 else 2771 flags |= pitch / 8; 2772 2773 2774 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2775 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2776 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2777 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2778 return 0; 2779} 2780 2781void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 2782{ 2783 int surf_index = reg * 16; 2784 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 2785} 2786 2787void r100_bandwidth_update(struct radeon_device *rdev) 2788{ 2789 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 2790 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 2791 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 2792 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 2793 fixed20_12 memtcas_ff[8] = { 2794 dfixed_init(1), 2795 dfixed_init(2), 2796 dfixed_init(3), 2797 dfixed_init(0), 2798 dfixed_init_half(1), 2799 dfixed_init_half(2), 2800 dfixed_init(0), 2801 }; 2802 fixed20_12 memtcas_rs480_ff[8] = { 2803 dfixed_init(0), 2804 dfixed_init(1), 2805 dfixed_init(2), 2806 dfixed_init(3), 2807 dfixed_init(0), 2808 dfixed_init_half(1), 2809 dfixed_init_half(2), 2810 dfixed_init_half(3), 2811 }; 2812 fixed20_12 memtcas2_ff[8] = { 2813 dfixed_init(0), 2814 dfixed_init(1), 2815 dfixed_init(2), 2816 dfixed_init(3), 2817 dfixed_init(4), 2818 dfixed_init(5), 2819 dfixed_init(6), 2820 dfixed_init(7), 2821 }; 2822 fixed20_12 memtrbs[8] = { 2823 dfixed_init(1), 2824 dfixed_init_half(1), 2825 dfixed_init(2), 2826 dfixed_init_half(2), 2827 dfixed_init(3), 2828 dfixed_init_half(3), 2829 dfixed_init(4), 2830 dfixed_init_half(4) 2831 }; 2832 fixed20_12 memtrbs_r4xx[8] = { 2833 dfixed_init(4), 2834 dfixed_init(5), 2835 dfixed_init(6), 2836 dfixed_init(7), 2837 dfixed_init(8), 2838 dfixed_init(9), 2839 dfixed_init(10), 2840 dfixed_init(11) 2841 }; 2842 fixed20_12 min_mem_eff; 2843 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 2844 fixed20_12 cur_latency_mclk, cur_latency_sclk; 2845 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 2846 disp_drain_rate2, read_return_rate; 2847 fixed20_12 time_disp1_drop_priority; 2848 int c; 2849 int cur_size = 16; /* in octawords */ 2850 int critical_point = 0, critical_point2; 2851/* uint32_t read_return_rate, time_disp1_drop_priority; */ 2852 int stop_req, max_stop_req; 2853 struct drm_display_mode *mode1 = NULL; 2854 struct drm_display_mode *mode2 = NULL; 2855 uint32_t pixel_bytes1 = 0; 2856 uint32_t pixel_bytes2 = 0; 2857 2858 radeon_update_display_priority(rdev); 2859 2860 if (rdev->mode_info.crtcs[0]->base.enabled) { 2861 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2862 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2863 } 2864 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 2865 if (rdev->mode_info.crtcs[1]->base.enabled) { 2866 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 2867 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 2868 } 2869 } 2870 2871 min_mem_eff.full = dfixed_const_8(0); 2872 /* get modes */ 2873 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 2874 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 2875 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 2876 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 2877 /* check crtc enables */ 2878 if (mode2) 2879 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 2880 if (mode1) 2881 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 2882 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 2883 } 2884 2885 /* 2886 * determine is there is enough bw for current mode 2887 */ 2888 sclk_ff = rdev->pm.sclk; 2889 mclk_ff = rdev->pm.mclk; 2890 2891 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2892 temp_ff.full = dfixed_const(temp); 2893 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 2894 2895 pix_clk.full = 0; 2896 pix_clk2.full = 0; 2897 peak_disp_bw.full = 0; 2898 if (mode1) { 2899 temp_ff.full = dfixed_const(1000); 2900 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 2901 pix_clk.full = dfixed_div(pix_clk, temp_ff); 2902 temp_ff.full = dfixed_const(pixel_bytes1); 2903 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 2904 } 2905 if (mode2) { 2906 temp_ff.full = dfixed_const(1000); 2907 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 2908 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 2909 temp_ff.full = dfixed_const(pixel_bytes2); 2910 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 2911 } 2912 2913 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 2914 if (peak_disp_bw.full >= mem_bw.full) { 2915 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 2916 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 2917 } 2918 2919 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 2920 temp = RREG32(RADEON_MEM_TIMING_CNTL); 2921 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 2922 mem_trcd = ((temp >> 2) & 0x3) + 1; 2923 mem_trp = ((temp & 0x3)) + 1; 2924 mem_tras = ((temp & 0x70) >> 4) + 1; 2925 } else if (rdev->family == CHIP_R300 || 2926 rdev->family == CHIP_R350) { /* r300, r350 */ 2927 mem_trcd = (temp & 0x7) + 1; 2928 mem_trp = ((temp >> 8) & 0x7) + 1; 2929 mem_tras = ((temp >> 11) & 0xf) + 4; 2930 } else if (rdev->family == CHIP_RV350 || 2931 rdev->family <= CHIP_RV380) { 2932 /* rv3x0 */ 2933 mem_trcd = (temp & 0x7) + 3; 2934 mem_trp = ((temp >> 8) & 0x7) + 3; 2935 mem_tras = ((temp >> 11) & 0xf) + 6; 2936 } else if (rdev->family == CHIP_R420 || 2937 rdev->family == CHIP_R423 || 2938 rdev->family == CHIP_RV410) { 2939 /* r4xx */ 2940 mem_trcd = (temp & 0xf) + 3; 2941 if (mem_trcd > 15) 2942 mem_trcd = 15; 2943 mem_trp = ((temp >> 8) & 0xf) + 3; 2944 if (mem_trp > 15) 2945 mem_trp = 15; 2946 mem_tras = ((temp >> 12) & 0x1f) + 6; 2947 if (mem_tras > 31) 2948 mem_tras = 31; 2949 } else { /* RV200, R200 */ 2950 mem_trcd = (temp & 0x7) + 1; 2951 mem_trp = ((temp >> 8) & 0x7) + 1; 2952 mem_tras = ((temp >> 12) & 0xf) + 4; 2953 } 2954 /* convert to FF */ 2955 trcd_ff.full = dfixed_const(mem_trcd); 2956 trp_ff.full = dfixed_const(mem_trp); 2957 tras_ff.full = dfixed_const(mem_tras); 2958 2959 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 2960 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2961 data = (temp & (7 << 20)) >> 20; 2962 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 2963 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 2964 tcas_ff = memtcas_rs480_ff[data]; 2965 else 2966 tcas_ff = memtcas_ff[data]; 2967 } else 2968 tcas_ff = memtcas2_ff[data]; 2969 2970 if (rdev->family == CHIP_RS400 || 2971 rdev->family == CHIP_RS480) { 2972 /* extra cas latency stored in bits 23-25 0-4 clocks */ 2973 data = (temp >> 23) & 0x7; 2974 if (data < 5) 2975 tcas_ff.full += dfixed_const(data); 2976 } 2977 2978 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2979 /* on the R300, Tcas is included in Trbs. 2980 */ 2981 temp = RREG32(RADEON_MEM_CNTL); 2982 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 2983 if (data == 1) { 2984 if (R300_MEM_USE_CD_CH_ONLY & temp) { 2985 temp = RREG32(R300_MC_IND_INDEX); 2986 temp &= ~R300_MC_IND_ADDR_MASK; 2987 temp |= R300_MC_READ_CNTL_CD_mcind; 2988 WREG32(R300_MC_IND_INDEX, temp); 2989 temp = RREG32(R300_MC_IND_DATA); 2990 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 2991 } else { 2992 temp = RREG32(R300_MC_READ_CNTL_AB); 2993 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2994 } 2995 } else { 2996 temp = RREG32(R300_MC_READ_CNTL_AB); 2997 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2998 } 2999 if (rdev->family == CHIP_RV410 || 3000 rdev->family == CHIP_R420 || 3001 rdev->family == CHIP_R423) 3002 trbs_ff = memtrbs_r4xx[data]; 3003 else 3004 trbs_ff = memtrbs[data]; 3005 tcas_ff.full += trbs_ff.full; 3006 } 3007 3008 sclk_eff_ff.full = sclk_ff.full; 3009 3010 if (rdev->flags & RADEON_IS_AGP) { 3011 fixed20_12 agpmode_ff; 3012 agpmode_ff.full = dfixed_const(radeon_agpmode); 3013 temp_ff.full = dfixed_const_666(16); 3014 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3015 } 3016 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3017 3018 if (ASIC_IS_R300(rdev)) { 3019 sclk_delay_ff.full = dfixed_const(250); 3020 } else { 3021 if ((rdev->family == CHIP_RV100) || 3022 rdev->flags & RADEON_IS_IGP) { 3023 if (rdev->mc.vram_is_ddr) 3024 sclk_delay_ff.full = dfixed_const(41); 3025 else 3026 sclk_delay_ff.full = dfixed_const(33); 3027 } else { 3028 if (rdev->mc.vram_width == 128) 3029 sclk_delay_ff.full = dfixed_const(57); 3030 else 3031 sclk_delay_ff.full = dfixed_const(41); 3032 } 3033 } 3034 3035 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3036 3037 if (rdev->mc.vram_is_ddr) { 3038 if (rdev->mc.vram_width == 32) { 3039 k1.full = dfixed_const(40); 3040 c = 3; 3041 } else { 3042 k1.full = dfixed_const(20); 3043 c = 1; 3044 } 3045 } else { 3046 k1.full = dfixed_const(40); 3047 c = 3; 3048 } 3049 3050 temp_ff.full = dfixed_const(2); 3051 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3052 temp_ff.full = dfixed_const(c); 3053 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3054 temp_ff.full = dfixed_const(4); 3055 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3056 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3057 mc_latency_mclk.full += k1.full; 3058 3059 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3060 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3061 3062 /* 3063 HW cursor time assuming worst case of full size colour cursor. 3064 */ 3065 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3066 temp_ff.full += trcd_ff.full; 3067 if (temp_ff.full < tras_ff.full) 3068 temp_ff.full = tras_ff.full; 3069 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3070 3071 temp_ff.full = dfixed_const(cur_size); 3072 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3073 /* 3074 Find the total latency for the display data. 3075 */ 3076 disp_latency_overhead.full = dfixed_const(8); 3077 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3078 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3079 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3080 3081 if (mc_latency_mclk.full > mc_latency_sclk.full) 3082 disp_latency.full = mc_latency_mclk.full; 3083 else 3084 disp_latency.full = mc_latency_sclk.full; 3085 3086 /* setup Max GRPH_STOP_REQ default value */ 3087 if (ASIC_IS_RV100(rdev)) 3088 max_stop_req = 0x5c; 3089 else 3090 max_stop_req = 0x7c; 3091 3092 if (mode1) { 3093 /* CRTC1 3094 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3095 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3096 */ 3097 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3098 3099 if (stop_req > max_stop_req) 3100 stop_req = max_stop_req; 3101 3102 /* 3103 Find the drain rate of the display buffer. 3104 */ 3105 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3106 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3107 3108 /* 3109 Find the critical point of the display buffer. 3110 */ 3111 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3112 crit_point_ff.full += dfixed_const_half(0); 3113 3114 critical_point = dfixed_trunc(crit_point_ff); 3115 3116 if (rdev->disp_priority == 2) { 3117 critical_point = 0; 3118 } 3119 3120 /* 3121 The critical point should never be above max_stop_req-4. Setting 3122 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3123 */ 3124 if (max_stop_req - critical_point < 4) 3125 critical_point = 0; 3126 3127 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3128 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3129 critical_point = 0x10; 3130 } 3131 3132 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3133 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3134 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3135 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3136 if ((rdev->family == CHIP_R350) && 3137 (stop_req > 0x15)) { 3138 stop_req -= 0x10; 3139 } 3140 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3141 temp |= RADEON_GRPH_BUFFER_SIZE; 3142 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3143 RADEON_GRPH_CRITICAL_AT_SOF | 3144 RADEON_GRPH_STOP_CNTL); 3145 /* 3146 Write the result into the register. 3147 */ 3148 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3149 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3150 3151#if 0 3152 if ((rdev->family == CHIP_RS400) || 3153 (rdev->family == CHIP_RS480)) { 3154 /* attempt to program RS400 disp regs correctly ??? */ 3155 temp = RREG32(RS400_DISP1_REG_CNTL); 3156 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3157 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3158 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3159 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3160 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3161 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3162 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3163 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3164 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3165 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3166 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3167 } 3168#endif 3169 3170 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3171 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3172 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3173 } 3174 3175 if (mode2) { 3176 u32 grph2_cntl; 3177 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3178 3179 if (stop_req > max_stop_req) 3180 stop_req = max_stop_req; 3181 3182 /* 3183 Find the drain rate of the display buffer. 3184 */ 3185 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3186 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3187 3188 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3189 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3190 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3191 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3192 if ((rdev->family == CHIP_R350) && 3193 (stop_req > 0x15)) { 3194 stop_req -= 0x10; 3195 } 3196 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3197 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3198 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3199 RADEON_GRPH_CRITICAL_AT_SOF | 3200 RADEON_GRPH_STOP_CNTL); 3201 3202 if ((rdev->family == CHIP_RS100) || 3203 (rdev->family == CHIP_RS200)) 3204 critical_point2 = 0; 3205 else { 3206 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3207 temp_ff.full = dfixed_const(temp); 3208 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3209 if (sclk_ff.full < temp_ff.full) 3210 temp_ff.full = sclk_ff.full; 3211 3212 read_return_rate.full = temp_ff.full; 3213 3214 if (mode1) { 3215 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3216 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3217 } else { 3218 time_disp1_drop_priority.full = 0; 3219 } 3220 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3221 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3222 crit_point_ff.full += dfixed_const_half(0); 3223 3224 critical_point2 = dfixed_trunc(crit_point_ff); 3225 3226 if (rdev->disp_priority == 2) { 3227 critical_point2 = 0; 3228 } 3229 3230 if (max_stop_req - critical_point2 < 4) 3231 critical_point2 = 0; 3232 3233 } 3234 3235 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3236 /* some R300 cards have problem with this set to 0 */ 3237 critical_point2 = 0x10; 3238 } 3239 3240 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3241 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3242 3243 if ((rdev->family == CHIP_RS400) || 3244 (rdev->family == CHIP_RS480)) { 3245#if 0 3246 /* attempt to program RS400 disp2 regs correctly ??? */ 3247 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3248 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3249 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3250 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3251 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3252 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3253 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3254 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3255 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3256 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3257 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3258 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3259#endif 3260 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3261 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3262 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3263 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3264 } 3265 3266 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3267 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3268 } 3269} 3270 3271static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 3272{ 3273 DRM_ERROR("pitch %d\n", t->pitch); 3274 DRM_ERROR("use_pitch %d\n", t->use_pitch); 3275 DRM_ERROR("width %d\n", t->width); 3276 DRM_ERROR("width_11 %d\n", t->width_11); 3277 DRM_ERROR("height %d\n", t->height); 3278 DRM_ERROR("height_11 %d\n", t->height_11); 3279 DRM_ERROR("num levels %d\n", t->num_levels); 3280 DRM_ERROR("depth %d\n", t->txdepth); 3281 DRM_ERROR("bpp %d\n", t->cpp); 3282 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 3283 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 3284 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 3285 DRM_ERROR("compress format %d\n", t->compress_format); 3286} 3287 3288static int r100_track_compress_size(int compress_format, int w, int h) 3289{ 3290 int block_width, block_height, block_bytes; 3291 int wblocks, hblocks; 3292 int min_wblocks; 3293 int sz; 3294 3295 block_width = 4; 3296 block_height = 4; 3297 3298 switch (compress_format) { 3299 case R100_TRACK_COMP_DXT1: 3300 block_bytes = 8; 3301 min_wblocks = 4; 3302 break; 3303 default: 3304 case R100_TRACK_COMP_DXT35: 3305 block_bytes = 16; 3306 min_wblocks = 2; 3307 break; 3308 } 3309 3310 hblocks = (h + block_height - 1) / block_height; 3311 wblocks = (w + block_width - 1) / block_width; 3312 if (wblocks < min_wblocks) 3313 wblocks = min_wblocks; 3314 sz = wblocks * hblocks * block_bytes; 3315 return sz; 3316} 3317 3318static int r100_cs_track_cube(struct radeon_device *rdev, 3319 struct r100_cs_track *track, unsigned idx) 3320{ 3321 unsigned face, w, h; 3322 struct radeon_bo *cube_robj; 3323 unsigned long size; 3324 unsigned compress_format = track->textures[idx].compress_format; 3325 3326 for (face = 0; face < 5; face++) { 3327 cube_robj = track->textures[idx].cube_info[face].robj; 3328 w = track->textures[idx].cube_info[face].width; 3329 h = track->textures[idx].cube_info[face].height; 3330 3331 if (compress_format) { 3332 size = r100_track_compress_size(compress_format, w, h); 3333 } else 3334 size = w * h; 3335 size *= track->textures[idx].cpp; 3336 3337 size += track->textures[idx].cube_info[face].offset; 3338 3339 if (size > radeon_bo_size(cube_robj)) { 3340 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 3341 size, radeon_bo_size(cube_robj)); 3342 r100_cs_track_texture_print(&track->textures[idx]); 3343 return -1; 3344 } 3345 } 3346 return 0; 3347} 3348 3349static int r100_cs_track_texture_check(struct radeon_device *rdev, 3350 struct r100_cs_track *track) 3351{ 3352 struct radeon_bo *robj; 3353 unsigned long size; 3354 unsigned u, i, w, h, d; 3355 int ret; 3356 3357 for (u = 0; u < track->num_texture; u++) { 3358 if (!track->textures[u].enabled) 3359 continue; 3360 if (track->textures[u].lookup_disable) 3361 continue; 3362 robj = track->textures[u].robj; 3363 if (robj == NULL) { 3364 DRM_ERROR("No texture bound to unit %u\n", u); 3365 return -EINVAL; 3366 } 3367 size = 0; 3368 for (i = 0; i <= track->textures[u].num_levels; i++) { 3369 if (track->textures[u].use_pitch) { 3370 if (rdev->family < CHIP_R300) 3371 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 3372 else 3373 w = track->textures[u].pitch / (1 << i); 3374 } else { 3375 w = track->textures[u].width; 3376 if (rdev->family >= CHIP_RV515) 3377 w |= track->textures[u].width_11; 3378 w = w / (1 << i); 3379 if (track->textures[u].roundup_w) 3380 w = roundup_pow_of_two(w); 3381 } 3382 h = track->textures[u].height; 3383 if (rdev->family >= CHIP_RV515) 3384 h |= track->textures[u].height_11; 3385 h = h / (1 << i); 3386 if (track->textures[u].roundup_h) 3387 h = roundup_pow_of_two(h); 3388 if (track->textures[u].tex_coord_type == 1) { 3389 d = (1 << track->textures[u].txdepth) / (1 << i); 3390 if (!d) 3391 d = 1; 3392 } else { 3393 d = 1; 3394 } 3395 if (track->textures[u].compress_format) { 3396 3397 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 3398 /* compressed textures are block based */ 3399 } else 3400 size += w * h * d; 3401 } 3402 size *= track->textures[u].cpp; 3403 3404 switch (track->textures[u].tex_coord_type) { 3405 case 0: 3406 case 1: 3407 break; 3408 case 2: 3409 if (track->separate_cube) { 3410 ret = r100_cs_track_cube(rdev, track, u); 3411 if (ret) 3412 return ret; 3413 } else 3414 size *= 6; 3415 break; 3416 default: 3417 DRM_ERROR("Invalid texture coordinate type %u for unit " 3418 "%u\n", track->textures[u].tex_coord_type, u); 3419 return -EINVAL; 3420 } 3421 if (size > radeon_bo_size(robj)) { 3422 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 3423 "%lu\n", u, size, radeon_bo_size(robj)); 3424 r100_cs_track_texture_print(&track->textures[u]); 3425 return -EINVAL; 3426 } 3427 } 3428 return 0; 3429} 3430 3431int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 3432{ 3433 unsigned i; 3434 unsigned long size; 3435 unsigned prim_walk; 3436 unsigned nverts; 3437 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 3438 3439 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 3440 !track->blend_read_enable) 3441 num_cb = 0; 3442 3443 for (i = 0; i < num_cb; i++) { 3444 if (track->cb[i].robj == NULL) { 3445 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3446 return -EINVAL; 3447 } 3448 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 3449 size += track->cb[i].offset; 3450 if (size > radeon_bo_size(track->cb[i].robj)) { 3451 DRM_ERROR("[drm] Buffer too small for color buffer %d " 3452 "(need %lu have %lu) !\n", i, size, 3453 radeon_bo_size(track->cb[i].robj)); 3454 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 3455 i, track->cb[i].pitch, track->cb[i].cpp, 3456 track->cb[i].offset, track->maxy); 3457 return -EINVAL; 3458 } 3459 } 3460 track->cb_dirty = false; 3461 3462 if (track->zb_dirty && track->z_enabled) { 3463 if (track->zb.robj == NULL) { 3464 DRM_ERROR("[drm] No buffer for z buffer !\n"); 3465 return -EINVAL; 3466 } 3467 size = track->zb.pitch * track->zb.cpp * track->maxy; 3468 size += track->zb.offset; 3469 if (size > radeon_bo_size(track->zb.robj)) { 3470 DRM_ERROR("[drm] Buffer too small for z buffer " 3471 "(need %lu have %lu) !\n", size, 3472 radeon_bo_size(track->zb.robj)); 3473 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 3474 track->zb.pitch, track->zb.cpp, 3475 track->zb.offset, track->maxy); 3476 return -EINVAL; 3477 } 3478 } 3479 track->zb_dirty = false; 3480 3481 if (track->aa_dirty && track->aaresolve) { 3482 if (track->aa.robj == NULL) { 3483 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 3484 return -EINVAL; 3485 } 3486 /* I believe the format comes from colorbuffer0. */ 3487 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 3488 size += track->aa.offset; 3489 if (size > radeon_bo_size(track->aa.robj)) { 3490 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 3491 "(need %lu have %lu) !\n", i, size, 3492 radeon_bo_size(track->aa.robj)); 3493 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 3494 i, track->aa.pitch, track->cb[0].cpp, 3495 track->aa.offset, track->maxy); 3496 return -EINVAL; 3497 } 3498 } 3499 track->aa_dirty = false; 3500 3501 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3502 if (track->vap_vf_cntl & (1 << 14)) { 3503 nverts = track->vap_alt_nverts; 3504 } else { 3505 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3506 } 3507 switch (prim_walk) { 3508 case 1: 3509 for (i = 0; i < track->num_arrays; i++) { 3510 size = track->arrays[i].esize * track->max_indx * 4; 3511 if (track->arrays[i].robj == NULL) { 3512 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3513 "bound\n", prim_walk, i); 3514 return -EINVAL; 3515 } 3516 if (size > radeon_bo_size(track->arrays[i].robj)) { 3517 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3518 "need %lu dwords have %lu dwords\n", 3519 prim_walk, i, size >> 2, 3520 radeon_bo_size(track->arrays[i].robj) 3521 >> 2); 3522 DRM_ERROR("Max indices %u\n", track->max_indx); 3523 return -EINVAL; 3524 } 3525 } 3526 break; 3527 case 2: 3528 for (i = 0; i < track->num_arrays; i++) { 3529 size = track->arrays[i].esize * (nverts - 1) * 4; 3530 if (track->arrays[i].robj == NULL) { 3531 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3532 "bound\n", prim_walk, i); 3533 return -EINVAL; 3534 } 3535 if (size > radeon_bo_size(track->arrays[i].robj)) { 3536 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3537 "need %lu dwords have %lu dwords\n", 3538 prim_walk, i, size >> 2, 3539 radeon_bo_size(track->arrays[i].robj) 3540 >> 2); 3541 return -EINVAL; 3542 } 3543 } 3544 break; 3545 case 3: 3546 size = track->vtx_size * nverts; 3547 if (size != track->immd_dwords) { 3548 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 3549 track->immd_dwords, size); 3550 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 3551 nverts, track->vtx_size); 3552 return -EINVAL; 3553 } 3554 break; 3555 default: 3556 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 3557 prim_walk); 3558 return -EINVAL; 3559 } 3560 3561 if (track->tex_dirty) { 3562 track->tex_dirty = false; 3563 return r100_cs_track_texture_check(rdev, track); 3564 } 3565 return 0; 3566} 3567 3568void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 3569{ 3570 unsigned i, face; 3571 3572 track->cb_dirty = true; 3573 track->zb_dirty = true; 3574 track->tex_dirty = true; 3575 track->aa_dirty = true; 3576 3577 if (rdev->family < CHIP_R300) { 3578 track->num_cb = 1; 3579 if (rdev->family <= CHIP_RS200) 3580 track->num_texture = 3; 3581 else 3582 track->num_texture = 6; 3583 track->maxy = 2048; 3584 track->separate_cube = 1; 3585 } else { 3586 track->num_cb = 4; 3587 track->num_texture = 16; 3588 track->maxy = 4096; 3589 track->separate_cube = 0; 3590 track->aaresolve = false; 3591 track->aa.robj = NULL; 3592 } 3593 3594 for (i = 0; i < track->num_cb; i++) { 3595 track->cb[i].robj = NULL; 3596 track->cb[i].pitch = 8192; 3597 track->cb[i].cpp = 16; 3598 track->cb[i].offset = 0; 3599 } 3600 track->z_enabled = true; 3601 track->zb.robj = NULL; 3602 track->zb.pitch = 8192; 3603 track->zb.cpp = 4; 3604 track->zb.offset = 0; 3605 track->vtx_size = 0x7F; 3606 track->immd_dwords = 0xFFFFFFFFUL; 3607 track->num_arrays = 11; 3608 track->max_indx = 0x00FFFFFFUL; 3609 for (i = 0; i < track->num_arrays; i++) { 3610 track->arrays[i].robj = NULL; 3611 track->arrays[i].esize = 0x7F; 3612 } 3613 for (i = 0; i < track->num_texture; i++) { 3614 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 3615 track->textures[i].pitch = 16536; 3616 track->textures[i].width = 16536; 3617 track->textures[i].height = 16536; 3618 track->textures[i].width_11 = 1 << 11; 3619 track->textures[i].height_11 = 1 << 11; 3620 track->textures[i].num_levels = 12; 3621 if (rdev->family <= CHIP_RS200) { 3622 track->textures[i].tex_coord_type = 0; 3623 track->textures[i].txdepth = 0; 3624 } else { 3625 track->textures[i].txdepth = 16; 3626 track->textures[i].tex_coord_type = 1; 3627 } 3628 track->textures[i].cpp = 64; 3629 track->textures[i].robj = NULL; 3630 /* CS IB emission code makes sure texture unit are disabled */ 3631 track->textures[i].enabled = false; 3632 track->textures[i].lookup_disable = false; 3633 track->textures[i].roundup_w = true; 3634 track->textures[i].roundup_h = true; 3635 if (track->separate_cube) 3636 for (face = 0; face < 5; face++) { 3637 track->textures[i].cube_info[face].robj = NULL; 3638 track->textures[i].cube_info[face].width = 16536; 3639 track->textures[i].cube_info[face].height = 16536; 3640 track->textures[i].cube_info[face].offset = 0; 3641 } 3642 } 3643} 3644 3645int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3646{ 3647 uint32_t scratch; 3648 uint32_t tmp = 0; 3649 unsigned i; 3650 int r; 3651 3652 r = radeon_scratch_get(rdev, &scratch); 3653 if (r) { 3654 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3655 return r; 3656 } 3657 WREG32(scratch, 0xCAFEDEAD); 3658 r = radeon_ring_lock(rdev, ring, 2); 3659 if (r) { 3660 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3661 radeon_scratch_free(rdev, scratch); 3662 return r; 3663 } 3664 radeon_ring_write(ring, PACKET0(scratch, 0)); 3665 radeon_ring_write(ring, 0xDEADBEEF); 3666 radeon_ring_unlock_commit(rdev, ring); 3667 for (i = 0; i < rdev->usec_timeout; i++) { 3668 tmp = RREG32(scratch); 3669 if (tmp == 0xDEADBEEF) { 3670 break; 3671 } 3672 DRM_UDELAY(1); 3673 } 3674 if (i < rdev->usec_timeout) { 3675 DRM_INFO("ring test succeeded in %d usecs\n", i); 3676 } else { 3677 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3678 scratch, tmp); 3679 r = -EINVAL; 3680 } 3681 radeon_scratch_free(rdev, scratch); 3682 return r; 3683} 3684 3685void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3686{ 3687 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3688 3689 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3690 radeon_ring_write(ring, ib->gpu_addr); 3691 radeon_ring_write(ring, ib->length_dw); 3692} 3693 3694int r100_ib_test(struct radeon_device *rdev) 3695{ 3696 struct radeon_ib *ib; 3697 uint32_t scratch; 3698 uint32_t tmp = 0; 3699 unsigned i; 3700 int r; 3701 3702 r = radeon_scratch_get(rdev, &scratch); 3703 if (r) { 3704 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3705 return r; 3706 } 3707 WREG32(scratch, 0xCAFEDEAD); 3708 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256); 3709 if (r) { 3710 return r; 3711 } 3712 ib->ptr[0] = PACKET0(scratch, 0); 3713 ib->ptr[1] = 0xDEADBEEF; 3714 ib->ptr[2] = PACKET2(0); 3715 ib->ptr[3] = PACKET2(0); 3716 ib->ptr[4] = PACKET2(0); 3717 ib->ptr[5] = PACKET2(0); 3718 ib->ptr[6] = PACKET2(0); 3719 ib->ptr[7] = PACKET2(0); 3720 ib->length_dw = 8; 3721 r = radeon_ib_schedule(rdev, ib); 3722 if (r) { 3723 radeon_scratch_free(rdev, scratch); 3724 radeon_ib_free(rdev, &ib); 3725 return r; 3726 } 3727 r = radeon_fence_wait(ib->fence, false); 3728 if (r) { 3729 return r; 3730 } 3731 for (i = 0; i < rdev->usec_timeout; i++) { 3732 tmp = RREG32(scratch); 3733 if (tmp == 0xDEADBEEF) { 3734 break; 3735 } 3736 DRM_UDELAY(1); 3737 } 3738 if (i < rdev->usec_timeout) { 3739 DRM_INFO("ib test succeeded in %u usecs\n", i); 3740 } else { 3741 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3742 scratch, tmp); 3743 r = -EINVAL; 3744 } 3745 radeon_scratch_free(rdev, scratch); 3746 radeon_ib_free(rdev, &ib); 3747 return r; 3748} 3749 3750void r100_ib_fini(struct radeon_device *rdev) 3751{ 3752 radeon_ib_pool_suspend(rdev); 3753 radeon_ib_pool_fini(rdev); 3754} 3755 3756void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3757{ 3758 /* Shutdown CP we shouldn't need to do that but better be safe than 3759 * sorry 3760 */ 3761 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3762 WREG32(R_000740_CP_CSQ_CNTL, 0); 3763 3764 /* Save few CRTC registers */ 3765 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3766 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3767 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3768 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3769 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3770 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3771 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3772 } 3773 3774 /* Disable VGA aperture access */ 3775 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3776 /* Disable cursor, overlay, crtc */ 3777 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3778 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3779 S_000054_CRTC_DISPLAY_DIS(1)); 3780 WREG32(R_000050_CRTC_GEN_CNTL, 3781 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3782 S_000050_CRTC_DISP_REQ_EN_B(1)); 3783 WREG32(R_000420_OV0_SCALE_CNTL, 3784 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3785 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3786 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3787 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3788 S_000360_CUR2_LOCK(1)); 3789 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3790 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3791 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3792 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3793 WREG32(R_000360_CUR2_OFFSET, 3794 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3795 } 3796} 3797 3798void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3799{ 3800 /* Update base address for crtc */ 3801 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3802 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3803 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3804 } 3805 /* Restore CRTC registers */ 3806 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3807 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3808 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3809 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3810 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3811 } 3812} 3813 3814void r100_vga_render_disable(struct radeon_device *rdev) 3815{ 3816 u32 tmp; 3817 3818 tmp = RREG8(R_0003C2_GENMO_WT); 3819 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3820} 3821 3822static void r100_debugfs(struct radeon_device *rdev) 3823{ 3824 int r; 3825 3826 r = r100_debugfs_mc_info_init(rdev); 3827 if (r) 3828 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3829} 3830 3831static void r100_mc_program(struct radeon_device *rdev) 3832{ 3833 struct r100_mc_save save; 3834 3835 /* Stops all mc clients */ 3836 r100_mc_stop(rdev, &save); 3837 if (rdev->flags & RADEON_IS_AGP) { 3838 WREG32(R_00014C_MC_AGP_LOCATION, 3839 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3840 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3841 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3842 if (rdev->family > CHIP_RV200) 3843 WREG32(R_00015C_AGP_BASE_2, 3844 upper_32_bits(rdev->mc.agp_base) & 0xff); 3845 } else { 3846 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3847 WREG32(R_000170_AGP_BASE, 0); 3848 if (rdev->family > CHIP_RV200) 3849 WREG32(R_00015C_AGP_BASE_2, 0); 3850 } 3851 /* Wait for mc idle */ 3852 if (r100_mc_wait_for_idle(rdev)) 3853 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3854 /* Program MC, should be a 32bits limited address space */ 3855 WREG32(R_000148_MC_FB_LOCATION, 3856 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3857 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3858 r100_mc_resume(rdev, &save); 3859} 3860 3861void r100_clock_startup(struct radeon_device *rdev) 3862{ 3863 u32 tmp; 3864 3865 if (radeon_dynclks != -1 && radeon_dynclks) 3866 radeon_legacy_set_clock_gating(rdev, 1); 3867 /* We need to force on some of the block */ 3868 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3869 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3870 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3871 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3872 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3873} 3874 3875static int r100_startup(struct radeon_device *rdev) 3876{ 3877 int r; 3878 3879 /* set common regs */ 3880 r100_set_common_regs(rdev); 3881 /* program mc */ 3882 r100_mc_program(rdev); 3883 /* Resume clock */ 3884 r100_clock_startup(rdev); 3885 /* Initialize GART (initialize after TTM so we can allocate 3886 * memory through TTM but finalize after TTM) */ 3887 r100_enable_bm(rdev); 3888 if (rdev->flags & RADEON_IS_PCI) { 3889 r = r100_pci_gart_enable(rdev); 3890 if (r) 3891 return r; 3892 } 3893 3894 /* allocate wb buffer */ 3895 r = radeon_wb_init(rdev); 3896 if (r) 3897 return r; 3898 3899 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3900 if (r) { 3901 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3902 return r; 3903 } 3904 3905 /* Enable IRQ */ 3906 r100_irq_set(rdev); 3907 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3908 /* 1M ring buffer */ 3909 r = r100_cp_init(rdev, 1024 * 1024); 3910 if (r) { 3911 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3912 return r; 3913 } 3914 3915 r = radeon_ib_pool_start(rdev); 3916 if (r) 3917 return r; 3918 3919 r = r100_ib_test(rdev); 3920 if (r) { 3921 dev_err(rdev->dev, "failed testing IB (%d).\n", r); 3922 rdev->accel_working = false; 3923 return r; 3924 } 3925 3926 return 0; 3927} 3928 3929int r100_resume(struct radeon_device *rdev) 3930{ 3931 int r; 3932 3933 /* Make sur GART are not working */ 3934 if (rdev->flags & RADEON_IS_PCI) 3935 r100_pci_gart_disable(rdev); 3936 /* Resume clock before doing reset */ 3937 r100_clock_startup(rdev); 3938 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3939 if (radeon_asic_reset(rdev)) { 3940 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3941 RREG32(R_000E40_RBBM_STATUS), 3942 RREG32(R_0007C0_CP_STAT)); 3943 } 3944 /* post */ 3945 radeon_combios_asic_init(rdev->ddev); 3946 /* Resume clock after posting */ 3947 r100_clock_startup(rdev); 3948 /* Initialize surface registers */ 3949 radeon_surface_init(rdev); 3950 3951 rdev->accel_working = true; 3952 r = r100_startup(rdev); 3953 if (r) { 3954 rdev->accel_working = false; 3955 } 3956 return r; 3957} 3958 3959int r100_suspend(struct radeon_device *rdev) 3960{ 3961 radeon_ib_pool_suspend(rdev); 3962 r100_cp_disable(rdev); 3963 radeon_wb_disable(rdev); 3964 r100_irq_disable(rdev); 3965 if (rdev->flags & RADEON_IS_PCI) 3966 r100_pci_gart_disable(rdev); 3967 return 0; 3968} 3969 3970void r100_fini(struct radeon_device *rdev) 3971{ 3972 r100_cp_fini(rdev); 3973 radeon_wb_fini(rdev); 3974 r100_ib_fini(rdev); 3975 radeon_gem_fini(rdev); 3976 if (rdev->flags & RADEON_IS_PCI) 3977 r100_pci_gart_fini(rdev); 3978 radeon_agp_fini(rdev); 3979 radeon_irq_kms_fini(rdev); 3980 radeon_fence_driver_fini(rdev); 3981 radeon_bo_fini(rdev); 3982 radeon_atombios_fini(rdev); 3983 kfree(rdev->bios); 3984 rdev->bios = NULL; 3985} 3986 3987/* 3988 * Due to how kexec works, it can leave the hw fully initialised when it 3989 * boots the new kernel. However doing our init sequence with the CP and 3990 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3991 * do some quick sanity checks and restore sane values to avoid this 3992 * problem. 3993 */ 3994void r100_restore_sanity(struct radeon_device *rdev) 3995{ 3996 u32 tmp; 3997 3998 tmp = RREG32(RADEON_CP_CSQ_CNTL); 3999 if (tmp) { 4000 WREG32(RADEON_CP_CSQ_CNTL, 0); 4001 } 4002 tmp = RREG32(RADEON_CP_RB_CNTL); 4003 if (tmp) { 4004 WREG32(RADEON_CP_RB_CNTL, 0); 4005 } 4006 tmp = RREG32(RADEON_SCRATCH_UMSK); 4007 if (tmp) { 4008 WREG32(RADEON_SCRATCH_UMSK, 0); 4009 } 4010} 4011 4012int r100_init(struct radeon_device *rdev) 4013{ 4014 int r; 4015 4016 /* Register debugfs file specific to this group of asics */ 4017 r100_debugfs(rdev); 4018 /* Disable VGA */ 4019 r100_vga_render_disable(rdev); 4020 /* Initialize scratch registers */ 4021 radeon_scratch_init(rdev); 4022 /* Initialize surface registers */ 4023 radeon_surface_init(rdev); 4024 /* sanity check some register to avoid hangs like after kexec */ 4025 r100_restore_sanity(rdev); 4026 /* TODO: disable VGA need to use VGA request */ 4027 /* BIOS*/ 4028 if (!radeon_get_bios(rdev)) { 4029 if (ASIC_IS_AVIVO(rdev)) 4030 return -EINVAL; 4031 } 4032 if (rdev->is_atom_bios) { 4033 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4034 return -EINVAL; 4035 } else { 4036 r = radeon_combios_init(rdev); 4037 if (r) 4038 return r; 4039 } 4040 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4041 if (radeon_asic_reset(rdev)) { 4042 dev_warn(rdev->dev, 4043 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4044 RREG32(R_000E40_RBBM_STATUS), 4045 RREG32(R_0007C0_CP_STAT)); 4046 } 4047 /* check if cards are posted or not */ 4048 if (radeon_boot_test_post_card(rdev) == false) 4049 return -EINVAL; 4050 /* Set asic errata */ 4051 r100_errata(rdev); 4052 /* Initialize clocks */ 4053 radeon_get_clock_info(rdev->ddev); 4054 /* initialize AGP */ 4055 if (rdev->flags & RADEON_IS_AGP) { 4056 r = radeon_agp_init(rdev); 4057 if (r) { 4058 radeon_agp_disable(rdev); 4059 } 4060 } 4061 /* initialize VRAM */ 4062 r100_mc_init(rdev); 4063 /* Fence driver */ 4064 r = radeon_fence_driver_init(rdev); 4065 if (r) 4066 return r; 4067 r = radeon_irq_kms_init(rdev); 4068 if (r) 4069 return r; 4070 /* Memory manager */ 4071 r = radeon_bo_init(rdev); 4072 if (r) 4073 return r; 4074 if (rdev->flags & RADEON_IS_PCI) { 4075 r = r100_pci_gart_init(rdev); 4076 if (r) 4077 return r; 4078 } 4079 r100_set_safe_registers(rdev); 4080 4081 r = radeon_ib_pool_init(rdev); 4082 rdev->accel_working = true; 4083 if (r) { 4084 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4085 rdev->accel_working = false; 4086 } 4087 4088 r = r100_startup(rdev); 4089 if (r) { 4090 /* Somethings want wront with the accel init stop accel */ 4091 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4092 r100_cp_fini(rdev); 4093 radeon_wb_fini(rdev); 4094 r100_ib_fini(rdev); 4095 radeon_irq_kms_fini(rdev); 4096 if (rdev->flags & RADEON_IS_PCI) 4097 r100_pci_gart_fini(rdev); 4098 rdev->accel_working = false; 4099 } 4100 return 0; 4101} 4102 4103uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 4104{ 4105 if (reg < rdev->rmmio_size) 4106 return readl(((void __iomem *)rdev->rmmio) + reg); 4107 else { 4108 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4109 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4110 } 4111} 4112 4113void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4114{ 4115 if (reg < rdev->rmmio_size) 4116 writel(v, ((void __iomem *)rdev->rmmio) + reg); 4117 else { 4118 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4119 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4120 } 4121} 4122 4123u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4124{ 4125 if (reg < rdev->rio_mem_size) 4126 return ioread32(rdev->rio_mem + reg); 4127 else { 4128 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4129 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4130 } 4131} 4132 4133void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4134{ 4135 if (reg < rdev->rio_mem_size) 4136 iowrite32(v, rdev->rio_mem + reg); 4137 else { 4138 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4139 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4140 } 4141} 4142