1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __RADEON_ASIC_H__ 29#define __RADEON_ASIC_H__ 30 31/* 32 * common functions 33 */ 34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45/* 46 * r100,rv100,rs100,rv200,rs200 47 */ 48struct r100_mc_save { 49 u32 GENMO_WT; 50 u32 CRTC_EXT_CNTL; 51 u32 CRTC_GEN_CNTL; 52 u32 CRTC2_GEN_CNTL; 53 u32 CUR_OFFSET; 54 u32 CUR2_OFFSET; 55}; 56int r100_init(struct radeon_device *rdev); 57void r100_fini(struct radeon_device *rdev); 58int r100_suspend(struct radeon_device *rdev); 59int r100_resume(struct radeon_device *rdev); 60void r100_vga_set_state(struct radeon_device *rdev, bool state); 61bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 62int r100_asic_reset(struct radeon_device *rdev); 63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 64void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 66void r100_ring_start(struct radeon_device *rdev); 67int r100_irq_set(struct radeon_device *rdev); 68int r100_irq_process(struct radeon_device *rdev); 69void r100_fence_ring_emit(struct radeon_device *rdev, 70 struct radeon_fence *fence); 71void r100_semaphore_ring_emit(struct radeon_device *rdev, 72 struct radeon_ring *cp, 73 struct radeon_semaphore *semaphore, 74 bool emit_wait); 75int r100_cs_parse(struct radeon_cs_parser *p); 76void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 77uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 78int r100_copy_blit(struct radeon_device *rdev, 79 uint64_t src_offset, 80 uint64_t dst_offset, 81 unsigned num_gpu_pages, 82 struct radeon_fence *fence); 83int r100_set_surface_reg(struct radeon_device *rdev, int reg, 84 uint32_t tiling_flags, uint32_t pitch, 85 uint32_t offset, uint32_t obj_size); 86void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 87void r100_bandwidth_update(struct radeon_device *rdev); 88void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 89int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 90void r100_hpd_init(struct radeon_device *rdev); 91void r100_hpd_fini(struct radeon_device *rdev); 92bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 93void r100_hpd_set_polarity(struct radeon_device *rdev, 94 enum radeon_hpd_id hpd); 95int r100_debugfs_rbbm_init(struct radeon_device *rdev); 96int r100_debugfs_cp_init(struct radeon_device *rdev); 97void r100_cp_disable(struct radeon_device *rdev); 98int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 99void r100_cp_fini(struct radeon_device *rdev); 100int r100_pci_gart_init(struct radeon_device *rdev); 101void r100_pci_gart_fini(struct radeon_device *rdev); 102int r100_pci_gart_enable(struct radeon_device *rdev); 103void r100_pci_gart_disable(struct radeon_device *rdev); 104int r100_debugfs_mc_info_init(struct radeon_device *rdev); 105int r100_gui_wait_for_idle(struct radeon_device *rdev); 106void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, 107 struct radeon_ring *cp); 108bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, 109 struct r100_gpu_lockup *lockup, 110 struct radeon_ring *cp); 111void r100_ib_fini(struct radeon_device *rdev); 112int r100_ib_test(struct radeon_device *rdev); 113void r100_irq_disable(struct radeon_device *rdev); 114void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 115void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 116void r100_vram_init_sizes(struct radeon_device *rdev); 117int r100_cp_reset(struct radeon_device *rdev); 118void r100_vga_render_disable(struct radeon_device *rdev); 119void r100_restore_sanity(struct radeon_device *rdev); 120int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 121 struct radeon_cs_packet *pkt, 122 struct radeon_bo *robj); 123int r100_cs_parse_packet0(struct radeon_cs_parser *p, 124 struct radeon_cs_packet *pkt, 125 const unsigned *auth, unsigned n, 126 radeon_packet0_check_t check); 127int r100_cs_packet_parse(struct radeon_cs_parser *p, 128 struct radeon_cs_packet *pkt, 129 unsigned idx); 130void r100_enable_bm(struct radeon_device *rdev); 131void r100_set_common_regs(struct radeon_device *rdev); 132void r100_bm_disable(struct radeon_device *rdev); 133extern bool r100_gui_idle(struct radeon_device *rdev); 134extern void r100_pm_misc(struct radeon_device *rdev); 135extern void r100_pm_prepare(struct radeon_device *rdev); 136extern void r100_pm_finish(struct radeon_device *rdev); 137extern void r100_pm_init_profile(struct radeon_device *rdev); 138extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 139extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 140extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 141extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 142 143/* 144 * r200,rv250,rs300,rv280 145 */ 146extern int r200_copy_dma(struct radeon_device *rdev, 147 uint64_t src_offset, 148 uint64_t dst_offset, 149 unsigned num_gpu_pages, 150 struct radeon_fence *fence); 151void r200_set_safe_registers(struct radeon_device *rdev); 152 153/* 154 * r300,r350,rv350,rv380 155 */ 156extern int r300_init(struct radeon_device *rdev); 157extern void r300_fini(struct radeon_device *rdev); 158extern int r300_suspend(struct radeon_device *rdev); 159extern int r300_resume(struct radeon_device *rdev); 160extern bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 161extern int r300_asic_reset(struct radeon_device *rdev); 162extern void r300_ring_start(struct radeon_device *rdev); 163extern void r300_fence_ring_emit(struct radeon_device *rdev, 164 struct radeon_fence *fence); 165extern int r300_cs_parse(struct radeon_cs_parser *p); 166extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 167extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 168extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 169extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 170extern void r300_set_reg_safe(struct radeon_device *rdev); 171extern void r300_mc_program(struct radeon_device *rdev); 172extern void r300_mc_init(struct radeon_device *rdev); 173extern void r300_clock_startup(struct radeon_device *rdev); 174extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 175extern int rv370_pcie_gart_init(struct radeon_device *rdev); 176extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 177extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 178extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 179 180/* 181 * r420,r423,rv410 182 */ 183extern int r420_init(struct radeon_device *rdev); 184extern void r420_fini(struct radeon_device *rdev); 185extern int r420_suspend(struct radeon_device *rdev); 186extern int r420_resume(struct radeon_device *rdev); 187extern void r420_pm_init_profile(struct radeon_device *rdev); 188extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 189extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 190extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 191extern void r420_pipes_init(struct radeon_device *rdev); 192 193/* 194 * rs400,rs480 195 */ 196extern int rs400_init(struct radeon_device *rdev); 197extern void rs400_fini(struct radeon_device *rdev); 198extern int rs400_suspend(struct radeon_device *rdev); 199extern int rs400_resume(struct radeon_device *rdev); 200void rs400_gart_tlb_flush(struct radeon_device *rdev); 201int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 202uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 203void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 204int rs400_gart_init(struct radeon_device *rdev); 205int rs400_gart_enable(struct radeon_device *rdev); 206void rs400_gart_adjust_size(struct radeon_device *rdev); 207void rs400_gart_disable(struct radeon_device *rdev); 208void rs400_gart_fini(struct radeon_device *rdev); 209 210/* 211 * rs600. 212 */ 213extern int rs600_asic_reset(struct radeon_device *rdev); 214extern int rs600_init(struct radeon_device *rdev); 215extern void rs600_fini(struct radeon_device *rdev); 216extern int rs600_suspend(struct radeon_device *rdev); 217extern int rs600_resume(struct radeon_device *rdev); 218int rs600_irq_set(struct radeon_device *rdev); 219int rs600_irq_process(struct radeon_device *rdev); 220void rs600_irq_disable(struct radeon_device *rdev); 221u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 222void rs600_gart_tlb_flush(struct radeon_device *rdev); 223int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 224uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 225void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 226void rs600_bandwidth_update(struct radeon_device *rdev); 227void rs600_hpd_init(struct radeon_device *rdev); 228void rs600_hpd_fini(struct radeon_device *rdev); 229bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 230void rs600_hpd_set_polarity(struct radeon_device *rdev, 231 enum radeon_hpd_id hpd); 232extern void rs600_pm_misc(struct radeon_device *rdev); 233extern void rs600_pm_prepare(struct radeon_device *rdev); 234extern void rs600_pm_finish(struct radeon_device *rdev); 235extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 236extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 237extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 238void rs600_set_safe_registers(struct radeon_device *rdev); 239 240 241/* 242 * rs690,rs740 243 */ 244int rs690_init(struct radeon_device *rdev); 245void rs690_fini(struct radeon_device *rdev); 246int rs690_resume(struct radeon_device *rdev); 247int rs690_suspend(struct radeon_device *rdev); 248uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 249void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 250void rs690_bandwidth_update(struct radeon_device *rdev); 251void rs690_line_buffer_adjust(struct radeon_device *rdev, 252 struct drm_display_mode *mode1, 253 struct drm_display_mode *mode2); 254 255/* 256 * rv515 257 */ 258struct rv515_mc_save { 259 u32 d1vga_control; 260 u32 d2vga_control; 261 u32 vga_render_control; 262 u32 vga_hdp_control; 263 u32 d1crtc_control; 264 u32 d2crtc_control; 265}; 266int rv515_init(struct radeon_device *rdev); 267void rv515_fini(struct radeon_device *rdev); 268uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 269void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 270void rv515_ring_start(struct radeon_device *rdev); 271void rv515_bandwidth_update(struct radeon_device *rdev); 272int rv515_resume(struct radeon_device *rdev); 273int rv515_suspend(struct radeon_device *rdev); 274void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 275void rv515_vga_render_disable(struct radeon_device *rdev); 276void rv515_set_safe_registers(struct radeon_device *rdev); 277void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 278void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 279void rv515_clock_startup(struct radeon_device *rdev); 280void rv515_debugfs(struct radeon_device *rdev); 281 282 283/* 284 * r520,rv530,rv560,rv570,r580 285 */ 286int r520_init(struct radeon_device *rdev); 287int r520_resume(struct radeon_device *rdev); 288 289/* 290 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 291 */ 292int r600_init(struct radeon_device *rdev); 293void r600_fini(struct radeon_device *rdev); 294int r600_suspend(struct radeon_device *rdev); 295int r600_resume(struct radeon_device *rdev); 296void r600_vga_set_state(struct radeon_device *rdev, bool state); 297int r600_wb_init(struct radeon_device *rdev); 298void r600_wb_fini(struct radeon_device *rdev); 299void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 300uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 301void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 302int r600_cs_parse(struct radeon_cs_parser *p); 303void r600_fence_ring_emit(struct radeon_device *rdev, 304 struct radeon_fence *fence); 305void r600_semaphore_ring_emit(struct radeon_device *rdev, 306 struct radeon_ring *cp, 307 struct radeon_semaphore *semaphore, 308 bool emit_wait); 309bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 310int r600_asic_reset(struct radeon_device *rdev); 311int r600_set_surface_reg(struct radeon_device *rdev, int reg, 312 uint32_t tiling_flags, uint32_t pitch, 313 uint32_t offset, uint32_t obj_size); 314void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 315int r600_ib_test(struct radeon_device *rdev, int ring); 316void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 317int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 318int r600_copy_blit(struct radeon_device *rdev, 319 uint64_t src_offset, uint64_t dst_offset, 320 unsigned num_gpu_pages, struct radeon_fence *fence); 321void r600_hpd_init(struct radeon_device *rdev); 322void r600_hpd_fini(struct radeon_device *rdev); 323bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 324void r600_hpd_set_polarity(struct radeon_device *rdev, 325 enum radeon_hpd_id hpd); 326extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 327extern bool r600_gui_idle(struct radeon_device *rdev); 328extern void r600_pm_misc(struct radeon_device *rdev); 329extern void r600_pm_init_profile(struct radeon_device *rdev); 330extern void rs780_pm_init_profile(struct radeon_device *rdev); 331extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 332extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 333extern int r600_get_pcie_lanes(struct radeon_device *rdev); 334bool r600_card_posted(struct radeon_device *rdev); 335void r600_cp_stop(struct radeon_device *rdev); 336int r600_cp_start(struct radeon_device *rdev); 337void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 338int r600_cp_resume(struct radeon_device *rdev); 339void r600_cp_fini(struct radeon_device *rdev); 340int r600_count_pipe_bits(uint32_t val); 341int r600_mc_wait_for_idle(struct radeon_device *rdev); 342int r600_pcie_gart_init(struct radeon_device *rdev); 343void r600_scratch_init(struct radeon_device *rdev); 344int r600_blit_init(struct radeon_device *rdev); 345void r600_blit_fini(struct radeon_device *rdev); 346int r600_init_microcode(struct radeon_device *rdev); 347/* r600 irq */ 348int r600_irq_process(struct radeon_device *rdev); 349int r600_irq_init(struct radeon_device *rdev); 350void r600_irq_fini(struct radeon_device *rdev); 351void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 352int r600_irq_set(struct radeon_device *rdev); 353void r600_irq_suspend(struct radeon_device *rdev); 354void r600_disable_interrupts(struct radeon_device *rdev); 355void r600_rlc_stop(struct radeon_device *rdev); 356/* r600 audio */ 357int r600_audio_init(struct radeon_device *rdev); 358int r600_audio_tmds_index(struct drm_encoder *encoder); 359void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 360int r600_audio_channels(struct radeon_device *rdev); 361int r600_audio_bits_per_sample(struct radeon_device *rdev); 362int r600_audio_rate(struct radeon_device *rdev); 363uint8_t r600_audio_status_bits(struct radeon_device *rdev); 364uint8_t r600_audio_category_code(struct radeon_device *rdev); 365void r600_audio_schedule_polling(struct radeon_device *rdev); 366void r600_audio_enable_polling(struct drm_encoder *encoder); 367void r600_audio_disable_polling(struct drm_encoder *encoder); 368void r600_audio_fini(struct radeon_device *rdev); 369void r600_hdmi_init(struct drm_encoder *encoder); 370int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 371void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 372/* r600 blit */ 373int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages); 374void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 375void r600_kms_blit_copy(struct radeon_device *rdev, 376 u64 src_gpu_addr, u64 dst_gpu_addr, 377 unsigned num_gpu_pages); 378 379/* 380 * rv770,rv730,rv710,rv740 381 */ 382int rv770_init(struct radeon_device *rdev); 383void rv770_fini(struct radeon_device *rdev); 384int rv770_suspend(struct radeon_device *rdev); 385int rv770_resume(struct radeon_device *rdev); 386void rv770_pm_misc(struct radeon_device *rdev); 387u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 388void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 389void r700_cp_stop(struct radeon_device *rdev); 390void r700_cp_fini(struct radeon_device *rdev); 391 392/* 393 * evergreen 394 */ 395struct evergreen_mc_save { 396 u32 vga_control[6]; 397 u32 vga_render_control; 398 u32 vga_hdp_control; 399 u32 crtc_control[6]; 400}; 401void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 402int evergreen_init(struct radeon_device *rdev); 403void evergreen_fini(struct radeon_device *rdev); 404int evergreen_suspend(struct radeon_device *rdev); 405int evergreen_resume(struct radeon_device *rdev); 406bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 407int evergreen_asic_reset(struct radeon_device *rdev); 408void evergreen_bandwidth_update(struct radeon_device *rdev); 409void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 410void evergreen_hpd_init(struct radeon_device *rdev); 411void evergreen_hpd_fini(struct radeon_device *rdev); 412bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 413void evergreen_hpd_set_polarity(struct radeon_device *rdev, 414 enum radeon_hpd_id hpd); 415u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 416int evergreen_irq_set(struct radeon_device *rdev); 417int evergreen_irq_process(struct radeon_device *rdev); 418extern int evergreen_cs_parse(struct radeon_cs_parser *p); 419extern void evergreen_pm_misc(struct radeon_device *rdev); 420extern void evergreen_pm_prepare(struct radeon_device *rdev); 421extern void evergreen_pm_finish(struct radeon_device *rdev); 422extern void sumo_pm_init_profile(struct radeon_device *rdev); 423extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 424extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 425extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 426void evergreen_disable_interrupt_state(struct radeon_device *rdev); 427int evergreen_blit_init(struct radeon_device *rdev); 428 429/* 430 * cayman 431 */ 432void cayman_fence_ring_emit(struct radeon_device *rdev, 433 struct radeon_fence *fence); 434void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 435int cayman_init(struct radeon_device *rdev); 436void cayman_fini(struct radeon_device *rdev); 437int cayman_suspend(struct radeon_device *rdev); 438int cayman_resume(struct radeon_device *rdev); 439bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 440int cayman_asic_reset(struct radeon_device *rdev); 441void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 442int cayman_vm_init(struct radeon_device *rdev); 443void cayman_vm_fini(struct radeon_device *rdev); 444int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id); 445void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); 446void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm); 447uint32_t cayman_vm_page_flags(struct radeon_device *rdev, 448 struct radeon_vm *vm, 449 uint32_t flags); 450void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm, 451 unsigned pfn, uint64_t addr, uint32_t flags); 452int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 453 454#endif 455