1/* ------------------------------------------------------------------------- */
2/* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c         */
3/* ------------------------------------------------------------------------- */
4/*   Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 *                      <Peter dot Milne at D hyphen TACQ dot com>
6
7    This program is free software; you can redistribute it and/or modify
8    it under the terms of the GNU General Public License as published by
9    the Free Software Foundation, version 2.
10
11    This program is distributed in the hope that it will be useful,
12    but WITHOUT ANY WARRANTY; without even the implied warranty of
13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14    GNU General Public License for more details.
15
16    You should have received a copy of the GNU General Public License
17    along with this program; if not, write to the Free Software
18    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
19/* ------------------------------------------------------------------------- */
20
21
22#ifndef I2C_IOP3XX_H
23#define I2C_IOP3XX_H 1
24
25/*
26 * iop321 hardware bit definitions
27 */
28#define IOP3XX_ICR_FAST_MODE	0x8000	/* 1=400kBps, 0=100kBps */
29#define IOP3XX_ICR_UNIT_RESET	0x4000	/* 1=RESET */
30#define IOP3XX_ICR_SAD_IE	0x2000	/* 1=Slave Detect Interrupt Enable */
31#define IOP3XX_ICR_ALD_IE	0x1000	/* 1=Arb Loss Detect Interrupt Enable */
32#define IOP3XX_ICR_SSD_IE	0x0800	/* 1=Slave STOP Detect Interrupt Enable */
33#define IOP3XX_ICR_BERR_IE	0x0400	/* 1=Bus Error Interrupt Enable */
34#define IOP3XX_ICR_RXFULL_IE	0x0200	/* 1=Receive Full Interrupt Enable */
35#define IOP3XX_ICR_TXEMPTY_IE	0x0100	/* 1=Transmit Empty Interrupt Enable */
36#define IOP3XX_ICR_GCD		0x0080	/* 1=General Call Disable */
37/*
38 * IOP3XX_ICR_GCD: 1 disables response as slave. "This bit must be set
39 * when sending a master mode general call message from the I2C unit"
40 */
41#define IOP3XX_ICR_UE		0x0040	/* 1=Unit Enable */
42/*
43 * "NOTE: To avoid I2C bus integrity problems,
44 * the user needs to ensure that the GPIO Output Data Register -
45 * GPOD bits associated with an I2C port are cleared prior to setting
46 * the enable bit for that I2C serial port.
47 * The user prepares to enable I2C port 0 and
48 * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
49 */
50#define IOP3XX_ICR_SCLEN	0x0020	/* 1=SCL enable for master mode */
51#define IOP3XX_ICR_MABORT	0x0010	/* 1=Send a STOP with no data
52					 * NB TBYTE must be clear */
53#define IOP3XX_ICR_TBYTE	0x0008	/* 1=Send/Receive a byte. i2c clears */
54#define IOP3XX_ICR_NACK		0x0004	/* 1=reply with NACK */
55#define IOP3XX_ICR_MSTOP	0x0002	/* 1=send a STOP after next data byte */
56#define IOP3XX_ICR_MSTART	0x0001	/* 1=initiate a START */
57
58
59#define IOP3XX_ISR_BERRD	0x0400	/* 1=BUS ERROR Detected */
60#define IOP3XX_ISR_SAD		0x0200	/* 1=Slave ADdress Detected */
61#define IOP3XX_ISR_GCAD		0x0100	/* 1=General Call Address Detected */
62#define IOP3XX_ISR_RXFULL	0x0080	/* 1=Receive Full */
63#define IOP3XX_ISR_TXEMPTY	0x0040	/* 1=Transmit Empty */
64#define IOP3XX_ISR_ALD		0x0020	/* 1=Arbitration Loss Detected */
65#define IOP3XX_ISR_SSD		0x0010	/* 1=Slave STOP Detected */
66#define IOP3XX_ISR_BBUSY	0x0008	/* 1=Bus BUSY */
67#define IOP3XX_ISR_UNITBUSY	0x0004	/* 1=Unit Busy */
68#define IOP3XX_ISR_NACK		0x0002	/* 1=Unit Rx or Tx a NACK */
69#define IOP3XX_ISR_RXREAD	0x0001	/* 1=READ 0=WRITE (R/W bit of slave addr */
70
71#define IOP3XX_ISR_CLEARBITS	0x07f0
72
73#define IOP3XX_ISAR_SAMASK	0x007f
74
75#define IOP3XX_IDBR_MASK	0x00ff
76
77#define IOP3XX_IBMR_SCL		0x0002
78#define IOP3XX_IBMR_SDA		0x0001
79
80#define IOP3XX_GPOD_I2C0	0x00c0	/* clear these bits to enable ch0 */
81#define IOP3XX_GPOD_I2C1	0x0030	/* clear these bits to enable ch1 */
82
83#define MYSAR			0	/* default slave address */
84
85#define I2C_ERR			321
86#define I2C_ERR_BERR		(I2C_ERR+0)
87#define I2C_ERR_ALD		(I2C_ERR+1)
88
89
90#define	CR_OFFSET		0
91#define	SR_OFFSET		0x4
92#define	SAR_OFFSET		0x8
93#define	DBR_OFFSET		0xc
94#define	CCR_OFFSET		0x10
95#define	BMR_OFFSET		0x14
96
97#define	IOP3XX_I2C_IO_SIZE	0x18
98
99struct i2c_algo_iop3xx_data {
100	void __iomem *ioaddr;
101	wait_queue_head_t waitq;
102	spinlock_t lock;
103	u32 SR_enabled, SR_received;
104	int id;
105};
106
107#endif /* I2C_IOP3XX_H */
108