1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15#include <linux/delay.h> 16#include <linux/highmem.h> 17#include <linux/module.h> 18#include <linux/pci.h> 19#include <linux/dma-mapping.h> 20#include <linux/slab.h> 21#include <linux/device.h> 22#include <linux/mmc/host.h> 23#include <linux/scatterlist.h> 24#include <linux/io.h> 25#include <linux/gpio.h> 26#include <linux/pm_runtime.h> 27#include <linux/mmc/sdhci-pci-data.h> 28 29#include "sdhci.h" 30 31/* 32 * PCI registers 33 */ 34 35#define PCI_SDHCI_IFPIO 0x00 36#define PCI_SDHCI_IFDMA 0x01 37#define PCI_SDHCI_IFVENDOR 0x02 38 39#define PCI_SLOT_INFO 0x40 /* 8 bits */ 40#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 41#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 42 43#define MAX_SLOTS 8 44 45struct sdhci_pci_chip; 46struct sdhci_pci_slot; 47 48struct sdhci_pci_fixes { 49 unsigned int quirks; 50 bool allow_runtime_pm; 51 52 int (*probe) (struct sdhci_pci_chip *); 53 54 int (*probe_slot) (struct sdhci_pci_slot *); 55 void (*remove_slot) (struct sdhci_pci_slot *, int); 56 57 int (*suspend) (struct sdhci_pci_chip *); 58 int (*resume) (struct sdhci_pci_chip *); 59}; 60 61struct sdhci_pci_slot { 62 struct sdhci_pci_chip *chip; 63 struct sdhci_host *host; 64 struct sdhci_pci_data *data; 65 66 int pci_bar; 67 int rst_n_gpio; 68 int cd_gpio; 69 int cd_irq; 70}; 71 72struct sdhci_pci_chip { 73 struct pci_dev *pdev; 74 75 unsigned int quirks; 76 bool allow_runtime_pm; 77 const struct sdhci_pci_fixes *fixes; 78 79 int num_slots; /* Slots on controller */ 80 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 81}; 82 83 84/*****************************************************************************\ 85 * * 86 * Hardware specific quirk handling * 87 * * 88\*****************************************************************************/ 89 90static int ricoh_probe(struct sdhci_pci_chip *chip) 91{ 92 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 93 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 94 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 95 return 0; 96} 97 98static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 99{ 100 slot->host->caps = 101 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 102 & SDHCI_TIMEOUT_CLK_MASK) | 103 104 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 105 & SDHCI_CLOCK_BASE_MASK) | 106 107 SDHCI_TIMEOUT_CLK_UNIT | 108 SDHCI_CAN_VDD_330 | 109 SDHCI_CAN_DO_SDMA; 110 return 0; 111} 112 113static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 114{ 115 /* Apply a delay to allow controller to settle */ 116 /* Otherwise it becomes confused if card state changed 117 during suspend */ 118 msleep(500); 119 return 0; 120} 121 122static const struct sdhci_pci_fixes sdhci_ricoh = { 123 .probe = ricoh_probe, 124 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 125 SDHCI_QUIRK_FORCE_DMA | 126 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 127}; 128 129static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 130 .probe_slot = ricoh_mmc_probe_slot, 131 .resume = ricoh_mmc_resume, 132 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 133 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 134 SDHCI_QUIRK_NO_CARD_NO_RESET | 135 SDHCI_QUIRK_MISSING_CAPS 136}; 137 138static const struct sdhci_pci_fixes sdhci_ene_712 = { 139 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 140 SDHCI_QUIRK_BROKEN_DMA, 141}; 142 143static const struct sdhci_pci_fixes sdhci_ene_714 = { 144 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 145 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 146 SDHCI_QUIRK_BROKEN_DMA, 147}; 148 149static const struct sdhci_pci_fixes sdhci_cafe = { 150 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 151 SDHCI_QUIRK_NO_BUSY_IRQ | 152 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 153}; 154 155static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 156{ 157 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 158 return 0; 159} 160 161/* 162 * ADMA operation is disabled for Moorestown platform due to 163 * hardware bugs. 164 */ 165static int mrst_hc_probe(struct sdhci_pci_chip *chip) 166{ 167 /* 168 * slots number is fixed here for MRST as SDIO3/5 are never used and 169 * have hardware bugs. 170 */ 171 chip->num_slots = 1; 172 return 0; 173} 174 175#ifdef CONFIG_PM_RUNTIME 176 177static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 178{ 179 struct sdhci_pci_slot *slot = dev_id; 180 struct sdhci_host *host = slot->host; 181 182 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 183 return IRQ_HANDLED; 184} 185 186static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 187{ 188 int err, irq, gpio = slot->cd_gpio; 189 190 slot->cd_gpio = -EINVAL; 191 slot->cd_irq = -EINVAL; 192 193 if (!gpio_is_valid(gpio)) 194 return; 195 196 err = gpio_request(gpio, "sd_cd"); 197 if (err < 0) 198 goto out; 199 200 err = gpio_direction_input(gpio); 201 if (err < 0) 202 goto out_free; 203 204 irq = gpio_to_irq(gpio); 205 if (irq < 0) 206 goto out_free; 207 208 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 209 IRQF_TRIGGER_FALLING, "sd_cd", slot); 210 if (err) 211 goto out_free; 212 213 slot->cd_gpio = gpio; 214 slot->cd_irq = irq; 215 216 return; 217 218out_free: 219 gpio_free(gpio); 220out: 221 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 222} 223 224static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 225{ 226 if (slot->cd_irq >= 0) 227 free_irq(slot->cd_irq, slot); 228 if (gpio_is_valid(slot->cd_gpio)) 229 gpio_free(slot->cd_gpio); 230} 231 232#else 233 234static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 235{ 236} 237 238static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 239{ 240} 241 242#endif 243 244static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 245{ 246 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 247 slot->host->mmc->caps2 = MMC_CAP2_BOOTPART_NOACC; 248 return 0; 249} 250 251static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 252{ 253 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 254 return 0; 255} 256 257static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 259 .probe_slot = mrst_hc_probe_slot, 260}; 261 262static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 263 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 264 .probe = mrst_hc_probe, 265}; 266 267static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 268 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 269 .allow_runtime_pm = true, 270}; 271 272static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 273 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 274 .allow_runtime_pm = true, 275 .probe_slot = mfd_sdio_probe_slot, 276}; 277 278static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 279 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 280 .allow_runtime_pm = true, 281 .probe_slot = mfd_emmc_probe_slot, 282}; 283 284/* O2Micro extra registers */ 285#define O2_SD_LOCK_WP 0xD3 286#define O2_SD_MULTI_VCC3V 0xEE 287#define O2_SD_CLKREQ 0xEC 288#define O2_SD_CAPS 0xE0 289#define O2_SD_ADMA1 0xE2 290#define O2_SD_ADMA2 0xE7 291#define O2_SD_INF_MOD 0xF1 292 293static int o2_probe(struct sdhci_pci_chip *chip) 294{ 295 int ret; 296 u8 scratch; 297 298 switch (chip->pdev->device) { 299 case PCI_DEVICE_ID_O2_8220: 300 case PCI_DEVICE_ID_O2_8221: 301 case PCI_DEVICE_ID_O2_8320: 302 case PCI_DEVICE_ID_O2_8321: 303 /* This extra setup is required due to broken ADMA. */ 304 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 305 if (ret) 306 return ret; 307 scratch &= 0x7f; 308 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 309 310 /* Set Multi 3 to VCC3V# */ 311 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 312 313 /* Disable CLK_REQ# support after media DET */ 314 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); 315 if (ret) 316 return ret; 317 scratch |= 0x20; 318 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 319 320 /* Choose capabilities, enable SDMA. We have to write 0x01 321 * to the capabilities register first to unlock it. 322 */ 323 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 324 if (ret) 325 return ret; 326 scratch |= 0x01; 327 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 328 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 329 330 /* Disable ADMA1/2 */ 331 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 332 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 333 334 /* Disable the infinite transfer mode */ 335 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); 336 if (ret) 337 return ret; 338 scratch |= 0x08; 339 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 340 341 /* Lock WP */ 342 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 343 if (ret) 344 return ret; 345 scratch |= 0x80; 346 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 347 } 348 349 return 0; 350} 351 352static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 353{ 354 u8 scratch; 355 int ret; 356 357 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 358 if (ret) 359 return ret; 360 361 /* 362 * Turn PMOS on [bit 0], set over current detection to 2.4 V 363 * [bit 1:2] and enable over current debouncing [bit 6]. 364 */ 365 if (on) 366 scratch |= 0x47; 367 else 368 scratch &= ~0x47; 369 370 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); 371 if (ret) 372 return ret; 373 374 return 0; 375} 376 377static int jmicron_probe(struct sdhci_pci_chip *chip) 378{ 379 int ret; 380 u16 mmcdev = 0; 381 382 if (chip->pdev->revision == 0) { 383 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 384 SDHCI_QUIRK_32BIT_DMA_SIZE | 385 SDHCI_QUIRK_32BIT_ADMA_SIZE | 386 SDHCI_QUIRK_RESET_AFTER_REQUEST | 387 SDHCI_QUIRK_BROKEN_SMALL_PIO; 388 } 389 390 /* 391 * JMicron chips can have two interfaces to the same hardware 392 * in order to work around limitations in Microsoft's driver. 393 * We need to make sure we only bind to one of them. 394 * 395 * This code assumes two things: 396 * 397 * 1. The PCI code adds subfunctions in order. 398 * 399 * 2. The MMC interface has a lower subfunction number 400 * than the SD interface. 401 */ 402 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 403 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 404 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 405 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 406 407 if (mmcdev) { 408 struct pci_dev *sd_dev; 409 410 sd_dev = NULL; 411 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 412 mmcdev, sd_dev)) != NULL) { 413 if ((PCI_SLOT(chip->pdev->devfn) == 414 PCI_SLOT(sd_dev->devfn)) && 415 (chip->pdev->bus == sd_dev->bus)) 416 break; 417 } 418 419 if (sd_dev) { 420 pci_dev_put(sd_dev); 421 dev_info(&chip->pdev->dev, "Refusing to bind to " 422 "secondary interface.\n"); 423 return -ENODEV; 424 } 425 } 426 427 /* 428 * JMicron chips need a bit of a nudge to enable the power 429 * output pins. 430 */ 431 ret = jmicron_pmos(chip, 1); 432 if (ret) { 433 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 434 return ret; 435 } 436 437 /* quirk for unsable RO-detection on JM388 chips */ 438 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 439 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 440 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 441 442 return 0; 443} 444 445static void jmicron_enable_mmc(struct sdhci_host *host, int on) 446{ 447 u8 scratch; 448 449 scratch = readb(host->ioaddr + 0xC0); 450 451 if (on) 452 scratch |= 0x01; 453 else 454 scratch &= ~0x01; 455 456 writeb(scratch, host->ioaddr + 0xC0); 457} 458 459static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 460{ 461 if (slot->chip->pdev->revision == 0) { 462 u16 version; 463 464 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 465 version = (version & SDHCI_VENDOR_VER_MASK) >> 466 SDHCI_VENDOR_VER_SHIFT; 467 468 /* 469 * Older versions of the chip have lots of nasty glitches 470 * in the ADMA engine. It's best just to avoid it 471 * completely. 472 */ 473 if (version < 0xAC) 474 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 475 } 476 477 /* JM388 MMC doesn't support 1.8V while SD supports it */ 478 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 479 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 480 MMC_VDD_29_30 | MMC_VDD_30_31 | 481 MMC_VDD_165_195; /* allow 1.8V */ 482 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 483 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 484 } 485 486 /* 487 * The secondary interface requires a bit set to get the 488 * interrupts. 489 */ 490 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 491 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 492 jmicron_enable_mmc(slot->host, 1); 493 494 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 495 496 return 0; 497} 498 499static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 500{ 501 if (dead) 502 return; 503 504 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 505 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 506 jmicron_enable_mmc(slot->host, 0); 507} 508 509static int jmicron_suspend(struct sdhci_pci_chip *chip) 510{ 511 int i; 512 513 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 514 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 515 for (i = 0; i < chip->num_slots; i++) 516 jmicron_enable_mmc(chip->slots[i]->host, 0); 517 } 518 519 return 0; 520} 521 522static int jmicron_resume(struct sdhci_pci_chip *chip) 523{ 524 int ret, i; 525 526 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 527 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 528 for (i = 0; i < chip->num_slots; i++) 529 jmicron_enable_mmc(chip->slots[i]->host, 1); 530 } 531 532 ret = jmicron_pmos(chip, 1); 533 if (ret) { 534 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 535 return ret; 536 } 537 538 return 0; 539} 540 541static const struct sdhci_pci_fixes sdhci_o2 = { 542 .probe = o2_probe, 543}; 544 545static const struct sdhci_pci_fixes sdhci_jmicron = { 546 .probe = jmicron_probe, 547 548 .probe_slot = jmicron_probe_slot, 549 .remove_slot = jmicron_remove_slot, 550 551 .suspend = jmicron_suspend, 552 .resume = jmicron_resume, 553}; 554 555/* SysKonnect CardBus2SDIO extra registers */ 556#define SYSKT_CTRL 0x200 557#define SYSKT_RDFIFO_STAT 0x204 558#define SYSKT_WRFIFO_STAT 0x208 559#define SYSKT_POWER_DATA 0x20c 560#define SYSKT_POWER_330 0xef 561#define SYSKT_POWER_300 0xf8 562#define SYSKT_POWER_184 0xcc 563#define SYSKT_POWER_CMD 0x20d 564#define SYSKT_POWER_START (1 << 7) 565#define SYSKT_POWER_STATUS 0x20e 566#define SYSKT_POWER_STATUS_OK (1 << 0) 567#define SYSKT_BOARD_REV 0x210 568#define SYSKT_CHIP_REV 0x211 569#define SYSKT_CONF_DATA 0x212 570#define SYSKT_CONF_DATA_1V8 (1 << 2) 571#define SYSKT_CONF_DATA_2V5 (1 << 1) 572#define SYSKT_CONF_DATA_3V3 (1 << 0) 573 574static int syskt_probe(struct sdhci_pci_chip *chip) 575{ 576 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 577 chip->pdev->class &= ~0x0000FF; 578 chip->pdev->class |= PCI_SDHCI_IFDMA; 579 } 580 return 0; 581} 582 583static int syskt_probe_slot(struct sdhci_pci_slot *slot) 584{ 585 int tm, ps; 586 587 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 588 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 589 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 590 "board rev %d.%d, chip rev %d.%d\n", 591 board_rev >> 4, board_rev & 0xf, 592 chip_rev >> 4, chip_rev & 0xf); 593 if (chip_rev >= 0x20) 594 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 595 596 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 597 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 598 udelay(50); 599 tm = 10; /* Wait max 1 ms */ 600 do { 601 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 602 if (ps & SYSKT_POWER_STATUS_OK) 603 break; 604 udelay(100); 605 } while (--tm); 606 if (!tm) { 607 dev_err(&slot->chip->pdev->dev, 608 "power regulator never stabilized"); 609 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 610 return -ENODEV; 611 } 612 613 return 0; 614} 615 616static const struct sdhci_pci_fixes sdhci_syskt = { 617 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 618 .probe = syskt_probe, 619 .probe_slot = syskt_probe_slot, 620}; 621 622static int via_probe(struct sdhci_pci_chip *chip) 623{ 624 if (chip->pdev->revision == 0x10) 625 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 626 627 return 0; 628} 629 630static const struct sdhci_pci_fixes sdhci_via = { 631 .probe = via_probe, 632}; 633 634static const struct pci_device_id pci_ids[] __devinitdata = { 635 { 636 .vendor = PCI_VENDOR_ID_RICOH, 637 .device = PCI_DEVICE_ID_RICOH_R5C822, 638 .subvendor = PCI_ANY_ID, 639 .subdevice = PCI_ANY_ID, 640 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 641 }, 642 643 { 644 .vendor = PCI_VENDOR_ID_RICOH, 645 .device = 0x843, 646 .subvendor = PCI_ANY_ID, 647 .subdevice = PCI_ANY_ID, 648 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 649 }, 650 651 { 652 .vendor = PCI_VENDOR_ID_RICOH, 653 .device = 0xe822, 654 .subvendor = PCI_ANY_ID, 655 .subdevice = PCI_ANY_ID, 656 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 657 }, 658 659 { 660 .vendor = PCI_VENDOR_ID_RICOH, 661 .device = 0xe823, 662 .subvendor = PCI_ANY_ID, 663 .subdevice = PCI_ANY_ID, 664 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 665 }, 666 667 { 668 .vendor = PCI_VENDOR_ID_ENE, 669 .device = PCI_DEVICE_ID_ENE_CB712_SD, 670 .subvendor = PCI_ANY_ID, 671 .subdevice = PCI_ANY_ID, 672 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 673 }, 674 675 { 676 .vendor = PCI_VENDOR_ID_ENE, 677 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 678 .subvendor = PCI_ANY_ID, 679 .subdevice = PCI_ANY_ID, 680 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 681 }, 682 683 { 684 .vendor = PCI_VENDOR_ID_ENE, 685 .device = PCI_DEVICE_ID_ENE_CB714_SD, 686 .subvendor = PCI_ANY_ID, 687 .subdevice = PCI_ANY_ID, 688 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 689 }, 690 691 { 692 .vendor = PCI_VENDOR_ID_ENE, 693 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 694 .subvendor = PCI_ANY_ID, 695 .subdevice = PCI_ANY_ID, 696 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 697 }, 698 699 { 700 .vendor = PCI_VENDOR_ID_MARVELL, 701 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 702 .subvendor = PCI_ANY_ID, 703 .subdevice = PCI_ANY_ID, 704 .driver_data = (kernel_ulong_t)&sdhci_cafe, 705 }, 706 707 { 708 .vendor = PCI_VENDOR_ID_JMICRON, 709 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 710 .subvendor = PCI_ANY_ID, 711 .subdevice = PCI_ANY_ID, 712 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 713 }, 714 715 { 716 .vendor = PCI_VENDOR_ID_JMICRON, 717 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 718 .subvendor = PCI_ANY_ID, 719 .subdevice = PCI_ANY_ID, 720 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 721 }, 722 723 { 724 .vendor = PCI_VENDOR_ID_JMICRON, 725 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 726 .subvendor = PCI_ANY_ID, 727 .subdevice = PCI_ANY_ID, 728 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 729 }, 730 731 { 732 .vendor = PCI_VENDOR_ID_JMICRON, 733 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 734 .subvendor = PCI_ANY_ID, 735 .subdevice = PCI_ANY_ID, 736 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 737 }, 738 739 { 740 .vendor = PCI_VENDOR_ID_SYSKONNECT, 741 .device = 0x8000, 742 .subvendor = PCI_ANY_ID, 743 .subdevice = PCI_ANY_ID, 744 .driver_data = (kernel_ulong_t)&sdhci_syskt, 745 }, 746 747 { 748 .vendor = PCI_VENDOR_ID_VIA, 749 .device = 0x95d0, 750 .subvendor = PCI_ANY_ID, 751 .subdevice = PCI_ANY_ID, 752 .driver_data = (kernel_ulong_t)&sdhci_via, 753 }, 754 755 { 756 .vendor = PCI_VENDOR_ID_INTEL, 757 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 758 .subvendor = PCI_ANY_ID, 759 .subdevice = PCI_ANY_ID, 760 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 761 }, 762 763 { 764 .vendor = PCI_VENDOR_ID_INTEL, 765 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 766 .subvendor = PCI_ANY_ID, 767 .subdevice = PCI_ANY_ID, 768 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 769 }, 770 771 { 772 .vendor = PCI_VENDOR_ID_INTEL, 773 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 774 .subvendor = PCI_ANY_ID, 775 .subdevice = PCI_ANY_ID, 776 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 777 }, 778 779 { 780 .vendor = PCI_VENDOR_ID_INTEL, 781 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 782 .subvendor = PCI_ANY_ID, 783 .subdevice = PCI_ANY_ID, 784 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 785 }, 786 787 { 788 .vendor = PCI_VENDOR_ID_INTEL, 789 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 790 .subvendor = PCI_ANY_ID, 791 .subdevice = PCI_ANY_ID, 792 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 793 }, 794 795 { 796 .vendor = PCI_VENDOR_ID_INTEL, 797 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 798 .subvendor = PCI_ANY_ID, 799 .subdevice = PCI_ANY_ID, 800 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 801 }, 802 803 { 804 .vendor = PCI_VENDOR_ID_INTEL, 805 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 806 .subvendor = PCI_ANY_ID, 807 .subdevice = PCI_ANY_ID, 808 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 809 }, 810 811 { 812 .vendor = PCI_VENDOR_ID_INTEL, 813 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 814 .subvendor = PCI_ANY_ID, 815 .subdevice = PCI_ANY_ID, 816 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 817 }, 818 819 { 820 .vendor = PCI_VENDOR_ID_O2, 821 .device = PCI_DEVICE_ID_O2_8120, 822 .subvendor = PCI_ANY_ID, 823 .subdevice = PCI_ANY_ID, 824 .driver_data = (kernel_ulong_t)&sdhci_o2, 825 }, 826 827 { 828 .vendor = PCI_VENDOR_ID_O2, 829 .device = PCI_DEVICE_ID_O2_8220, 830 .subvendor = PCI_ANY_ID, 831 .subdevice = PCI_ANY_ID, 832 .driver_data = (kernel_ulong_t)&sdhci_o2, 833 }, 834 835 { 836 .vendor = PCI_VENDOR_ID_O2, 837 .device = PCI_DEVICE_ID_O2_8221, 838 .subvendor = PCI_ANY_ID, 839 .subdevice = PCI_ANY_ID, 840 .driver_data = (kernel_ulong_t)&sdhci_o2, 841 }, 842 843 { 844 .vendor = PCI_VENDOR_ID_O2, 845 .device = PCI_DEVICE_ID_O2_8320, 846 .subvendor = PCI_ANY_ID, 847 .subdevice = PCI_ANY_ID, 848 .driver_data = (kernel_ulong_t)&sdhci_o2, 849 }, 850 851 { 852 .vendor = PCI_VENDOR_ID_O2, 853 .device = PCI_DEVICE_ID_O2_8321, 854 .subvendor = PCI_ANY_ID, 855 .subdevice = PCI_ANY_ID, 856 .driver_data = (kernel_ulong_t)&sdhci_o2, 857 }, 858 859 { /* Generic SD host controller */ 860 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 861 }, 862 863 { /* end: all zeroes */ }, 864}; 865 866MODULE_DEVICE_TABLE(pci, pci_ids); 867 868/*****************************************************************************\ 869 * * 870 * SDHCI core callbacks * 871 * * 872\*****************************************************************************/ 873 874static int sdhci_pci_enable_dma(struct sdhci_host *host) 875{ 876 struct sdhci_pci_slot *slot; 877 struct pci_dev *pdev; 878 int ret; 879 880 slot = sdhci_priv(host); 881 pdev = slot->chip->pdev; 882 883 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 884 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 885 (host->flags & SDHCI_USE_SDMA)) { 886 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 887 "doesn't fully claim to support it.\n"); 888 } 889 890 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 891 if (ret) 892 return ret; 893 894 pci_set_master(pdev); 895 896 return 0; 897} 898 899static int sdhci_pci_8bit_width(struct sdhci_host *host, int width) 900{ 901 u8 ctrl; 902 903 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 904 905 switch (width) { 906 case MMC_BUS_WIDTH_8: 907 ctrl |= SDHCI_CTRL_8BITBUS; 908 ctrl &= ~SDHCI_CTRL_4BITBUS; 909 break; 910 case MMC_BUS_WIDTH_4: 911 ctrl |= SDHCI_CTRL_4BITBUS; 912 ctrl &= ~SDHCI_CTRL_8BITBUS; 913 break; 914 default: 915 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 916 break; 917 } 918 919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 920 921 return 0; 922} 923 924static void sdhci_pci_hw_reset(struct sdhci_host *host) 925{ 926 struct sdhci_pci_slot *slot = sdhci_priv(host); 927 int rst_n_gpio = slot->rst_n_gpio; 928 929 if (!gpio_is_valid(rst_n_gpio)) 930 return; 931 gpio_set_value_cansleep(rst_n_gpio, 0); 932 /* For eMMC, minimum is 1us but give it 10us for good measure */ 933 udelay(10); 934 gpio_set_value_cansleep(rst_n_gpio, 1); 935 /* For eMMC, minimum is 200us but give it 300us for good measure */ 936 usleep_range(300, 1000); 937} 938 939static struct sdhci_ops sdhci_pci_ops = { 940 .enable_dma = sdhci_pci_enable_dma, 941 .platform_8bit_width = sdhci_pci_8bit_width, 942 .hw_reset = sdhci_pci_hw_reset, 943}; 944 945/*****************************************************************************\ 946 * * 947 * Suspend/resume * 948 * * 949\*****************************************************************************/ 950 951#ifdef CONFIG_PM 952 953static int sdhci_pci_suspend(struct device *dev) 954{ 955 struct pci_dev *pdev = to_pci_dev(dev); 956 struct sdhci_pci_chip *chip; 957 struct sdhci_pci_slot *slot; 958 mmc_pm_flag_t slot_pm_flags; 959 mmc_pm_flag_t pm_flags = 0; 960 int i, ret; 961 962 chip = pci_get_drvdata(pdev); 963 if (!chip) 964 return 0; 965 966 for (i = 0; i < chip->num_slots; i++) { 967 slot = chip->slots[i]; 968 if (!slot) 969 continue; 970 971 ret = sdhci_suspend_host(slot->host); 972 973 if (ret) 974 goto err_pci_suspend; 975 976 slot_pm_flags = slot->host->mmc->pm_flags; 977 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 978 sdhci_enable_irq_wakeups(slot->host); 979 980 pm_flags |= slot_pm_flags; 981 } 982 983 if (chip->fixes && chip->fixes->suspend) { 984 ret = chip->fixes->suspend(chip); 985 if (ret) 986 goto err_pci_suspend; 987 } 988 989 pci_save_state(pdev); 990 if (pm_flags & MMC_PM_KEEP_POWER) { 991 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) { 992 pci_pme_active(pdev, true); 993 pci_enable_wake(pdev, PCI_D3hot, 1); 994 } 995 pci_set_power_state(pdev, PCI_D3hot); 996 } else { 997 pci_enable_wake(pdev, PCI_D3hot, 0); 998 pci_disable_device(pdev); 999 pci_set_power_state(pdev, PCI_D3hot); 1000 } 1001 1002 return 0; 1003 1004err_pci_suspend: 1005 while (--i >= 0) 1006 sdhci_resume_host(chip->slots[i]->host); 1007 return ret; 1008} 1009 1010static int sdhci_pci_resume(struct device *dev) 1011{ 1012 struct pci_dev *pdev = to_pci_dev(dev); 1013 struct sdhci_pci_chip *chip; 1014 struct sdhci_pci_slot *slot; 1015 int i, ret; 1016 1017 chip = pci_get_drvdata(pdev); 1018 if (!chip) 1019 return 0; 1020 1021 pci_set_power_state(pdev, PCI_D0); 1022 pci_restore_state(pdev); 1023 ret = pci_enable_device(pdev); 1024 if (ret) 1025 return ret; 1026 1027 if (chip->fixes && chip->fixes->resume) { 1028 ret = chip->fixes->resume(chip); 1029 if (ret) 1030 return ret; 1031 } 1032 1033 for (i = 0; i < chip->num_slots; i++) { 1034 slot = chip->slots[i]; 1035 if (!slot) 1036 continue; 1037 1038 ret = sdhci_resume_host(slot->host); 1039 if (ret) 1040 return ret; 1041 } 1042 1043 return 0; 1044} 1045 1046#else /* CONFIG_PM */ 1047 1048#define sdhci_pci_suspend NULL 1049#define sdhci_pci_resume NULL 1050 1051#endif /* CONFIG_PM */ 1052 1053#ifdef CONFIG_PM_RUNTIME 1054 1055static int sdhci_pci_runtime_suspend(struct device *dev) 1056{ 1057 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 1058 struct sdhci_pci_chip *chip; 1059 struct sdhci_pci_slot *slot; 1060 int i, ret; 1061 1062 chip = pci_get_drvdata(pdev); 1063 if (!chip) 1064 return 0; 1065 1066 for (i = 0; i < chip->num_slots; i++) { 1067 slot = chip->slots[i]; 1068 if (!slot) 1069 continue; 1070 1071 ret = sdhci_runtime_suspend_host(slot->host); 1072 1073 if (ret) 1074 goto err_pci_runtime_suspend; 1075 } 1076 1077 if (chip->fixes && chip->fixes->suspend) { 1078 ret = chip->fixes->suspend(chip); 1079 if (ret) 1080 goto err_pci_runtime_suspend; 1081 } 1082 1083 return 0; 1084 1085err_pci_runtime_suspend: 1086 while (--i >= 0) 1087 sdhci_runtime_resume_host(chip->slots[i]->host); 1088 return ret; 1089} 1090 1091static int sdhci_pci_runtime_resume(struct device *dev) 1092{ 1093 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 1094 struct sdhci_pci_chip *chip; 1095 struct sdhci_pci_slot *slot; 1096 int i, ret; 1097 1098 chip = pci_get_drvdata(pdev); 1099 if (!chip) 1100 return 0; 1101 1102 if (chip->fixes && chip->fixes->resume) { 1103 ret = chip->fixes->resume(chip); 1104 if (ret) 1105 return ret; 1106 } 1107 1108 for (i = 0; i < chip->num_slots; i++) { 1109 slot = chip->slots[i]; 1110 if (!slot) 1111 continue; 1112 1113 ret = sdhci_runtime_resume_host(slot->host); 1114 if (ret) 1115 return ret; 1116 } 1117 1118 return 0; 1119} 1120 1121static int sdhci_pci_runtime_idle(struct device *dev) 1122{ 1123 return 0; 1124} 1125 1126#else 1127 1128#define sdhci_pci_runtime_suspend NULL 1129#define sdhci_pci_runtime_resume NULL 1130#define sdhci_pci_runtime_idle NULL 1131 1132#endif 1133 1134static const struct dev_pm_ops sdhci_pci_pm_ops = { 1135 .suspend = sdhci_pci_suspend, 1136 .resume = sdhci_pci_resume, 1137 .runtime_suspend = sdhci_pci_runtime_suspend, 1138 .runtime_resume = sdhci_pci_runtime_resume, 1139 .runtime_idle = sdhci_pci_runtime_idle, 1140}; 1141 1142/*****************************************************************************\ 1143 * * 1144 * Device probing/removal * 1145 * * 1146\*****************************************************************************/ 1147 1148static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot( 1149 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1150 int slotno) 1151{ 1152 struct sdhci_pci_slot *slot; 1153 struct sdhci_host *host; 1154 int ret, bar = first_bar + slotno; 1155 1156 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1157 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1158 return ERR_PTR(-ENODEV); 1159 } 1160 1161 if (pci_resource_len(pdev, bar) != 0x100) { 1162 dev_err(&pdev->dev, "Invalid iomem size. You may " 1163 "experience problems.\n"); 1164 } 1165 1166 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1167 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1168 return ERR_PTR(-ENODEV); 1169 } 1170 1171 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1172 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1173 return ERR_PTR(-ENODEV); 1174 } 1175 1176 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1177 if (IS_ERR(host)) { 1178 dev_err(&pdev->dev, "cannot allocate host\n"); 1179 return ERR_CAST(host); 1180 } 1181 1182 slot = sdhci_priv(host); 1183 1184 slot->chip = chip; 1185 slot->host = host; 1186 slot->pci_bar = bar; 1187 slot->rst_n_gpio = -EINVAL; 1188 slot->cd_gpio = -EINVAL; 1189 1190 /* Retrieve platform data if there is any */ 1191 if (*sdhci_pci_get_data) 1192 slot->data = sdhci_pci_get_data(pdev, slotno); 1193 1194 if (slot->data) { 1195 if (slot->data->setup) { 1196 ret = slot->data->setup(slot->data); 1197 if (ret) { 1198 dev_err(&pdev->dev, "platform setup failed\n"); 1199 goto free; 1200 } 1201 } 1202 slot->rst_n_gpio = slot->data->rst_n_gpio; 1203 slot->cd_gpio = slot->data->cd_gpio; 1204 } 1205 1206 host->hw_name = "PCI"; 1207 host->ops = &sdhci_pci_ops; 1208 host->quirks = chip->quirks; 1209 1210 host->irq = pdev->irq; 1211 1212 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); 1213 if (ret) { 1214 dev_err(&pdev->dev, "cannot request region\n"); 1215 goto cleanup; 1216 } 1217 1218 host->ioaddr = pci_ioremap_bar(pdev, bar); 1219 if (!host->ioaddr) { 1220 dev_err(&pdev->dev, "failed to remap registers\n"); 1221 ret = -ENOMEM; 1222 goto release; 1223 } 1224 1225 if (chip->fixes && chip->fixes->probe_slot) { 1226 ret = chip->fixes->probe_slot(slot); 1227 if (ret) 1228 goto unmap; 1229 } 1230 1231 if (gpio_is_valid(slot->rst_n_gpio)) { 1232 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) { 1233 gpio_direction_output(slot->rst_n_gpio, 1); 1234 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1235 } else { 1236 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1237 slot->rst_n_gpio = -EINVAL; 1238 } 1239 } 1240 1241 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1242 1243 ret = sdhci_add_host(host); 1244 if (ret) 1245 goto remove; 1246 1247 sdhci_pci_add_own_cd(slot); 1248 1249 return slot; 1250 1251remove: 1252 if (gpio_is_valid(slot->rst_n_gpio)) 1253 gpio_free(slot->rst_n_gpio); 1254 1255 if (chip->fixes && chip->fixes->remove_slot) 1256 chip->fixes->remove_slot(slot, 0); 1257 1258unmap: 1259 iounmap(host->ioaddr); 1260 1261release: 1262 pci_release_region(pdev, bar); 1263 1264cleanup: 1265 if (slot->data && slot->data->cleanup) 1266 slot->data->cleanup(slot->data); 1267 1268free: 1269 sdhci_free_host(host); 1270 1271 return ERR_PTR(ret); 1272} 1273 1274static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1275{ 1276 int dead; 1277 u32 scratch; 1278 1279 sdhci_pci_remove_own_cd(slot); 1280 1281 dead = 0; 1282 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1283 if (scratch == (u32)-1) 1284 dead = 1; 1285 1286 sdhci_remove_host(slot->host, dead); 1287 1288 if (gpio_is_valid(slot->rst_n_gpio)) 1289 gpio_free(slot->rst_n_gpio); 1290 1291 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1292 slot->chip->fixes->remove_slot(slot, dead); 1293 1294 if (slot->data && slot->data->cleanup) 1295 slot->data->cleanup(slot->data); 1296 1297 pci_release_region(slot->chip->pdev, slot->pci_bar); 1298 1299 sdhci_free_host(slot->host); 1300} 1301 1302static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev) 1303{ 1304 pm_runtime_put_noidle(dev); 1305 pm_runtime_allow(dev); 1306 pm_runtime_set_autosuspend_delay(dev, 50); 1307 pm_runtime_use_autosuspend(dev); 1308 pm_suspend_ignore_children(dev, 1); 1309} 1310 1311static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev) 1312{ 1313 pm_runtime_forbid(dev); 1314 pm_runtime_get_noresume(dev); 1315} 1316 1317static int __devinit sdhci_pci_probe(struct pci_dev *pdev, 1318 const struct pci_device_id *ent) 1319{ 1320 struct sdhci_pci_chip *chip; 1321 struct sdhci_pci_slot *slot; 1322 1323 u8 slots, first_bar; 1324 int ret, i; 1325 1326 BUG_ON(pdev == NULL); 1327 BUG_ON(ent == NULL); 1328 1329 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1330 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1331 1332 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1333 if (ret) 1334 return ret; 1335 1336 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1337 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1338 if (slots == 0) 1339 return -ENODEV; 1340 1341 BUG_ON(slots > MAX_SLOTS); 1342 1343 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1344 if (ret) 1345 return ret; 1346 1347 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1348 1349 if (first_bar > 5) { 1350 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1351 return -ENODEV; 1352 } 1353 1354 ret = pci_enable_device(pdev); 1355 if (ret) 1356 return ret; 1357 1358 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); 1359 if (!chip) { 1360 ret = -ENOMEM; 1361 goto err; 1362 } 1363 1364 chip->pdev = pdev; 1365 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1366 if (chip->fixes) { 1367 chip->quirks = chip->fixes->quirks; 1368 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1369 } 1370 chip->num_slots = slots; 1371 1372 pci_set_drvdata(pdev, chip); 1373 1374 if (chip->fixes && chip->fixes->probe) { 1375 ret = chip->fixes->probe(chip); 1376 if (ret) 1377 goto free; 1378 } 1379 1380 slots = chip->num_slots; /* Quirk may have changed this */ 1381 1382 for (i = 0; i < slots; i++) { 1383 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1384 if (IS_ERR(slot)) { 1385 for (i--; i >= 0; i--) 1386 sdhci_pci_remove_slot(chip->slots[i]); 1387 ret = PTR_ERR(slot); 1388 goto free; 1389 } 1390 1391 chip->slots[i] = slot; 1392 } 1393 1394 if (chip->allow_runtime_pm) 1395 sdhci_pci_runtime_pm_allow(&pdev->dev); 1396 1397 return 0; 1398 1399free: 1400 pci_set_drvdata(pdev, NULL); 1401 kfree(chip); 1402 1403err: 1404 pci_disable_device(pdev); 1405 return ret; 1406} 1407 1408static void __devexit sdhci_pci_remove(struct pci_dev *pdev) 1409{ 1410 int i; 1411 struct sdhci_pci_chip *chip; 1412 1413 chip = pci_get_drvdata(pdev); 1414 1415 if (chip) { 1416 if (chip->allow_runtime_pm) 1417 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1418 1419 for (i = 0; i < chip->num_slots; i++) 1420 sdhci_pci_remove_slot(chip->slots[i]); 1421 1422 pci_set_drvdata(pdev, NULL); 1423 kfree(chip); 1424 } 1425 1426 pci_disable_device(pdev); 1427} 1428 1429static struct pci_driver sdhci_driver = { 1430 .name = "sdhci-pci", 1431 .id_table = pci_ids, 1432 .probe = sdhci_pci_probe, 1433 .remove = __devexit_p(sdhci_pci_remove), 1434 .driver = { 1435 .pm = &sdhci_pci_pm_ops 1436 }, 1437}; 1438 1439/*****************************************************************************\ 1440 * * 1441 * Driver init/exit * 1442 * * 1443\*****************************************************************************/ 1444 1445static int __init sdhci_drv_init(void) 1446{ 1447 return pci_register_driver(&sdhci_driver); 1448} 1449 1450static void __exit sdhci_drv_exit(void) 1451{ 1452 pci_unregister_driver(&sdhci_driver); 1453} 1454 1455module_init(sdhci_drv_init); 1456module_exit(sdhci_drv_exit); 1457 1458MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1459MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1460MODULE_LICENSE("GPL"); 1461