1/* 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18/* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30}; 31 32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45}; 46 47#define CQE_FLAGS_VALID_MASK (1 << 31) 48#define CQE_FLAGS_ASYNC_MASK (1 << 30) 49#define CQE_FLAGS_COMPLETED_MASK (1 << 28) 50#define CQE_FLAGS_CONSUMED_MASK (1 << 27) 51 52/* Completion Status */ 53enum { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66 61}; 62 63#define CQE_STATUS_COMPL_MASK 0xFFFF 64#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ 65#define CQE_STATUS_EXTD_MASK 0xFFFF 66#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */ 67 68struct be_mcc_compl { 69 u32 status; /* dword 0 */ 70 u32 tag0; /* dword 1 */ 71 u32 tag1; /* dword 2 */ 72 u32 flags; /* dword 3 */ 73}; 74 75/* When the async bit of mcc_compl is set, the last 4 bytes of 76 * mcc_compl is interpreted as follows: 77 */ 78#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 79#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF 80#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16 81#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF 82#define ASYNC_EVENT_CODE_LINK_STATE 0x1 83#define ASYNC_EVENT_CODE_GRP_5 0x5 84#define ASYNC_EVENT_QOS_SPEED 0x1 85#define ASYNC_EVENT_COS_PRIORITY 0x2 86#define ASYNC_EVENT_PVID_STATE 0x3 87struct be_async_event_trailer { 88 u32 code; 89}; 90 91enum { 92 LINK_DOWN = 0x0, 93 LINK_UP = 0x1 94}; 95#define LINK_STATUS_MASK 0x1 96 97/* When the event code of an async trailer is link-state, the mcc_compl 98 * must be interpreted as follows 99 */ 100struct be_async_event_link_state { 101 u8 physical_port; 102 u8 port_link_status; 103 u8 port_duplex; 104 u8 port_speed; 105 u8 port_fault; 106 u8 rsvd0[7]; 107 struct be_async_event_trailer trailer; 108} __packed; 109 110/* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED 111 * the mcc_compl must be interpreted as follows 112 */ 113struct be_async_event_grp5_qos_link_speed { 114 u8 physical_port; 115 u8 rsvd[5]; 116 u16 qos_link_speed; 117 u32 event_tag; 118 struct be_async_event_trailer trailer; 119} __packed; 120 121/* When the event code of an async trailer is GRP5 and event type is 122 * CoS-Priority, the mcc_compl must be interpreted as follows 123 */ 124struct be_async_event_grp5_cos_priority { 125 u8 physical_port; 126 u8 available_priority_bmap; 127 u8 reco_default_priority; 128 u8 valid; 129 u8 rsvd0; 130 u8 event_tag; 131 struct be_async_event_trailer trailer; 132} __packed; 133 134/* When the event code of an async trailer is GRP5 and event type is 135 * PVID state, the mcc_compl must be interpreted as follows 136 */ 137struct be_async_event_grp5_pvid_state { 138 u8 enabled; 139 u8 rsvd0; 140 u16 tag; 141 u32 event_tag; 142 u32 rsvd1; 143 struct be_async_event_trailer trailer; 144} __packed; 145 146struct be_mcc_mailbox { 147 struct be_mcc_wrb wrb; 148 struct be_mcc_compl compl; 149}; 150 151#define CMD_SUBSYSTEM_COMMON 0x1 152#define CMD_SUBSYSTEM_ETH 0x3 153#define CMD_SUBSYSTEM_LOWLEVEL 0xb 154 155#define OPCODE_COMMON_NTWK_MAC_QUERY 1 156#define OPCODE_COMMON_NTWK_MAC_SET 2 157#define OPCODE_COMMON_NTWK_MULTICAST_SET 3 158#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 159#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 160#define OPCODE_COMMON_READ_FLASHROM 6 161#define OPCODE_COMMON_WRITE_FLASHROM 7 162#define OPCODE_COMMON_CQ_CREATE 12 163#define OPCODE_COMMON_EQ_CREATE 13 164#define OPCODE_COMMON_MCC_CREATE 21 165#define OPCODE_COMMON_SET_QOS 28 166#define OPCODE_COMMON_MCC_CREATE_EXT 90 167#define OPCODE_COMMON_SEEPROM_READ 30 168#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 169#define OPCODE_COMMON_NTWK_RX_FILTER 34 170#define OPCODE_COMMON_GET_FW_VERSION 35 171#define OPCODE_COMMON_SET_FLOW_CONTROL 36 172#define OPCODE_COMMON_GET_FLOW_CONTROL 37 173#define OPCODE_COMMON_SET_FRAME_SIZE 39 174#define OPCODE_COMMON_MODIFY_EQ_DELAY 41 175#define OPCODE_COMMON_FIRMWARE_CONFIG 42 176#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 177#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 178#define OPCODE_COMMON_MCC_DESTROY 53 179#define OPCODE_COMMON_CQ_DESTROY 54 180#define OPCODE_COMMON_EQ_DESTROY 55 181#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 182#define OPCODE_COMMON_NTWK_PMAC_ADD 59 183#define OPCODE_COMMON_NTWK_PMAC_DEL 60 184#define OPCODE_COMMON_FUNCTION_RESET 61 185#define OPCODE_COMMON_MANAGE_FAT 68 186#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 187#define OPCODE_COMMON_GET_BEACON_STATE 70 188#define OPCODE_COMMON_READ_TRANSRECV_DATA 73 189#define OPCODE_COMMON_GET_PHY_DETAILS 102 190#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 191#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 192#define OPCODE_COMMON_GET_MAC_LIST 147 193#define OPCODE_COMMON_SET_MAC_LIST 148 194#define OPCODE_COMMON_READ_OBJECT 171 195#define OPCODE_COMMON_WRITE_OBJECT 172 196 197#define OPCODE_ETH_RSS_CONFIG 1 198#define OPCODE_ETH_ACPI_CONFIG 2 199#define OPCODE_ETH_PROMISCUOUS 3 200#define OPCODE_ETH_GET_STATISTICS 4 201#define OPCODE_ETH_TX_CREATE 7 202#define OPCODE_ETH_RX_CREATE 8 203#define OPCODE_ETH_TX_DESTROY 9 204#define OPCODE_ETH_RX_DESTROY 10 205#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 206#define OPCODE_ETH_GET_PPORT_STATS 18 207 208#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 209#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 210#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 211 212struct be_cmd_req_hdr { 213 u8 opcode; /* dword 0 */ 214 u8 subsystem; /* dword 0 */ 215 u8 port_number; /* dword 0 */ 216 u8 domain; /* dword 0 */ 217 u32 timeout; /* dword 1 */ 218 u32 request_length; /* dword 2 */ 219 u8 version; /* dword 3 */ 220 u8 rsvd[3]; /* dword 3 */ 221}; 222 223#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 224#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 225struct be_cmd_resp_hdr { 226 u32 info; /* dword 0 */ 227 u32 status; /* dword 1 */ 228 u32 response_length; /* dword 2 */ 229 u32 actual_resp_len; /* dword 3 */ 230}; 231 232struct phys_addr { 233 u32 lo; 234 u32 hi; 235}; 236 237/************************** 238 * BE Command definitions * 239 **************************/ 240 241/* Pseudo amap definition in which each bit of the actual structure is defined 242 * as a byte: used to calculate offset/shift/mask of each field */ 243struct amap_eq_context { 244 u8 cidx[13]; /* dword 0*/ 245 u8 rsvd0[3]; /* dword 0*/ 246 u8 epidx[13]; /* dword 0*/ 247 u8 valid; /* dword 0*/ 248 u8 rsvd1; /* dword 0*/ 249 u8 size; /* dword 0*/ 250 u8 pidx[13]; /* dword 1*/ 251 u8 rsvd2[3]; /* dword 1*/ 252 u8 pd[10]; /* dword 1*/ 253 u8 count[3]; /* dword 1*/ 254 u8 solevent; /* dword 1*/ 255 u8 stalled; /* dword 1*/ 256 u8 armed; /* dword 1*/ 257 u8 rsvd3[4]; /* dword 2*/ 258 u8 func[8]; /* dword 2*/ 259 u8 rsvd4; /* dword 2*/ 260 u8 delaymult[10]; /* dword 2*/ 261 u8 rsvd5[2]; /* dword 2*/ 262 u8 phase[2]; /* dword 2*/ 263 u8 nodelay; /* dword 2*/ 264 u8 rsvd6[4]; /* dword 2*/ 265 u8 rsvd7[32]; /* dword 3*/ 266} __packed; 267 268struct be_cmd_req_eq_create { 269 struct be_cmd_req_hdr hdr; 270 u16 num_pages; /* sword */ 271 u16 rsvd0; /* sword */ 272 u8 context[sizeof(struct amap_eq_context) / 8]; 273 struct phys_addr pages[8]; 274} __packed; 275 276struct be_cmd_resp_eq_create { 277 struct be_cmd_resp_hdr resp_hdr; 278 u16 eq_id; /* sword */ 279 u16 rsvd0; /* sword */ 280} __packed; 281 282/******************** Mac query ***************************/ 283enum { 284 MAC_ADDRESS_TYPE_STORAGE = 0x0, 285 MAC_ADDRESS_TYPE_NETWORK = 0x1, 286 MAC_ADDRESS_TYPE_PD = 0x2, 287 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 288}; 289 290struct mac_addr { 291 u16 size_of_struct; 292 u8 addr[ETH_ALEN]; 293} __packed; 294 295struct be_cmd_req_mac_query { 296 struct be_cmd_req_hdr hdr; 297 u8 type; 298 u8 permanent; 299 u16 if_id; 300 u32 pmac_id; 301} __packed; 302 303struct be_cmd_resp_mac_query { 304 struct be_cmd_resp_hdr hdr; 305 struct mac_addr mac; 306}; 307 308/******************** PMac Add ***************************/ 309struct be_cmd_req_pmac_add { 310 struct be_cmd_req_hdr hdr; 311 u32 if_id; 312 u8 mac_address[ETH_ALEN]; 313 u8 rsvd0[2]; 314} __packed; 315 316struct be_cmd_resp_pmac_add { 317 struct be_cmd_resp_hdr hdr; 318 u32 pmac_id; 319}; 320 321/******************** PMac Del ***************************/ 322struct be_cmd_req_pmac_del { 323 struct be_cmd_req_hdr hdr; 324 u32 if_id; 325 u32 pmac_id; 326}; 327 328/******************** Create CQ ***************************/ 329/* Pseudo amap definition in which each bit of the actual structure is defined 330 * as a byte: used to calculate offset/shift/mask of each field */ 331struct amap_cq_context_be { 332 u8 cidx[11]; /* dword 0*/ 333 u8 rsvd0; /* dword 0*/ 334 u8 coalescwm[2]; /* dword 0*/ 335 u8 nodelay; /* dword 0*/ 336 u8 epidx[11]; /* dword 0*/ 337 u8 rsvd1; /* dword 0*/ 338 u8 count[2]; /* dword 0*/ 339 u8 valid; /* dword 0*/ 340 u8 solevent; /* dword 0*/ 341 u8 eventable; /* dword 0*/ 342 u8 pidx[11]; /* dword 1*/ 343 u8 rsvd2; /* dword 1*/ 344 u8 pd[10]; /* dword 1*/ 345 u8 eqid[8]; /* dword 1*/ 346 u8 stalled; /* dword 1*/ 347 u8 armed; /* dword 1*/ 348 u8 rsvd3[4]; /* dword 2*/ 349 u8 func[8]; /* dword 2*/ 350 u8 rsvd4[20]; /* dword 2*/ 351 u8 rsvd5[32]; /* dword 3*/ 352} __packed; 353 354struct amap_cq_context_lancer { 355 u8 rsvd0[12]; /* dword 0*/ 356 u8 coalescwm[2]; /* dword 0*/ 357 u8 nodelay; /* dword 0*/ 358 u8 rsvd1[12]; /* dword 0*/ 359 u8 count[2]; /* dword 0*/ 360 u8 valid; /* dword 0*/ 361 u8 rsvd2; /* dword 0*/ 362 u8 eventable; /* dword 0*/ 363 u8 eqid[16]; /* dword 1*/ 364 u8 rsvd3[15]; /* dword 1*/ 365 u8 armed; /* dword 1*/ 366 u8 rsvd4[32]; /* dword 2*/ 367 u8 rsvd5[32]; /* dword 3*/ 368} __packed; 369 370struct be_cmd_req_cq_create { 371 struct be_cmd_req_hdr hdr; 372 u16 num_pages; 373 u8 page_size; 374 u8 rsvd0; 375 u8 context[sizeof(struct amap_cq_context_be) / 8]; 376 struct phys_addr pages[8]; 377} __packed; 378 379 380struct be_cmd_resp_cq_create { 381 struct be_cmd_resp_hdr hdr; 382 u16 cq_id; 383 u16 rsvd0; 384} __packed; 385 386struct be_cmd_req_get_fat { 387 struct be_cmd_req_hdr hdr; 388 u32 fat_operation; 389 u32 read_log_offset; 390 u32 read_log_length; 391 u32 data_buffer_size; 392 u32 data_buffer[1]; 393} __packed; 394 395struct be_cmd_resp_get_fat { 396 struct be_cmd_resp_hdr hdr; 397 u32 log_size; 398 u32 read_log_length; 399 u32 rsvd[2]; 400 u32 data_buffer[1]; 401} __packed; 402 403 404/******************** Create MCCQ ***************************/ 405/* Pseudo amap definition in which each bit of the actual structure is defined 406 * as a byte: used to calculate offset/shift/mask of each field */ 407struct amap_mcc_context_be { 408 u8 con_index[14]; 409 u8 rsvd0[2]; 410 u8 ring_size[4]; 411 u8 fetch_wrb; 412 u8 fetch_r2t; 413 u8 cq_id[10]; 414 u8 prod_index[14]; 415 u8 fid[8]; 416 u8 pdid[9]; 417 u8 valid; 418 u8 rsvd1[32]; 419 u8 rsvd2[32]; 420} __packed; 421 422struct amap_mcc_context_lancer { 423 u8 async_cq_id[16]; 424 u8 ring_size[4]; 425 u8 rsvd0[12]; 426 u8 rsvd1[31]; 427 u8 valid; 428 u8 async_cq_valid[1]; 429 u8 rsvd2[31]; 430 u8 rsvd3[32]; 431} __packed; 432 433struct be_cmd_req_mcc_create { 434 struct be_cmd_req_hdr hdr; 435 u16 num_pages; 436 u16 cq_id; 437 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 438 struct phys_addr pages[8]; 439} __packed; 440 441struct be_cmd_req_mcc_ext_create { 442 struct be_cmd_req_hdr hdr; 443 u16 num_pages; 444 u16 cq_id; 445 u32 async_event_bitmap[1]; 446 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 447 struct phys_addr pages[8]; 448} __packed; 449 450struct be_cmd_resp_mcc_create { 451 struct be_cmd_resp_hdr hdr; 452 u16 id; 453 u16 rsvd0; 454} __packed; 455 456/******************** Create TxQ ***************************/ 457#define BE_ETH_TX_RING_TYPE_STANDARD 2 458#define BE_ULP1_NUM 1 459 460/* Pseudo amap definition in which each bit of the actual structure is defined 461 * as a byte: used to calculate offset/shift/mask of each field */ 462struct amap_tx_context { 463 u8 if_id[16]; /* dword 0 */ 464 u8 tx_ring_size[4]; /* dword 0 */ 465 u8 rsvd1[26]; /* dword 0 */ 466 u8 pci_func_id[8]; /* dword 1 */ 467 u8 rsvd2[9]; /* dword 1 */ 468 u8 ctx_valid; /* dword 1 */ 469 u8 cq_id_send[16]; /* dword 2 */ 470 u8 rsvd3[16]; /* dword 2 */ 471 u8 rsvd4[32]; /* dword 3 */ 472 u8 rsvd5[32]; /* dword 4 */ 473 u8 rsvd6[32]; /* dword 5 */ 474 u8 rsvd7[32]; /* dword 6 */ 475 u8 rsvd8[32]; /* dword 7 */ 476 u8 rsvd9[32]; /* dword 8 */ 477 u8 rsvd10[32]; /* dword 9 */ 478 u8 rsvd11[32]; /* dword 10 */ 479 u8 rsvd12[32]; /* dword 11 */ 480 u8 rsvd13[32]; /* dword 12 */ 481 u8 rsvd14[32]; /* dword 13 */ 482 u8 rsvd15[32]; /* dword 14 */ 483 u8 rsvd16[32]; /* dword 15 */ 484} __packed; 485 486struct be_cmd_req_eth_tx_create { 487 struct be_cmd_req_hdr hdr; 488 u8 num_pages; 489 u8 ulp_num; 490 u8 type; 491 u8 bound_port; 492 u8 context[sizeof(struct amap_tx_context) / 8]; 493 struct phys_addr pages[8]; 494} __packed; 495 496struct be_cmd_resp_eth_tx_create { 497 struct be_cmd_resp_hdr hdr; 498 u16 cid; 499 u16 rsvd0; 500} __packed; 501 502/******************** Create RxQ ***************************/ 503struct be_cmd_req_eth_rx_create { 504 struct be_cmd_req_hdr hdr; 505 u16 cq_id; 506 u8 frag_size; 507 u8 num_pages; 508 struct phys_addr pages[2]; 509 u32 interface_id; 510 u16 max_frame_size; 511 u16 rsvd0; 512 u32 rss_queue; 513} __packed; 514 515struct be_cmd_resp_eth_rx_create { 516 struct be_cmd_resp_hdr hdr; 517 u16 id; 518 u8 rss_id; 519 u8 rsvd0; 520} __packed; 521 522/******************** Q Destroy ***************************/ 523/* Type of Queue to be destroyed */ 524enum { 525 QTYPE_EQ = 1, 526 QTYPE_CQ, 527 QTYPE_TXQ, 528 QTYPE_RXQ, 529 QTYPE_MCCQ 530}; 531 532struct be_cmd_req_q_destroy { 533 struct be_cmd_req_hdr hdr; 534 u16 id; 535 u16 bypass_flush; /* valid only for rx q destroy */ 536} __packed; 537 538/************ I/f Create (it's actually I/f Config Create)**********/ 539 540/* Capability flags for the i/f */ 541enum be_if_flags { 542 BE_IF_FLAGS_RSS = 0x4, 543 BE_IF_FLAGS_PROMISCUOUS = 0x8, 544 BE_IF_FLAGS_BROADCAST = 0x10, 545 BE_IF_FLAGS_UNTAGGED = 0x20, 546 BE_IF_FLAGS_ULP = 0x40, 547 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 548 BE_IF_FLAGS_VLAN = 0x100, 549 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 550 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 551 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 552 BE_IF_FLAGS_MULTICAST = 0x1000 553}; 554 555/* An RX interface is an object with one or more MAC addresses and 556 * filtering capabilities. */ 557struct be_cmd_req_if_create { 558 struct be_cmd_req_hdr hdr; 559 u32 version; /* ignore currently */ 560 u32 capability_flags; 561 u32 enable_flags; 562 u8 mac_addr[ETH_ALEN]; 563 u8 rsvd0; 564 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 565 u32 vlan_tag; /* not used currently */ 566} __packed; 567 568struct be_cmd_resp_if_create { 569 struct be_cmd_resp_hdr hdr; 570 u32 interface_id; 571 u32 pmac_id; 572}; 573 574/****** I/f Destroy(it's actually I/f Config Destroy )**********/ 575struct be_cmd_req_if_destroy { 576 struct be_cmd_req_hdr hdr; 577 u32 interface_id; 578}; 579 580/*************** HW Stats Get **********************************/ 581struct be_port_rxf_stats_v0 { 582 u32 rx_bytes_lsd; /* dword 0*/ 583 u32 rx_bytes_msd; /* dword 1*/ 584 u32 rx_total_frames; /* dword 2*/ 585 u32 rx_unicast_frames; /* dword 3*/ 586 u32 rx_multicast_frames; /* dword 4*/ 587 u32 rx_broadcast_frames; /* dword 5*/ 588 u32 rx_crc_errors; /* dword 6*/ 589 u32 rx_alignment_symbol_errors; /* dword 7*/ 590 u32 rx_pause_frames; /* dword 8*/ 591 u32 rx_control_frames; /* dword 9*/ 592 u32 rx_in_range_errors; /* dword 10*/ 593 u32 rx_out_range_errors; /* dword 11*/ 594 u32 rx_frame_too_long; /* dword 12*/ 595 u32 rx_address_match_errors; /* dword 13*/ 596 u32 rx_vlan_mismatch; /* dword 14*/ 597 u32 rx_dropped_too_small; /* dword 15*/ 598 u32 rx_dropped_too_short; /* dword 16*/ 599 u32 rx_dropped_header_too_small; /* dword 17*/ 600 u32 rx_dropped_tcp_length; /* dword 18*/ 601 u32 rx_dropped_runt; /* dword 19*/ 602 u32 rx_64_byte_packets; /* dword 20*/ 603 u32 rx_65_127_byte_packets; /* dword 21*/ 604 u32 rx_128_256_byte_packets; /* dword 22*/ 605 u32 rx_256_511_byte_packets; /* dword 23*/ 606 u32 rx_512_1023_byte_packets; /* dword 24*/ 607 u32 rx_1024_1518_byte_packets; /* dword 25*/ 608 u32 rx_1519_2047_byte_packets; /* dword 26*/ 609 u32 rx_2048_4095_byte_packets; /* dword 27*/ 610 u32 rx_4096_8191_byte_packets; /* dword 28*/ 611 u32 rx_8192_9216_byte_packets; /* dword 29*/ 612 u32 rx_ip_checksum_errs; /* dword 30*/ 613 u32 rx_tcp_checksum_errs; /* dword 31*/ 614 u32 rx_udp_checksum_errs; /* dword 32*/ 615 u32 rx_non_rss_packets; /* dword 33*/ 616 u32 rx_ipv4_packets; /* dword 34*/ 617 u32 rx_ipv6_packets; /* dword 35*/ 618 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 619 u32 rx_ipv4_bytes_msd; /* dword 37*/ 620 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 621 u32 rx_ipv6_bytes_msd; /* dword 39*/ 622 u32 rx_chute1_packets; /* dword 40*/ 623 u32 rx_chute2_packets; /* dword 41*/ 624 u32 rx_chute3_packets; /* dword 42*/ 625 u32 rx_management_packets; /* dword 43*/ 626 u32 rx_switched_unicast_packets; /* dword 44*/ 627 u32 rx_switched_multicast_packets; /* dword 45*/ 628 u32 rx_switched_broadcast_packets; /* dword 46*/ 629 u32 tx_bytes_lsd; /* dword 47*/ 630 u32 tx_bytes_msd; /* dword 48*/ 631 u32 tx_unicastframes; /* dword 49*/ 632 u32 tx_multicastframes; /* dword 50*/ 633 u32 tx_broadcastframes; /* dword 51*/ 634 u32 tx_pauseframes; /* dword 52*/ 635 u32 tx_controlframes; /* dword 53*/ 636 u32 tx_64_byte_packets; /* dword 54*/ 637 u32 tx_65_127_byte_packets; /* dword 55*/ 638 u32 tx_128_256_byte_packets; /* dword 56*/ 639 u32 tx_256_511_byte_packets; /* dword 57*/ 640 u32 tx_512_1023_byte_packets; /* dword 58*/ 641 u32 tx_1024_1518_byte_packets; /* dword 59*/ 642 u32 tx_1519_2047_byte_packets; /* dword 60*/ 643 u32 tx_2048_4095_byte_packets; /* dword 61*/ 644 u32 tx_4096_8191_byte_packets; /* dword 62*/ 645 u32 tx_8192_9216_byte_packets; /* dword 63*/ 646 u32 rx_fifo_overflow; /* dword 64*/ 647 u32 rx_input_fifo_overflow; /* dword 65*/ 648}; 649 650struct be_rxf_stats_v0 { 651 struct be_port_rxf_stats_v0 port[2]; 652 u32 rx_drops_no_pbuf; /* dword 132*/ 653 u32 rx_drops_no_txpb; /* dword 133*/ 654 u32 rx_drops_no_erx_descr; /* dword 134*/ 655 u32 rx_drops_no_tpre_descr; /* dword 135*/ 656 u32 management_rx_port_packets; /* dword 136*/ 657 u32 management_rx_port_bytes; /* dword 137*/ 658 u32 management_rx_port_pause_frames; /* dword 138*/ 659 u32 management_rx_port_errors; /* dword 139*/ 660 u32 management_tx_port_packets; /* dword 140*/ 661 u32 management_tx_port_bytes; /* dword 141*/ 662 u32 management_tx_port_pause; /* dword 142*/ 663 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 664 u32 rx_drops_too_many_frags; /* dword 144*/ 665 u32 rx_drops_invalid_ring; /* dword 145*/ 666 u32 forwarded_packets; /* dword 146*/ 667 u32 rx_drops_mtu; /* dword 147*/ 668 u32 rsvd0[7]; 669 u32 port0_jabber_events; 670 u32 port1_jabber_events; 671 u32 rsvd1[6]; 672}; 673 674struct be_erx_stats_v0 { 675 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 676 u32 rsvd[4]; 677}; 678 679struct be_pmem_stats { 680 u32 eth_red_drops; 681 u32 rsvd[5]; 682}; 683 684struct be_hw_stats_v0 { 685 struct be_rxf_stats_v0 rxf; 686 u32 rsvd[48]; 687 struct be_erx_stats_v0 erx; 688 struct be_pmem_stats pmem; 689}; 690 691struct be_cmd_req_get_stats_v0 { 692 struct be_cmd_req_hdr hdr; 693 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 694}; 695 696struct be_cmd_resp_get_stats_v0 { 697 struct be_cmd_resp_hdr hdr; 698 struct be_hw_stats_v0 hw_stats; 699}; 700 701struct lancer_pport_stats { 702 u32 tx_packets_lo; 703 u32 tx_packets_hi; 704 u32 tx_unicast_packets_lo; 705 u32 tx_unicast_packets_hi; 706 u32 tx_multicast_packets_lo; 707 u32 tx_multicast_packets_hi; 708 u32 tx_broadcast_packets_lo; 709 u32 tx_broadcast_packets_hi; 710 u32 tx_bytes_lo; 711 u32 tx_bytes_hi; 712 u32 tx_unicast_bytes_lo; 713 u32 tx_unicast_bytes_hi; 714 u32 tx_multicast_bytes_lo; 715 u32 tx_multicast_bytes_hi; 716 u32 tx_broadcast_bytes_lo; 717 u32 tx_broadcast_bytes_hi; 718 u32 tx_discards_lo; 719 u32 tx_discards_hi; 720 u32 tx_errors_lo; 721 u32 tx_errors_hi; 722 u32 tx_pause_frames_lo; 723 u32 tx_pause_frames_hi; 724 u32 tx_pause_on_frames_lo; 725 u32 tx_pause_on_frames_hi; 726 u32 tx_pause_off_frames_lo; 727 u32 tx_pause_off_frames_hi; 728 u32 tx_internal_mac_errors_lo; 729 u32 tx_internal_mac_errors_hi; 730 u32 tx_control_frames_lo; 731 u32 tx_control_frames_hi; 732 u32 tx_packets_64_bytes_lo; 733 u32 tx_packets_64_bytes_hi; 734 u32 tx_packets_65_to_127_bytes_lo; 735 u32 tx_packets_65_to_127_bytes_hi; 736 u32 tx_packets_128_to_255_bytes_lo; 737 u32 tx_packets_128_to_255_bytes_hi; 738 u32 tx_packets_256_to_511_bytes_lo; 739 u32 tx_packets_256_to_511_bytes_hi; 740 u32 tx_packets_512_to_1023_bytes_lo; 741 u32 tx_packets_512_to_1023_bytes_hi; 742 u32 tx_packets_1024_to_1518_bytes_lo; 743 u32 tx_packets_1024_to_1518_bytes_hi; 744 u32 tx_packets_1519_to_2047_bytes_lo; 745 u32 tx_packets_1519_to_2047_bytes_hi; 746 u32 tx_packets_2048_to_4095_bytes_lo; 747 u32 tx_packets_2048_to_4095_bytes_hi; 748 u32 tx_packets_4096_to_8191_bytes_lo; 749 u32 tx_packets_4096_to_8191_bytes_hi; 750 u32 tx_packets_8192_to_9216_bytes_lo; 751 u32 tx_packets_8192_to_9216_bytes_hi; 752 u32 tx_lso_packets_lo; 753 u32 tx_lso_packets_hi; 754 u32 rx_packets_lo; 755 u32 rx_packets_hi; 756 u32 rx_unicast_packets_lo; 757 u32 rx_unicast_packets_hi; 758 u32 rx_multicast_packets_lo; 759 u32 rx_multicast_packets_hi; 760 u32 rx_broadcast_packets_lo; 761 u32 rx_broadcast_packets_hi; 762 u32 rx_bytes_lo; 763 u32 rx_bytes_hi; 764 u32 rx_unicast_bytes_lo; 765 u32 rx_unicast_bytes_hi; 766 u32 rx_multicast_bytes_lo; 767 u32 rx_multicast_bytes_hi; 768 u32 rx_broadcast_bytes_lo; 769 u32 rx_broadcast_bytes_hi; 770 u32 rx_unknown_protos; 771 u32 rsvd_69; /* Word 69 is reserved */ 772 u32 rx_discards_lo; 773 u32 rx_discards_hi; 774 u32 rx_errors_lo; 775 u32 rx_errors_hi; 776 u32 rx_crc_errors_lo; 777 u32 rx_crc_errors_hi; 778 u32 rx_alignment_errors_lo; 779 u32 rx_alignment_errors_hi; 780 u32 rx_symbol_errors_lo; 781 u32 rx_symbol_errors_hi; 782 u32 rx_pause_frames_lo; 783 u32 rx_pause_frames_hi; 784 u32 rx_pause_on_frames_lo; 785 u32 rx_pause_on_frames_hi; 786 u32 rx_pause_off_frames_lo; 787 u32 rx_pause_off_frames_hi; 788 u32 rx_frames_too_long_lo; 789 u32 rx_frames_too_long_hi; 790 u32 rx_internal_mac_errors_lo; 791 u32 rx_internal_mac_errors_hi; 792 u32 rx_undersize_packets; 793 u32 rx_oversize_packets; 794 u32 rx_fragment_packets; 795 u32 rx_jabbers; 796 u32 rx_control_frames_lo; 797 u32 rx_control_frames_hi; 798 u32 rx_control_frames_unknown_opcode_lo; 799 u32 rx_control_frames_unknown_opcode_hi; 800 u32 rx_in_range_errors; 801 u32 rx_out_of_range_errors; 802 u32 rx_address_match_errors; 803 u32 rx_vlan_mismatch_errors; 804 u32 rx_dropped_too_small; 805 u32 rx_dropped_too_short; 806 u32 rx_dropped_header_too_small; 807 u32 rx_dropped_invalid_tcp_length; 808 u32 rx_dropped_runt; 809 u32 rx_ip_checksum_errors; 810 u32 rx_tcp_checksum_errors; 811 u32 rx_udp_checksum_errors; 812 u32 rx_non_rss_packets; 813 u32 rsvd_111; 814 u32 rx_ipv4_packets_lo; 815 u32 rx_ipv4_packets_hi; 816 u32 rx_ipv6_packets_lo; 817 u32 rx_ipv6_packets_hi; 818 u32 rx_ipv4_bytes_lo; 819 u32 rx_ipv4_bytes_hi; 820 u32 rx_ipv6_bytes_lo; 821 u32 rx_ipv6_bytes_hi; 822 u32 rx_nic_packets_lo; 823 u32 rx_nic_packets_hi; 824 u32 rx_tcp_packets_lo; 825 u32 rx_tcp_packets_hi; 826 u32 rx_iscsi_packets_lo; 827 u32 rx_iscsi_packets_hi; 828 u32 rx_management_packets_lo; 829 u32 rx_management_packets_hi; 830 u32 rx_switched_unicast_packets_lo; 831 u32 rx_switched_unicast_packets_hi; 832 u32 rx_switched_multicast_packets_lo; 833 u32 rx_switched_multicast_packets_hi; 834 u32 rx_switched_broadcast_packets_lo; 835 u32 rx_switched_broadcast_packets_hi; 836 u32 num_forwards_lo; 837 u32 num_forwards_hi; 838 u32 rx_fifo_overflow; 839 u32 rx_input_fifo_overflow; 840 u32 rx_drops_too_many_frags_lo; 841 u32 rx_drops_too_many_frags_hi; 842 u32 rx_drops_invalid_queue; 843 u32 rsvd_141; 844 u32 rx_drops_mtu_lo; 845 u32 rx_drops_mtu_hi; 846 u32 rx_packets_64_bytes_lo; 847 u32 rx_packets_64_bytes_hi; 848 u32 rx_packets_65_to_127_bytes_lo; 849 u32 rx_packets_65_to_127_bytes_hi; 850 u32 rx_packets_128_to_255_bytes_lo; 851 u32 rx_packets_128_to_255_bytes_hi; 852 u32 rx_packets_256_to_511_bytes_lo; 853 u32 rx_packets_256_to_511_bytes_hi; 854 u32 rx_packets_512_to_1023_bytes_lo; 855 u32 rx_packets_512_to_1023_bytes_hi; 856 u32 rx_packets_1024_to_1518_bytes_lo; 857 u32 rx_packets_1024_to_1518_bytes_hi; 858 u32 rx_packets_1519_to_2047_bytes_lo; 859 u32 rx_packets_1519_to_2047_bytes_hi; 860 u32 rx_packets_2048_to_4095_bytes_lo; 861 u32 rx_packets_2048_to_4095_bytes_hi; 862 u32 rx_packets_4096_to_8191_bytes_lo; 863 u32 rx_packets_4096_to_8191_bytes_hi; 864 u32 rx_packets_8192_to_9216_bytes_lo; 865 u32 rx_packets_8192_to_9216_bytes_hi; 866}; 867 868struct pport_stats_params { 869 u16 pport_num; 870 u8 rsvd; 871 u8 reset_stats; 872}; 873 874struct lancer_cmd_req_pport_stats { 875 struct be_cmd_req_hdr hdr; 876 union { 877 struct pport_stats_params params; 878 u8 rsvd[sizeof(struct lancer_pport_stats)]; 879 } cmd_params; 880}; 881 882struct lancer_cmd_resp_pport_stats { 883 struct be_cmd_resp_hdr hdr; 884 struct lancer_pport_stats pport_stats; 885}; 886 887static inline struct lancer_pport_stats* 888 pport_stats_from_cmd(struct be_adapter *adapter) 889{ 890 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 891 return &cmd->pport_stats; 892} 893 894struct be_cmd_req_get_cntl_addnl_attribs { 895 struct be_cmd_req_hdr hdr; 896 u8 rsvd[8]; 897}; 898 899struct be_cmd_resp_get_cntl_addnl_attribs { 900 struct be_cmd_resp_hdr hdr; 901 u16 ipl_file_number; 902 u8 ipl_file_version; 903 u8 rsvd0; 904 u8 on_die_temperature; /* in degrees centigrade*/ 905 u8 rsvd1[3]; 906}; 907 908struct be_cmd_req_vlan_config { 909 struct be_cmd_req_hdr hdr; 910 u8 interface_id; 911 u8 promiscuous; 912 u8 untagged; 913 u8 num_vlan; 914 u16 normal_vlan[64]; 915} __packed; 916 917/******************* RX FILTER ******************************/ 918#define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 919struct macaddr { 920 u8 byte[ETH_ALEN]; 921}; 922 923struct be_cmd_req_rx_filter { 924 struct be_cmd_req_hdr hdr; 925 u32 global_flags_mask; 926 u32 global_flags; 927 u32 if_flags_mask; 928 u32 if_flags; 929 u32 if_id; 930 u32 mcast_num; 931 struct macaddr mcast_mac[BE_MAX_MC]; 932}; 933 934/******************** Link Status Query *******************/ 935struct be_cmd_req_link_status { 936 struct be_cmd_req_hdr hdr; 937 u32 rsvd; 938}; 939 940enum { 941 PHY_LINK_DUPLEX_NONE = 0x0, 942 PHY_LINK_DUPLEX_HALF = 0x1, 943 PHY_LINK_DUPLEX_FULL = 0x2 944}; 945 946enum { 947 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 948 PHY_LINK_SPEED_10MBPS = 0x1, 949 PHY_LINK_SPEED_100MBPS = 0x2, 950 PHY_LINK_SPEED_1GBPS = 0x3, 951 PHY_LINK_SPEED_10GBPS = 0x4 952}; 953 954struct be_cmd_resp_link_status { 955 struct be_cmd_resp_hdr hdr; 956 u8 physical_port; 957 u8 mac_duplex; 958 u8 mac_speed; 959 u8 mac_fault; 960 u8 mgmt_mac_duplex; 961 u8 mgmt_mac_speed; 962 u16 link_speed; 963 u8 logical_link_status; 964 u8 rsvd1[3]; 965} __packed; 966 967/******************** Port Identification ***************************/ 968/* Identifies the type of port attached to NIC */ 969struct be_cmd_req_port_type { 970 struct be_cmd_req_hdr hdr; 971 u32 page_num; 972 u32 port; 973}; 974 975enum { 976 TR_PAGE_A0 = 0xa0, 977 TR_PAGE_A2 = 0xa2 978}; 979 980struct be_cmd_resp_port_type { 981 struct be_cmd_resp_hdr hdr; 982 u32 page_num; 983 u32 port; 984 struct data { 985 u8 identifier; 986 u8 identifier_ext; 987 u8 connector; 988 u8 transceiver[8]; 989 u8 rsvd0[3]; 990 u8 length_km; 991 u8 length_hm; 992 u8 length_om1; 993 u8 length_om2; 994 u8 length_cu; 995 u8 length_cu_m; 996 u8 vendor_name[16]; 997 u8 rsvd; 998 u8 vendor_oui[3]; 999 u8 vendor_pn[16]; 1000 u8 vendor_rev[4]; 1001 } data; 1002}; 1003 1004/******************** Get FW Version *******************/ 1005struct be_cmd_req_get_fw_version { 1006 struct be_cmd_req_hdr hdr; 1007 u8 rsvd0[FW_VER_LEN]; 1008 u8 rsvd1[FW_VER_LEN]; 1009} __packed; 1010 1011struct be_cmd_resp_get_fw_version { 1012 struct be_cmd_resp_hdr hdr; 1013 u8 firmware_version_string[FW_VER_LEN]; 1014 u8 fw_on_flash_version_string[FW_VER_LEN]; 1015} __packed; 1016 1017/******************** Set Flow Contrl *******************/ 1018struct be_cmd_req_set_flow_control { 1019 struct be_cmd_req_hdr hdr; 1020 u16 tx_flow_control; 1021 u16 rx_flow_control; 1022} __packed; 1023 1024/******************** Get Flow Contrl *******************/ 1025struct be_cmd_req_get_flow_control { 1026 struct be_cmd_req_hdr hdr; 1027 u32 rsvd; 1028}; 1029 1030struct be_cmd_resp_get_flow_control { 1031 struct be_cmd_resp_hdr hdr; 1032 u16 tx_flow_control; 1033 u16 rx_flow_control; 1034} __packed; 1035 1036/******************** Modify EQ Delay *******************/ 1037struct be_cmd_req_modify_eq_delay { 1038 struct be_cmd_req_hdr hdr; 1039 u32 num_eq; 1040 struct { 1041 u32 eq_id; 1042 u32 phase; 1043 u32 delay_multiplier; 1044 } delay[8]; 1045} __packed; 1046 1047struct be_cmd_resp_modify_eq_delay { 1048 struct be_cmd_resp_hdr hdr; 1049 u32 rsvd0; 1050} __packed; 1051 1052/******************** Get FW Config *******************/ 1053#define BE_FUNCTION_CAPS_RSS 0x2 1054/* The HW can come up in either of the following multi-channel modes 1055 * based on the skew/IPL. 1056 */ 1057#define FLEX10_MODE 0x400 1058#define VNIC_MODE 0x20000 1059#define UMC_ENABLED 0x1000000 1060struct be_cmd_req_query_fw_cfg { 1061 struct be_cmd_req_hdr hdr; 1062 u32 rsvd[31]; 1063}; 1064 1065struct be_cmd_resp_query_fw_cfg { 1066 struct be_cmd_resp_hdr hdr; 1067 u32 be_config_number; 1068 u32 asic_revision; 1069 u32 phys_port; 1070 u32 function_mode; 1071 u32 rsvd[26]; 1072 u32 function_caps; 1073}; 1074 1075/******************** RSS Config *******************/ 1076/* RSS types */ 1077#define RSS_ENABLE_NONE 0x0 1078#define RSS_ENABLE_IPV4 0x1 1079#define RSS_ENABLE_TCP_IPV4 0x2 1080#define RSS_ENABLE_IPV6 0x4 1081#define RSS_ENABLE_TCP_IPV6 0x8 1082 1083struct be_cmd_req_rss_config { 1084 struct be_cmd_req_hdr hdr; 1085 u32 if_id; 1086 u16 enable_rss; 1087 u16 cpu_table_size_log2; 1088 u32 hash[10]; 1089 u8 cpu_table[128]; 1090 u8 flush; 1091 u8 rsvd0[3]; 1092}; 1093 1094/******************** Port Beacon ***************************/ 1095 1096#define BEACON_STATE_ENABLED 0x1 1097#define BEACON_STATE_DISABLED 0x0 1098 1099struct be_cmd_req_enable_disable_beacon { 1100 struct be_cmd_req_hdr hdr; 1101 u8 port_num; 1102 u8 beacon_state; 1103 u8 beacon_duration; 1104 u8 status_duration; 1105} __packed; 1106 1107struct be_cmd_resp_enable_disable_beacon { 1108 struct be_cmd_resp_hdr resp_hdr; 1109 u32 rsvd0; 1110} __packed; 1111 1112struct be_cmd_req_get_beacon_state { 1113 struct be_cmd_req_hdr hdr; 1114 u8 port_num; 1115 u8 rsvd0; 1116 u16 rsvd1; 1117} __packed; 1118 1119struct be_cmd_resp_get_beacon_state { 1120 struct be_cmd_resp_hdr resp_hdr; 1121 u8 beacon_state; 1122 u8 rsvd0[3]; 1123} __packed; 1124 1125/****************** Firmware Flash ******************/ 1126struct flashrom_params { 1127 u32 op_code; 1128 u32 op_type; 1129 u32 data_buf_size; 1130 u32 offset; 1131 u8 data_buf[4]; 1132}; 1133 1134struct be_cmd_write_flashrom { 1135 struct be_cmd_req_hdr hdr; 1136 struct flashrom_params params; 1137}; 1138 1139/**************** Lancer Firmware Flash ************/ 1140struct amap_lancer_write_obj_context { 1141 u8 write_length[24]; 1142 u8 reserved1[7]; 1143 u8 eof; 1144} __packed; 1145 1146struct lancer_cmd_req_write_object { 1147 struct be_cmd_req_hdr hdr; 1148 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1149 u32 write_offset; 1150 u8 object_name[104]; 1151 u32 descriptor_count; 1152 u32 buf_len; 1153 u32 addr_low; 1154 u32 addr_high; 1155}; 1156 1157struct lancer_cmd_resp_write_object { 1158 u8 opcode; 1159 u8 subsystem; 1160 u8 rsvd1[2]; 1161 u8 status; 1162 u8 additional_status; 1163 u8 rsvd2[2]; 1164 u32 resp_len; 1165 u32 actual_resp_len; 1166 u32 actual_write_len; 1167}; 1168 1169/************************ Lancer Read FW info **************/ 1170#define LANCER_READ_FILE_CHUNK (32*1024) 1171#define LANCER_READ_FILE_EOF_MASK 0x80000000 1172 1173#define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1174#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1175#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1176 1177struct lancer_cmd_req_read_object { 1178 struct be_cmd_req_hdr hdr; 1179 u32 desired_read_len; 1180 u32 read_offset; 1181 u8 object_name[104]; 1182 u32 descriptor_count; 1183 u32 buf_len; 1184 u32 addr_low; 1185 u32 addr_high; 1186}; 1187 1188struct lancer_cmd_resp_read_object { 1189 u8 opcode; 1190 u8 subsystem; 1191 u8 rsvd1[2]; 1192 u8 status; 1193 u8 additional_status; 1194 u8 rsvd2[2]; 1195 u32 resp_len; 1196 u32 actual_resp_len; 1197 u32 actual_read_len; 1198 u32 eof; 1199}; 1200 1201/************************ WOL *******************************/ 1202struct be_cmd_req_acpi_wol_magic_config{ 1203 struct be_cmd_req_hdr hdr; 1204 u32 rsvd0[145]; 1205 u8 magic_mac[6]; 1206 u8 rsvd2[2]; 1207} __packed; 1208 1209/********************** LoopBack test *********************/ 1210struct be_cmd_req_loopback_test { 1211 struct be_cmd_req_hdr hdr; 1212 u32 loopback_type; 1213 u32 num_pkts; 1214 u64 pattern; 1215 u32 src_port; 1216 u32 dest_port; 1217 u32 pkt_size; 1218}; 1219 1220struct be_cmd_resp_loopback_test { 1221 struct be_cmd_resp_hdr resp_hdr; 1222 u32 status; 1223 u32 num_txfer; 1224 u32 num_rx; 1225 u32 miscomp_off; 1226 u32 ticks_compl; 1227}; 1228 1229struct be_cmd_req_set_lmode { 1230 struct be_cmd_req_hdr hdr; 1231 u8 src_port; 1232 u8 dest_port; 1233 u8 loopback_type; 1234 u8 loopback_state; 1235}; 1236 1237struct be_cmd_resp_set_lmode { 1238 struct be_cmd_resp_hdr resp_hdr; 1239 u8 rsvd0[4]; 1240}; 1241 1242/********************** DDR DMA test *********************/ 1243struct be_cmd_req_ddrdma_test { 1244 struct be_cmd_req_hdr hdr; 1245 u64 pattern; 1246 u32 byte_count; 1247 u32 rsvd0; 1248 u8 snd_buff[4096]; 1249 u8 rsvd1[4096]; 1250}; 1251 1252struct be_cmd_resp_ddrdma_test { 1253 struct be_cmd_resp_hdr hdr; 1254 u64 pattern; 1255 u32 byte_cnt; 1256 u32 snd_err; 1257 u8 rsvd0[4096]; 1258 u8 rcv_buff[4096]; 1259}; 1260 1261/*********************** SEEPROM Read ***********************/ 1262 1263#define BE_READ_SEEPROM_LEN 1024 1264struct be_cmd_req_seeprom_read { 1265 struct be_cmd_req_hdr hdr; 1266 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1267}; 1268 1269struct be_cmd_resp_seeprom_read { 1270 struct be_cmd_req_hdr hdr; 1271 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1272}; 1273 1274enum { 1275 PHY_TYPE_CX4_10GB = 0, 1276 PHY_TYPE_XFP_10GB, 1277 PHY_TYPE_SFP_1GB, 1278 PHY_TYPE_SFP_PLUS_10GB, 1279 PHY_TYPE_KR_10GB, 1280 PHY_TYPE_KX4_10GB, 1281 PHY_TYPE_BASET_10GB, 1282 PHY_TYPE_BASET_1GB, 1283 PHY_TYPE_DISABLED = 255 1284}; 1285 1286struct be_cmd_req_get_phy_info { 1287 struct be_cmd_req_hdr hdr; 1288 u8 rsvd0[24]; 1289}; 1290 1291struct be_phy_info { 1292 u16 phy_type; 1293 u16 interface_type; 1294 u32 misc_params; 1295 u32 future_use[4]; 1296}; 1297 1298struct be_cmd_resp_get_phy_info { 1299 struct be_cmd_req_hdr hdr; 1300 struct be_phy_info phy_info; 1301}; 1302 1303/*********************** Set QOS ***********************/ 1304 1305#define BE_QOS_BITS_NIC 1 1306 1307struct be_cmd_req_set_qos { 1308 struct be_cmd_req_hdr hdr; 1309 u32 valid_bits; 1310 u32 max_bps_nic; 1311 u32 rsvd[7]; 1312}; 1313 1314struct be_cmd_resp_set_qos { 1315 struct be_cmd_resp_hdr hdr; 1316 u32 rsvd; 1317}; 1318 1319/*********************** Controller Attributes ***********************/ 1320struct be_cmd_req_cntl_attribs { 1321 struct be_cmd_req_hdr hdr; 1322}; 1323 1324struct be_cmd_resp_cntl_attribs { 1325 struct be_cmd_resp_hdr hdr; 1326 struct mgmt_controller_attrib attribs; 1327}; 1328 1329/*********************** Set driver function ***********************/ 1330#define CAPABILITY_SW_TIMESTAMPS 2 1331#define CAPABILITY_BE3_NATIVE_ERX_API 4 1332 1333struct be_cmd_req_set_func_cap { 1334 struct be_cmd_req_hdr hdr; 1335 u32 valid_cap_flags; 1336 u32 cap_flags; 1337 u8 rsvd[212]; 1338}; 1339 1340struct be_cmd_resp_set_func_cap { 1341 struct be_cmd_resp_hdr hdr; 1342 u32 valid_cap_flags; 1343 u32 cap_flags; 1344 u8 rsvd[212]; 1345}; 1346 1347/******************** GET/SET_MACLIST **************************/ 1348#define BE_MAX_MAC 64 1349struct amap_get_mac_list_context { 1350 u8 macid[31]; 1351 u8 act; 1352} __packed; 1353 1354struct be_cmd_req_get_mac_list { 1355 struct be_cmd_req_hdr hdr; 1356 u32 rsvd; 1357} __packed; 1358 1359struct be_cmd_resp_get_mac_list { 1360 struct be_cmd_resp_hdr hdr; 1361 u8 mac_count; 1362 u8 rsvd1; 1363 u16 rsvd2; 1364 u8 context[sizeof(struct amap_get_mac_list_context) / 8][BE_MAX_MAC]; 1365} __packed; 1366 1367struct be_cmd_req_set_mac_list { 1368 struct be_cmd_req_hdr hdr; 1369 u8 mac_count; 1370 u8 rsvd1; 1371 u16 rsvd2; 1372 struct macaddr mac[BE_MAX_MAC]; 1373} __packed; 1374 1375/*************** HW Stats Get v1 **********************************/ 1376#define BE_TXP_SW_SZ 48 1377struct be_port_rxf_stats_v1 { 1378 u32 rsvd0[12]; 1379 u32 rx_crc_errors; 1380 u32 rx_alignment_symbol_errors; 1381 u32 rx_pause_frames; 1382 u32 rx_priority_pause_frames; 1383 u32 rx_control_frames; 1384 u32 rx_in_range_errors; 1385 u32 rx_out_range_errors; 1386 u32 rx_frame_too_long; 1387 u32 rx_address_match_errors; 1388 u32 rx_dropped_too_small; 1389 u32 rx_dropped_too_short; 1390 u32 rx_dropped_header_too_small; 1391 u32 rx_dropped_tcp_length; 1392 u32 rx_dropped_runt; 1393 u32 rsvd1[10]; 1394 u32 rx_ip_checksum_errs; 1395 u32 rx_tcp_checksum_errs; 1396 u32 rx_udp_checksum_errs; 1397 u32 rsvd2[7]; 1398 u32 rx_switched_unicast_packets; 1399 u32 rx_switched_multicast_packets; 1400 u32 rx_switched_broadcast_packets; 1401 u32 rsvd3[3]; 1402 u32 tx_pauseframes; 1403 u32 tx_priority_pauseframes; 1404 u32 tx_controlframes; 1405 u32 rsvd4[10]; 1406 u32 rxpp_fifo_overflow_drop; 1407 u32 rx_input_fifo_overflow_drop; 1408 u32 pmem_fifo_overflow_drop; 1409 u32 jabber_events; 1410 u32 rsvd5[3]; 1411}; 1412 1413 1414struct be_rxf_stats_v1 { 1415 struct be_port_rxf_stats_v1 port[4]; 1416 u32 rsvd0[2]; 1417 u32 rx_drops_no_pbuf; 1418 u32 rx_drops_no_txpb; 1419 u32 rx_drops_no_erx_descr; 1420 u32 rx_drops_no_tpre_descr; 1421 u32 rsvd1[6]; 1422 u32 rx_drops_too_many_frags; 1423 u32 rx_drops_invalid_ring; 1424 u32 forwarded_packets; 1425 u32 rx_drops_mtu; 1426 u32 rsvd2[14]; 1427}; 1428 1429struct be_erx_stats_v1 { 1430 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1431 u32 rsvd[4]; 1432}; 1433 1434struct be_hw_stats_v1 { 1435 struct be_rxf_stats_v1 rxf; 1436 u32 rsvd0[BE_TXP_SW_SZ]; 1437 struct be_erx_stats_v1 erx; 1438 struct be_pmem_stats pmem; 1439 u32 rsvd1[3]; 1440}; 1441 1442struct be_cmd_req_get_stats_v1 { 1443 struct be_cmd_req_hdr hdr; 1444 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 1445}; 1446 1447struct be_cmd_resp_get_stats_v1 { 1448 struct be_cmd_resp_hdr hdr; 1449 struct be_hw_stats_v1 hw_stats; 1450}; 1451 1452static inline void *hw_stats_from_cmd(struct be_adapter *adapter) 1453{ 1454 if (adapter->generation == BE_GEN3) { 1455 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va; 1456 1457 return &cmd->hw_stats; 1458 } else { 1459 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va; 1460 1461 return &cmd->hw_stats; 1462 } 1463} 1464 1465static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter) 1466{ 1467 if (adapter->generation == BE_GEN3) { 1468 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); 1469 1470 return &hw_stats->erx; 1471 } else { 1472 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); 1473 1474 return &hw_stats->erx; 1475 } 1476} 1477 1478extern int be_pci_fnum_get(struct be_adapter *adapter); 1479extern int be_cmd_POST(struct be_adapter *adapter); 1480extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 1481 u8 type, bool permanent, u32 if_handle, u32 pmac_id); 1482extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 1483 u32 if_id, u32 *pmac_id, u32 domain); 1484extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, 1485 int pmac_id, u32 domain); 1486extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, 1487 u32 en_flags, u8 *mac, u32 *if_handle, u32 *pmac_id, 1488 u32 domain); 1489extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, 1490 u32 domain); 1491extern int be_cmd_eq_create(struct be_adapter *adapter, 1492 struct be_queue_info *eq, int eq_delay); 1493extern int be_cmd_cq_create(struct be_adapter *adapter, 1494 struct be_queue_info *cq, struct be_queue_info *eq, 1495 bool sol_evts, bool no_delay, 1496 int num_cqe_dma_coalesce); 1497extern int be_cmd_mccq_create(struct be_adapter *adapter, 1498 struct be_queue_info *mccq, 1499 struct be_queue_info *cq); 1500extern int be_cmd_txq_create(struct be_adapter *adapter, 1501 struct be_queue_info *txq, 1502 struct be_queue_info *cq); 1503extern int be_cmd_rxq_create(struct be_adapter *adapter, 1504 struct be_queue_info *rxq, u16 cq_id, 1505 u16 frag_size, u16 max_frame_size, u32 if_id, 1506 u32 rss, u8 *rss_id); 1507extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1508 int type); 1509extern int be_cmd_rxq_destroy(struct be_adapter *adapter, 1510 struct be_queue_info *q); 1511extern int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, 1512 u16 *link_speed, u8 *link_status, u32 dom); 1513extern int be_cmd_reset(struct be_adapter *adapter); 1514extern int be_cmd_get_stats(struct be_adapter *adapter, 1515 struct be_dma_mem *nonemb_cmd); 1516extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1517 struct be_dma_mem *nonemb_cmd); 1518extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 1519 char *fw_on_flash); 1520 1521extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd); 1522extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, 1523 u16 *vtag_array, u32 num, bool untagged, 1524 bool promiscuous); 1525extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 1526extern int be_cmd_set_flow_control(struct be_adapter *adapter, 1527 u32 tx_fc, u32 rx_fc); 1528extern int be_cmd_get_flow_control(struct be_adapter *adapter, 1529 u32 *tx_fc, u32 *rx_fc); 1530extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, 1531 u32 *port_num, u32 *function_mode, u32 *function_caps); 1532extern int be_cmd_reset_function(struct be_adapter *adapter); 1533extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 1534 u16 table_size); 1535extern int be_process_mcc(struct be_adapter *adapter, int *status); 1536extern int be_cmd_set_beacon_state(struct be_adapter *adapter, 1537 u8 port_num, u8 beacon, u8 status, u8 state); 1538extern int be_cmd_get_beacon_state(struct be_adapter *adapter, 1539 u8 port_num, u32 *state); 1540extern int be_cmd_write_flashrom(struct be_adapter *adapter, 1541 struct be_dma_mem *cmd, u32 flash_oper, 1542 u32 flash_opcode, u32 buf_size); 1543extern int lancer_cmd_write_object(struct be_adapter *adapter, 1544 struct be_dma_mem *cmd, 1545 u32 data_size, u32 data_offset, 1546 const char *obj_name, 1547 u32 *data_written, u8 *addn_status); 1548int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 1549 u32 data_size, u32 data_offset, const char *obj_name, 1550 u32 *data_read, u32 *eof, u8 *addn_status); 1551int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 1552 int offset); 1553extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 1554 struct be_dma_mem *nonemb_cmd); 1555extern int be_cmd_fw_init(struct be_adapter *adapter); 1556extern int be_cmd_fw_clean(struct be_adapter *adapter); 1557extern void be_async_mcc_enable(struct be_adapter *adapter); 1558extern void be_async_mcc_disable(struct be_adapter *adapter); 1559extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 1560 u32 loopback_type, u32 pkt_size, 1561 u32 num_pkts, u64 pattern); 1562extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 1563 u32 byte_cnt, struct be_dma_mem *cmd); 1564extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, 1565 struct be_dma_mem *nonemb_cmd); 1566extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 1567 u8 loopback_type, u8 enable); 1568extern int be_cmd_get_phy_info(struct be_adapter *adapter, 1569 struct be_phy_info *phy_info); 1570extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain); 1571extern void be_detect_dump_ue(struct be_adapter *adapter); 1572extern int be_cmd_get_die_temperature(struct be_adapter *adapter); 1573extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 1574extern int be_cmd_req_native_mode(struct be_adapter *adapter); 1575extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); 1576extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); 1577extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain, 1578 u32 *pmac_id); 1579extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, 1580 u8 mac_count, u32 domain); 1581 1582