1/**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11#include <linux/module.h> 12#include <linux/pci.h> 13#include <linux/netdevice.h> 14#include <linux/etherdevice.h> 15#include <linux/delay.h> 16#include <linux/notifier.h> 17#include <linux/ip.h> 18#include <linux/tcp.h> 19#include <linux/in.h> 20#include <linux/crc32.h> 21#include <linux/ethtool.h> 22#include <linux/topology.h> 23#include <linux/gfp.h> 24#include <linux/cpu_rmap.h> 25#include "net_driver.h" 26#include "efx.h" 27#include "nic.h" 28 29#include "mcdi.h" 30#include "workarounds.h" 31 32/************************************************************************** 33 * 34 * Type name strings 35 * 36 ************************************************************************** 37 */ 38 39/* Loopback mode names (see LOOPBACK_MODE()) */ 40const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; 41const char *efx_loopback_mode_names[] = { 42 [LOOPBACK_NONE] = "NONE", 43 [LOOPBACK_DATA] = "DATAPATH", 44 [LOOPBACK_GMAC] = "GMAC", 45 [LOOPBACK_XGMII] = "XGMII", 46 [LOOPBACK_XGXS] = "XGXS", 47 [LOOPBACK_XAUI] = "XAUI", 48 [LOOPBACK_GMII] = "GMII", 49 [LOOPBACK_SGMII] = "SGMII", 50 [LOOPBACK_XGBR] = "XGBR", 51 [LOOPBACK_XFI] = "XFI", 52 [LOOPBACK_XAUI_FAR] = "XAUI_FAR", 53 [LOOPBACK_GMII_FAR] = "GMII_FAR", 54 [LOOPBACK_SGMII_FAR] = "SGMII_FAR", 55 [LOOPBACK_XFI_FAR] = "XFI_FAR", 56 [LOOPBACK_GPHY] = "GPHY", 57 [LOOPBACK_PHYXS] = "PHYXS", 58 [LOOPBACK_PCS] = "PCS", 59 [LOOPBACK_PMAPMD] = "PMA/PMD", 60 [LOOPBACK_XPORT] = "XPORT", 61 [LOOPBACK_XGMII_WS] = "XGMII_WS", 62 [LOOPBACK_XAUI_WS] = "XAUI_WS", 63 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", 64 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", 65 [LOOPBACK_GMII_WS] = "GMII_WS", 66 [LOOPBACK_XFI_WS] = "XFI_WS", 67 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", 68 [LOOPBACK_PHYXS_WS] = "PHYXS_WS", 69}; 70 71const unsigned int efx_reset_type_max = RESET_TYPE_MAX; 72const char *efx_reset_type_names[] = { 73 [RESET_TYPE_INVISIBLE] = "INVISIBLE", 74 [RESET_TYPE_ALL] = "ALL", 75 [RESET_TYPE_WORLD] = "WORLD", 76 [RESET_TYPE_DISABLE] = "DISABLE", 77 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", 78 [RESET_TYPE_INT_ERROR] = "INT_ERROR", 79 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", 80 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", 81 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", 82 [RESET_TYPE_TX_SKIP] = "TX_SKIP", 83 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", 84}; 85 86#define EFX_MAX_MTU (9 * 1024) 87 88/* Reset workqueue. If any NIC has a hardware failure then a reset will be 89 * queued onto this work queue. This is not a per-nic work queue, because 90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. 91 */ 92static struct workqueue_struct *reset_workqueue; 93 94/************************************************************************** 95 * 96 * Configurable values 97 * 98 *************************************************************************/ 99 100/* 101 * Use separate channels for TX and RX events 102 * 103 * Set this to 1 to use separate channels for TX and RX. It allows us 104 * to control interrupt affinity separately for TX and RX. 105 * 106 * This is only used in MSI-X interrupt mode 107 */ 108static unsigned int separate_tx_channels; 109module_param(separate_tx_channels, uint, 0444); 110MODULE_PARM_DESC(separate_tx_channels, 111 "Use separate channels for TX and RX"); 112 113/* This is the weight assigned to each of the (per-channel) virtual 114 * NAPI devices. 115 */ 116static int napi_weight = 64; 117 118/* This is the time (in jiffies) between invocations of the hardware 119 * monitor. On Falcon-based NICs, this will: 120 * - Check the on-board hardware monitor; 121 * - Poll the link state and reconfigure the hardware as necessary. 122 */ 123static unsigned int efx_monitor_interval = 1 * HZ; 124 125/* This controls whether or not the driver will initialise devices 126 * with invalid MAC addresses stored in the EEPROM or flash. If true, 127 * such devices will be initialised with a random locally-generated 128 * MAC address. This allows for loading the sfc_mtd driver to 129 * reprogram the flash, even if the flash contents (including the MAC 130 * address) have previously been erased. 131 */ 132static unsigned int allow_bad_hwaddr; 133 134/* Initial interrupt moderation settings. They can be modified after 135 * module load with ethtool. 136 * 137 * The default for RX should strike a balance between increasing the 138 * round-trip latency and reducing overhead. 139 */ 140static unsigned int rx_irq_mod_usec = 60; 141 142/* Initial interrupt moderation settings. They can be modified after 143 * module load with ethtool. 144 * 145 * This default is chosen to ensure that a 10G link does not go idle 146 * while a TX queue is stopped after it has become full. A queue is 147 * restarted when it drops below half full. The time this takes (assuming 148 * worst case 3 descriptors per packet and 1024 descriptors) is 149 * 512 / 3 * 1.2 = 205 usec. 150 */ 151static unsigned int tx_irq_mod_usec = 150; 152 153/* This is the first interrupt mode to try out of: 154 * 0 => MSI-X 155 * 1 => MSI 156 * 2 => legacy 157 */ 158static unsigned int interrupt_mode; 159 160/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 161 * i.e. the number of CPUs among which we may distribute simultaneous 162 * interrupt handling. 163 * 164 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 165 * The default (0) means to assign an interrupt to each package (level II cache) 166 */ 167static unsigned int rss_cpus; 168module_param(rss_cpus, uint, 0444); 169MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 170 171static int phy_flash_cfg; 172module_param(phy_flash_cfg, int, 0644); 173MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); 174 175static unsigned irq_adapt_low_thresh = 10000; 176module_param(irq_adapt_low_thresh, uint, 0644); 177MODULE_PARM_DESC(irq_adapt_low_thresh, 178 "Threshold score for reducing IRQ moderation"); 179 180static unsigned irq_adapt_high_thresh = 20000; 181module_param(irq_adapt_high_thresh, uint, 0644); 182MODULE_PARM_DESC(irq_adapt_high_thresh, 183 "Threshold score for increasing IRQ moderation"); 184 185static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 186 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 187 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | 188 NETIF_MSG_TX_ERR | NETIF_MSG_HW); 189module_param(debug, uint, 0); 190MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); 191 192/************************************************************************** 193 * 194 * Utility functions and prototypes 195 * 196 *************************************************************************/ 197 198static void efx_remove_channels(struct efx_nic *efx); 199static void efx_remove_port(struct efx_nic *efx); 200static void efx_init_napi(struct efx_nic *efx); 201static void efx_fini_napi(struct efx_nic *efx); 202static void efx_fini_napi_channel(struct efx_channel *channel); 203static void efx_fini_struct(struct efx_nic *efx); 204static void efx_start_all(struct efx_nic *efx); 205static void efx_stop_all(struct efx_nic *efx); 206 207#define EFX_ASSERT_RESET_SERIALISED(efx) \ 208 do { \ 209 if ((efx->state == STATE_RUNNING) || \ 210 (efx->state == STATE_DISABLED)) \ 211 ASSERT_RTNL(); \ 212 } while (0) 213 214/************************************************************************** 215 * 216 * Event queue processing 217 * 218 *************************************************************************/ 219 220/* Process channel's event queue 221 * 222 * This function is responsible for processing the event queue of a 223 * single channel. The caller must guarantee that this function will 224 * never be concurrently called more than once on the same channel, 225 * though different channels may be being processed concurrently. 226 */ 227static int efx_process_channel(struct efx_channel *channel, int budget) 228{ 229 struct efx_nic *efx = channel->efx; 230 int spent; 231 232 if (unlikely(efx->reset_pending || !channel->enabled)) 233 return 0; 234 235 spent = efx_nic_process_eventq(channel, budget); 236 if (spent == 0) 237 return 0; 238 239 /* Deliver last RX packet. */ 240 if (channel->rx_pkt) { 241 __efx_rx_packet(channel, channel->rx_pkt, 242 channel->rx_pkt_csummed); 243 channel->rx_pkt = NULL; 244 } 245 246 efx_rx_strategy(channel); 247 248 efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel)); 249 250 return spent; 251} 252 253/* Mark channel as finished processing 254 * 255 * Note that since we will not receive further interrupts for this 256 * channel before we finish processing and call the eventq_read_ack() 257 * method, there is no need to use the interrupt hold-off timers. 258 */ 259static inline void efx_channel_processed(struct efx_channel *channel) 260{ 261 /* The interrupt handler for this channel may set work_pending 262 * as soon as we acknowledge the events we've seen. Make sure 263 * it's cleared before then. */ 264 channel->work_pending = false; 265 smp_wmb(); 266 267 efx_nic_eventq_read_ack(channel); 268} 269 270/* NAPI poll handler 271 * 272 * NAPI guarantees serialisation of polls of the same device, which 273 * provides the guarantee required by efx_process_channel(). 274 */ 275static int efx_poll(struct napi_struct *napi, int budget) 276{ 277 struct efx_channel *channel = 278 container_of(napi, struct efx_channel, napi_str); 279 struct efx_nic *efx = channel->efx; 280 int spent; 281 282 netif_vdbg(efx, intr, efx->net_dev, 283 "channel %d NAPI poll executing on CPU %d\n", 284 channel->channel, raw_smp_processor_id()); 285 286 spent = efx_process_channel(channel, budget); 287 288 if (spent < budget) { 289 if (channel->channel < efx->n_rx_channels && 290 efx->irq_rx_adaptive && 291 unlikely(++channel->irq_count == 1000)) { 292 if (unlikely(channel->irq_mod_score < 293 irq_adapt_low_thresh)) { 294 if (channel->irq_moderation > 1) { 295 channel->irq_moderation -= 1; 296 efx->type->push_irq_moderation(channel); 297 } 298 } else if (unlikely(channel->irq_mod_score > 299 irq_adapt_high_thresh)) { 300 if (channel->irq_moderation < 301 efx->irq_rx_moderation) { 302 channel->irq_moderation += 1; 303 efx->type->push_irq_moderation(channel); 304 } 305 } 306 channel->irq_count = 0; 307 channel->irq_mod_score = 0; 308 } 309 310 efx_filter_rfs_expire(channel); 311 312 /* There is no race here; although napi_disable() will 313 * only wait for napi_complete(), this isn't a problem 314 * since efx_channel_processed() will have no effect if 315 * interrupts have already been disabled. 316 */ 317 napi_complete(napi); 318 efx_channel_processed(channel); 319 } 320 321 return spent; 322} 323 324/* Process the eventq of the specified channel immediately on this CPU 325 * 326 * Disable hardware generated interrupts, wait for any existing 327 * processing to finish, then directly poll (and ack ) the eventq. 328 * Finally reenable NAPI and interrupts. 329 * 330 * This is for use only during a loopback self-test. It must not 331 * deliver any packets up the stack as this can result in deadlock. 332 */ 333void efx_process_channel_now(struct efx_channel *channel) 334{ 335 struct efx_nic *efx = channel->efx; 336 337 BUG_ON(channel->channel >= efx->n_channels); 338 BUG_ON(!channel->enabled); 339 BUG_ON(!efx->loopback_selftest); 340 341 /* Disable interrupts and wait for ISRs to complete */ 342 efx_nic_disable_interrupts(efx); 343 if (efx->legacy_irq) { 344 synchronize_irq(efx->legacy_irq); 345 efx->legacy_irq_enabled = false; 346 } 347 if (channel->irq) 348 synchronize_irq(channel->irq); 349 350 /* Wait for any NAPI processing to complete */ 351 napi_disable(&channel->napi_str); 352 353 /* Poll the channel */ 354 efx_process_channel(channel, channel->eventq_mask + 1); 355 356 /* Ack the eventq. This may cause an interrupt to be generated 357 * when they are reenabled */ 358 efx_channel_processed(channel); 359 360 napi_enable(&channel->napi_str); 361 if (efx->legacy_irq) 362 efx->legacy_irq_enabled = true; 363 efx_nic_enable_interrupts(efx); 364} 365 366/* Create event queue 367 * Event queue memory allocations are done only once. If the channel 368 * is reset, the memory buffer will be reused; this guards against 369 * errors during channel reset and also simplifies interrupt handling. 370 */ 371static int efx_probe_eventq(struct efx_channel *channel) 372{ 373 struct efx_nic *efx = channel->efx; 374 unsigned long entries; 375 376 netif_dbg(channel->efx, probe, channel->efx->net_dev, 377 "chan %d create event queue\n", channel->channel); 378 379 /* Build an event queue with room for one event per tx and rx buffer, 380 * plus some extra for link state events and MCDI completions. */ 381 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 382 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 383 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 384 385 return efx_nic_probe_eventq(channel); 386} 387 388/* Prepare channel's event queue */ 389static void efx_init_eventq(struct efx_channel *channel) 390{ 391 netif_dbg(channel->efx, drv, channel->efx->net_dev, 392 "chan %d init event queue\n", channel->channel); 393 394 channel->eventq_read_ptr = 0; 395 396 efx_nic_init_eventq(channel); 397} 398 399static void efx_fini_eventq(struct efx_channel *channel) 400{ 401 netif_dbg(channel->efx, drv, channel->efx->net_dev, 402 "chan %d fini event queue\n", channel->channel); 403 404 efx_nic_fini_eventq(channel); 405} 406 407static void efx_remove_eventq(struct efx_channel *channel) 408{ 409 netif_dbg(channel->efx, drv, channel->efx->net_dev, 410 "chan %d remove event queue\n", channel->channel); 411 412 efx_nic_remove_eventq(channel); 413} 414 415/************************************************************************** 416 * 417 * Channel handling 418 * 419 *************************************************************************/ 420 421/* Allocate and initialise a channel structure, optionally copying 422 * parameters (but not resources) from an old channel structure. */ 423static struct efx_channel * 424efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 425{ 426 struct efx_channel *channel; 427 struct efx_rx_queue *rx_queue; 428 struct efx_tx_queue *tx_queue; 429 int j; 430 431 if (old_channel) { 432 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 433 if (!channel) 434 return NULL; 435 436 *channel = *old_channel; 437 438 channel->napi_dev = NULL; 439 memset(&channel->eventq, 0, sizeof(channel->eventq)); 440 441 rx_queue = &channel->rx_queue; 442 rx_queue->buffer = NULL; 443 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 444 445 for (j = 0; j < EFX_TXQ_TYPES; j++) { 446 tx_queue = &channel->tx_queue[j]; 447 if (tx_queue->channel) 448 tx_queue->channel = channel; 449 tx_queue->buffer = NULL; 450 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 451 } 452 } else { 453 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 454 if (!channel) 455 return NULL; 456 457 channel->efx = efx; 458 channel->channel = i; 459 460 for (j = 0; j < EFX_TXQ_TYPES; j++) { 461 tx_queue = &channel->tx_queue[j]; 462 tx_queue->efx = efx; 463 tx_queue->queue = i * EFX_TXQ_TYPES + j; 464 tx_queue->channel = channel; 465 } 466 } 467 468 rx_queue = &channel->rx_queue; 469 rx_queue->efx = efx; 470 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 471 (unsigned long)rx_queue); 472 473 return channel; 474} 475 476static int efx_probe_channel(struct efx_channel *channel) 477{ 478 struct efx_tx_queue *tx_queue; 479 struct efx_rx_queue *rx_queue; 480 int rc; 481 482 netif_dbg(channel->efx, probe, channel->efx->net_dev, 483 "creating channel %d\n", channel->channel); 484 485 rc = efx_probe_eventq(channel); 486 if (rc) 487 goto fail1; 488 489 efx_for_each_channel_tx_queue(tx_queue, channel) { 490 rc = efx_probe_tx_queue(tx_queue); 491 if (rc) 492 goto fail2; 493 } 494 495 efx_for_each_channel_rx_queue(rx_queue, channel) { 496 rc = efx_probe_rx_queue(rx_queue); 497 if (rc) 498 goto fail3; 499 } 500 501 channel->n_rx_frm_trunc = 0; 502 503 return 0; 504 505 fail3: 506 efx_for_each_channel_rx_queue(rx_queue, channel) 507 efx_remove_rx_queue(rx_queue); 508 fail2: 509 efx_for_each_channel_tx_queue(tx_queue, channel) 510 efx_remove_tx_queue(tx_queue); 511 fail1: 512 return rc; 513} 514 515 516static void efx_set_channel_names(struct efx_nic *efx) 517{ 518 struct efx_channel *channel; 519 const char *type = ""; 520 int number; 521 522 efx_for_each_channel(channel, efx) { 523 number = channel->channel; 524 if (efx->n_channels > efx->n_rx_channels) { 525 if (channel->channel < efx->n_rx_channels) { 526 type = "-rx"; 527 } else { 528 type = "-tx"; 529 number -= efx->n_rx_channels; 530 } 531 } 532 snprintf(efx->channel_name[channel->channel], 533 sizeof(efx->channel_name[0]), 534 "%s%s-%d", efx->name, type, number); 535 } 536} 537 538static int efx_probe_channels(struct efx_nic *efx) 539{ 540 struct efx_channel *channel; 541 int rc; 542 543 /* Restart special buffer allocation */ 544 efx->next_buffer_table = 0; 545 546 efx_for_each_channel(channel, efx) { 547 rc = efx_probe_channel(channel); 548 if (rc) { 549 netif_err(efx, probe, efx->net_dev, 550 "failed to create channel %d\n", 551 channel->channel); 552 goto fail; 553 } 554 } 555 efx_set_channel_names(efx); 556 557 return 0; 558 559fail: 560 efx_remove_channels(efx); 561 return rc; 562} 563 564/* Channels are shutdown and reinitialised whilst the NIC is running 565 * to propagate configuration changes (mtu, checksum offload), or 566 * to clear hardware error conditions 567 */ 568static void efx_init_channels(struct efx_nic *efx) 569{ 570 struct efx_tx_queue *tx_queue; 571 struct efx_rx_queue *rx_queue; 572 struct efx_channel *channel; 573 574 /* Calculate the rx buffer allocation parameters required to 575 * support the current MTU, including padding for header 576 * alignment and overruns. 577 */ 578 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + 579 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + 580 efx->type->rx_buffer_hash_size + 581 efx->type->rx_buffer_padding); 582 efx->rx_buffer_order = get_order(efx->rx_buffer_len + 583 sizeof(struct efx_rx_page_state)); 584 585 /* Initialise the channels */ 586 efx_for_each_channel(channel, efx) { 587 netif_dbg(channel->efx, drv, channel->efx->net_dev, 588 "init chan %d\n", channel->channel); 589 590 efx_init_eventq(channel); 591 592 efx_for_each_channel_tx_queue(tx_queue, channel) 593 efx_init_tx_queue(tx_queue); 594 595 /* The rx buffer allocation strategy is MTU dependent */ 596 efx_rx_strategy(channel); 597 598 efx_for_each_channel_rx_queue(rx_queue, channel) 599 efx_init_rx_queue(rx_queue); 600 601 WARN_ON(channel->rx_pkt != NULL); 602 efx_rx_strategy(channel); 603 } 604} 605 606/* This enables event queue processing and packet transmission. 607 * 608 * Note that this function is not allowed to fail, since that would 609 * introduce too much complexity into the suspend/resume path. 610 */ 611static void efx_start_channel(struct efx_channel *channel) 612{ 613 struct efx_rx_queue *rx_queue; 614 615 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 616 "starting chan %d\n", channel->channel); 617 618 /* The interrupt handler for this channel may set work_pending 619 * as soon as we enable it. Make sure it's cleared before 620 * then. Similarly, make sure it sees the enabled flag set. */ 621 channel->work_pending = false; 622 channel->enabled = true; 623 smp_wmb(); 624 625 /* Fill the queues before enabling NAPI */ 626 efx_for_each_channel_rx_queue(rx_queue, channel) 627 efx_fast_push_rx_descriptors(rx_queue); 628 629 napi_enable(&channel->napi_str); 630} 631 632/* This disables event queue processing and packet transmission. 633 * This function does not guarantee that all queue processing 634 * (e.g. RX refill) is complete. 635 */ 636static void efx_stop_channel(struct efx_channel *channel) 637{ 638 if (!channel->enabled) 639 return; 640 641 netif_dbg(channel->efx, ifdown, channel->efx->net_dev, 642 "stop chan %d\n", channel->channel); 643 644 channel->enabled = false; 645 napi_disable(&channel->napi_str); 646} 647 648static void efx_fini_channels(struct efx_nic *efx) 649{ 650 struct efx_channel *channel; 651 struct efx_tx_queue *tx_queue; 652 struct efx_rx_queue *rx_queue; 653 int rc; 654 655 EFX_ASSERT_RESET_SERIALISED(efx); 656 BUG_ON(efx->port_enabled); 657 658 rc = efx_nic_flush_queues(efx); 659 if (rc && EFX_WORKAROUND_7803(efx)) { 660 /* Schedule a reset to recover from the flush failure. The 661 * descriptor caches reference memory we're about to free, 662 * but falcon_reconfigure_mac_wrapper() won't reconnect 663 * the MACs because of the pending reset. */ 664 netif_err(efx, drv, efx->net_dev, 665 "Resetting to recover from flush failure\n"); 666 efx_schedule_reset(efx, RESET_TYPE_ALL); 667 } else if (rc) { 668 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 669 } else { 670 netif_dbg(efx, drv, efx->net_dev, 671 "successfully flushed all queues\n"); 672 } 673 674 efx_for_each_channel(channel, efx) { 675 netif_dbg(channel->efx, drv, channel->efx->net_dev, 676 "shut down chan %d\n", channel->channel); 677 678 efx_for_each_channel_rx_queue(rx_queue, channel) 679 efx_fini_rx_queue(rx_queue); 680 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 681 efx_fini_tx_queue(tx_queue); 682 efx_fini_eventq(channel); 683 } 684} 685 686static void efx_remove_channel(struct efx_channel *channel) 687{ 688 struct efx_tx_queue *tx_queue; 689 struct efx_rx_queue *rx_queue; 690 691 netif_dbg(channel->efx, drv, channel->efx->net_dev, 692 "destroy chan %d\n", channel->channel); 693 694 efx_for_each_channel_rx_queue(rx_queue, channel) 695 efx_remove_rx_queue(rx_queue); 696 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 697 efx_remove_tx_queue(tx_queue); 698 efx_remove_eventq(channel); 699} 700 701static void efx_remove_channels(struct efx_nic *efx) 702{ 703 struct efx_channel *channel; 704 705 efx_for_each_channel(channel, efx) 706 efx_remove_channel(channel); 707} 708 709int 710efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 711{ 712 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 713 u32 old_rxq_entries, old_txq_entries; 714 unsigned i; 715 int rc; 716 717 efx_stop_all(efx); 718 efx_fini_channels(efx); 719 720 /* Clone channels */ 721 memset(other_channel, 0, sizeof(other_channel)); 722 for (i = 0; i < efx->n_channels; i++) { 723 channel = efx_alloc_channel(efx, i, efx->channel[i]); 724 if (!channel) { 725 rc = -ENOMEM; 726 goto out; 727 } 728 other_channel[i] = channel; 729 } 730 731 /* Swap entry counts and channel pointers */ 732 old_rxq_entries = efx->rxq_entries; 733 old_txq_entries = efx->txq_entries; 734 efx->rxq_entries = rxq_entries; 735 efx->txq_entries = txq_entries; 736 for (i = 0; i < efx->n_channels; i++) { 737 channel = efx->channel[i]; 738 efx->channel[i] = other_channel[i]; 739 other_channel[i] = channel; 740 } 741 742 rc = efx_probe_channels(efx); 743 if (rc) 744 goto rollback; 745 746 efx_init_napi(efx); 747 748 /* Destroy old channels */ 749 for (i = 0; i < efx->n_channels; i++) { 750 efx_fini_napi_channel(other_channel[i]); 751 efx_remove_channel(other_channel[i]); 752 } 753out: 754 /* Free unused channel structures */ 755 for (i = 0; i < efx->n_channels; i++) 756 kfree(other_channel[i]); 757 758 efx_init_channels(efx); 759 efx_start_all(efx); 760 return rc; 761 762rollback: 763 /* Swap back */ 764 efx->rxq_entries = old_rxq_entries; 765 efx->txq_entries = old_txq_entries; 766 for (i = 0; i < efx->n_channels; i++) { 767 channel = efx->channel[i]; 768 efx->channel[i] = other_channel[i]; 769 other_channel[i] = channel; 770 } 771 goto out; 772} 773 774void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) 775{ 776 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); 777} 778 779/************************************************************************** 780 * 781 * Port handling 782 * 783 **************************************************************************/ 784 785/* This ensures that the kernel is kept informed (via 786 * netif_carrier_on/off) of the link status, and also maintains the 787 * link status's stop on the port's TX queue. 788 */ 789void efx_link_status_changed(struct efx_nic *efx) 790{ 791 struct efx_link_state *link_state = &efx->link_state; 792 793 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure 794 * that no events are triggered between unregister_netdev() and the 795 * driver unloading. A more general condition is that NETDEV_CHANGE 796 * can only be generated between NETDEV_UP and NETDEV_DOWN */ 797 if (!netif_running(efx->net_dev)) 798 return; 799 800 if (link_state->up != netif_carrier_ok(efx->net_dev)) { 801 efx->n_link_state_changes++; 802 803 if (link_state->up) 804 netif_carrier_on(efx->net_dev); 805 else 806 netif_carrier_off(efx->net_dev); 807 } 808 809 /* Status message for kernel log */ 810 if (link_state->up) { 811 netif_info(efx, link, efx->net_dev, 812 "link up at %uMbps %s-duplex (MTU %d)%s\n", 813 link_state->speed, link_state->fd ? "full" : "half", 814 efx->net_dev->mtu, 815 (efx->promiscuous ? " [PROMISC]" : "")); 816 } else { 817 netif_info(efx, link, efx->net_dev, "link down\n"); 818 } 819 820} 821 822void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) 823{ 824 efx->link_advertising = advertising; 825 if (advertising) { 826 if (advertising & ADVERTISED_Pause) 827 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); 828 else 829 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); 830 if (advertising & ADVERTISED_Asym_Pause) 831 efx->wanted_fc ^= EFX_FC_TX; 832 } 833} 834 835void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) 836{ 837 efx->wanted_fc = wanted_fc; 838 if (efx->link_advertising) { 839 if (wanted_fc & EFX_FC_RX) 840 efx->link_advertising |= (ADVERTISED_Pause | 841 ADVERTISED_Asym_Pause); 842 else 843 efx->link_advertising &= ~(ADVERTISED_Pause | 844 ADVERTISED_Asym_Pause); 845 if (wanted_fc & EFX_FC_TX) 846 efx->link_advertising ^= ADVERTISED_Asym_Pause; 847 } 848} 849 850static void efx_fini_port(struct efx_nic *efx); 851 852/* Push loopback/power/transmit disable settings to the PHY, and reconfigure 853 * the MAC appropriately. All other PHY configuration changes are pushed 854 * through phy_op->set_settings(), and pushed asynchronously to the MAC 855 * through efx_monitor(). 856 * 857 * Callers must hold the mac_lock 858 */ 859int __efx_reconfigure_port(struct efx_nic *efx) 860{ 861 enum efx_phy_mode phy_mode; 862 int rc; 863 864 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 865 866 /* Serialise the promiscuous flag with efx_set_multicast_list. */ 867 if (efx_dev_registered(efx)) { 868 netif_addr_lock_bh(efx->net_dev); 869 netif_addr_unlock_bh(efx->net_dev); 870 } 871 872 /* Disable PHY transmit in mac level loopbacks */ 873 phy_mode = efx->phy_mode; 874 if (LOOPBACK_INTERNAL(efx)) 875 efx->phy_mode |= PHY_MODE_TX_DISABLED; 876 else 877 efx->phy_mode &= ~PHY_MODE_TX_DISABLED; 878 879 rc = efx->type->reconfigure_port(efx); 880 881 if (rc) 882 efx->phy_mode = phy_mode; 883 884 return rc; 885} 886 887/* Reinitialise the MAC to pick up new PHY settings, even if the port is 888 * disabled. */ 889int efx_reconfigure_port(struct efx_nic *efx) 890{ 891 int rc; 892 893 EFX_ASSERT_RESET_SERIALISED(efx); 894 895 mutex_lock(&efx->mac_lock); 896 rc = __efx_reconfigure_port(efx); 897 mutex_unlock(&efx->mac_lock); 898 899 return rc; 900} 901 902/* Asynchronous work item for changing MAC promiscuity and multicast 903 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current 904 * MAC directly. */ 905static void efx_mac_work(struct work_struct *data) 906{ 907 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); 908 909 mutex_lock(&efx->mac_lock); 910 if (efx->port_enabled) { 911 efx->type->push_multicast_hash(efx); 912 efx->mac_op->reconfigure(efx); 913 } 914 mutex_unlock(&efx->mac_lock); 915} 916 917static int efx_probe_port(struct efx_nic *efx) 918{ 919 unsigned char *perm_addr; 920 int rc; 921 922 netif_dbg(efx, probe, efx->net_dev, "create port\n"); 923 924 if (phy_flash_cfg) 925 efx->phy_mode = PHY_MODE_SPECIAL; 926 927 /* Connect up MAC/PHY operations table */ 928 rc = efx->type->probe_port(efx); 929 if (rc) 930 return rc; 931 932 /* Sanity check MAC address */ 933 perm_addr = efx->net_dev->perm_addr; 934 if (is_valid_ether_addr(perm_addr)) { 935 memcpy(efx->net_dev->dev_addr, perm_addr, ETH_ALEN); 936 } else { 937 netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n", 938 perm_addr); 939 if (!allow_bad_hwaddr) { 940 rc = -EINVAL; 941 goto err; 942 } 943 random_ether_addr(efx->net_dev->dev_addr); 944 netif_info(efx, probe, efx->net_dev, 945 "using locally-generated MAC %pM\n", 946 efx->net_dev->dev_addr); 947 } 948 949 return 0; 950 951 err: 952 efx->type->remove_port(efx); 953 return rc; 954} 955 956static int efx_init_port(struct efx_nic *efx) 957{ 958 int rc; 959 960 netif_dbg(efx, drv, efx->net_dev, "init port\n"); 961 962 mutex_lock(&efx->mac_lock); 963 964 rc = efx->phy_op->init(efx); 965 if (rc) 966 goto fail1; 967 968 efx->port_initialized = true; 969 970 /* Reconfigure the MAC before creating dma queues (required for 971 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ 972 efx->mac_op->reconfigure(efx); 973 974 /* Ensure the PHY advertises the correct flow control settings */ 975 rc = efx->phy_op->reconfigure(efx); 976 if (rc) 977 goto fail2; 978 979 mutex_unlock(&efx->mac_lock); 980 return 0; 981 982fail2: 983 efx->phy_op->fini(efx); 984fail1: 985 mutex_unlock(&efx->mac_lock); 986 return rc; 987} 988 989static void efx_start_port(struct efx_nic *efx) 990{ 991 netif_dbg(efx, ifup, efx->net_dev, "start port\n"); 992 BUG_ON(efx->port_enabled); 993 994 mutex_lock(&efx->mac_lock); 995 efx->port_enabled = true; 996 997 /* efx_mac_work() might have been scheduled after efx_stop_port(), 998 * and then cancelled by efx_flush_all() */ 999 efx->type->push_multicast_hash(efx); 1000 efx->mac_op->reconfigure(efx); 1001 1002 mutex_unlock(&efx->mac_lock); 1003} 1004 1005/* Prevent efx_mac_work() and efx_monitor() from working */ 1006static void efx_stop_port(struct efx_nic *efx) 1007{ 1008 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); 1009 1010 mutex_lock(&efx->mac_lock); 1011 efx->port_enabled = false; 1012 mutex_unlock(&efx->mac_lock); 1013 1014 /* Serialise against efx_set_multicast_list() */ 1015 if (efx_dev_registered(efx)) { 1016 netif_addr_lock_bh(efx->net_dev); 1017 netif_addr_unlock_bh(efx->net_dev); 1018 } 1019} 1020 1021static void efx_fini_port(struct efx_nic *efx) 1022{ 1023 netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); 1024 1025 if (!efx->port_initialized) 1026 return; 1027 1028 efx->phy_op->fini(efx); 1029 efx->port_initialized = false; 1030 1031 efx->link_state.up = false; 1032 efx_link_status_changed(efx); 1033} 1034 1035static void efx_remove_port(struct efx_nic *efx) 1036{ 1037 netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); 1038 1039 efx->type->remove_port(efx); 1040} 1041 1042/************************************************************************** 1043 * 1044 * NIC handling 1045 * 1046 **************************************************************************/ 1047 1048/* This configures the PCI device to enable I/O and DMA. */ 1049static int efx_init_io(struct efx_nic *efx) 1050{ 1051 struct pci_dev *pci_dev = efx->pci_dev; 1052 dma_addr_t dma_mask = efx->type->max_dma_mask; 1053 int rc; 1054 1055 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); 1056 1057 rc = pci_enable_device(pci_dev); 1058 if (rc) { 1059 netif_err(efx, probe, efx->net_dev, 1060 "failed to enable PCI device\n"); 1061 goto fail1; 1062 } 1063 1064 pci_set_master(pci_dev); 1065 1066 /* Set the PCI DMA mask. Try all possibilities from our 1067 * genuine mask down to 32 bits, because some architectures 1068 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit 1069 * masks event though they reject 46 bit masks. 1070 */ 1071 while (dma_mask > 0x7fffffffUL) { 1072 if (pci_dma_supported(pci_dev, dma_mask) && 1073 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) 1074 break; 1075 dma_mask >>= 1; 1076 } 1077 if (rc) { 1078 netif_err(efx, probe, efx->net_dev, 1079 "could not find a suitable DMA mask\n"); 1080 goto fail2; 1081 } 1082 netif_dbg(efx, probe, efx->net_dev, 1083 "using DMA mask %llx\n", (unsigned long long) dma_mask); 1084 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); 1085 if (rc) { 1086 /* pci_set_consistent_dma_mask() is not *allowed* to 1087 * fail with a mask that pci_set_dma_mask() accepted, 1088 * but just in case... 1089 */ 1090 netif_err(efx, probe, efx->net_dev, 1091 "failed to set consistent DMA mask\n"); 1092 goto fail2; 1093 } 1094 1095 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); 1096 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); 1097 if (rc) { 1098 netif_err(efx, probe, efx->net_dev, 1099 "request for memory BAR failed\n"); 1100 rc = -EIO; 1101 goto fail3; 1102 } 1103 efx->membase = ioremap_nocache(efx->membase_phys, 1104 efx->type->mem_map_size); 1105 if (!efx->membase) { 1106 netif_err(efx, probe, efx->net_dev, 1107 "could not map memory BAR at %llx+%x\n", 1108 (unsigned long long)efx->membase_phys, 1109 efx->type->mem_map_size); 1110 rc = -ENOMEM; 1111 goto fail4; 1112 } 1113 netif_dbg(efx, probe, efx->net_dev, 1114 "memory BAR at %llx+%x (virtual %p)\n", 1115 (unsigned long long)efx->membase_phys, 1116 efx->type->mem_map_size, efx->membase); 1117 1118 return 0; 1119 1120 fail4: 1121 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1122 fail3: 1123 efx->membase_phys = 0; 1124 fail2: 1125 pci_disable_device(efx->pci_dev); 1126 fail1: 1127 return rc; 1128} 1129 1130static void efx_fini_io(struct efx_nic *efx) 1131{ 1132 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); 1133 1134 if (efx->membase) { 1135 iounmap(efx->membase); 1136 efx->membase = NULL; 1137 } 1138 1139 if (efx->membase_phys) { 1140 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1141 efx->membase_phys = 0; 1142 } 1143 1144 pci_disable_device(efx->pci_dev); 1145} 1146 1147/* Get number of channels wanted. Each channel will have its own IRQ, 1148 * 1 RX queue and/or 2 TX queues. */ 1149static int efx_wanted_channels(void) 1150{ 1151 cpumask_var_t core_mask; 1152 int count; 1153 int cpu; 1154 1155 if (rss_cpus) 1156 return rss_cpus; 1157 1158 if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { 1159 printk(KERN_WARNING 1160 "sfc: RSS disabled due to allocation failure\n"); 1161 return 1; 1162 } 1163 1164 count = 0; 1165 for_each_online_cpu(cpu) { 1166 if (!cpumask_test_cpu(cpu, core_mask)) { 1167 ++count; 1168 cpumask_or(core_mask, core_mask, 1169 topology_core_cpumask(cpu)); 1170 } 1171 } 1172 1173 free_cpumask_var(core_mask); 1174 return count; 1175} 1176 1177static int 1178efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) 1179{ 1180#ifdef CONFIG_RFS_ACCEL 1181 int i, rc; 1182 1183 efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); 1184 if (!efx->net_dev->rx_cpu_rmap) 1185 return -ENOMEM; 1186 for (i = 0; i < efx->n_rx_channels; i++) { 1187 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, 1188 xentries[i].vector); 1189 if (rc) { 1190 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 1191 efx->net_dev->rx_cpu_rmap = NULL; 1192 return rc; 1193 } 1194 } 1195#endif 1196 return 0; 1197} 1198 1199/* Probe the number and type of interrupts we are able to obtain, and 1200 * the resulting numbers of channels and RX queues. 1201 */ 1202static int efx_probe_interrupts(struct efx_nic *efx) 1203{ 1204 int max_channels = 1205 min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); 1206 int rc, i; 1207 1208 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 1209 struct msix_entry xentries[EFX_MAX_CHANNELS]; 1210 int n_channels; 1211 1212 n_channels = efx_wanted_channels(); 1213 if (separate_tx_channels) 1214 n_channels *= 2; 1215 n_channels = min(n_channels, max_channels); 1216 1217 for (i = 0; i < n_channels; i++) 1218 xentries[i].entry = i; 1219 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); 1220 if (rc > 0) { 1221 netif_err(efx, drv, efx->net_dev, 1222 "WARNING: Insufficient MSI-X vectors" 1223 " available (%d < %d).\n", rc, n_channels); 1224 netif_err(efx, drv, efx->net_dev, 1225 "WARNING: Performance may be reduced.\n"); 1226 EFX_BUG_ON_PARANOID(rc >= n_channels); 1227 n_channels = rc; 1228 rc = pci_enable_msix(efx->pci_dev, xentries, 1229 n_channels); 1230 } 1231 1232 if (rc == 0) { 1233 efx->n_channels = n_channels; 1234 if (separate_tx_channels) { 1235 efx->n_tx_channels = 1236 max(efx->n_channels / 2, 1U); 1237 efx->n_rx_channels = 1238 max(efx->n_channels - 1239 efx->n_tx_channels, 1U); 1240 } else { 1241 efx->n_tx_channels = efx->n_channels; 1242 efx->n_rx_channels = efx->n_channels; 1243 } 1244 rc = efx_init_rx_cpu_rmap(efx, xentries); 1245 if (rc) { 1246 pci_disable_msix(efx->pci_dev); 1247 return rc; 1248 } 1249 for (i = 0; i < n_channels; i++) 1250 efx_get_channel(efx, i)->irq = 1251 xentries[i].vector; 1252 } else { 1253 /* Fall back to single channel MSI */ 1254 efx->interrupt_mode = EFX_INT_MODE_MSI; 1255 netif_err(efx, drv, efx->net_dev, 1256 "could not enable MSI-X\n"); 1257 } 1258 } 1259 1260 /* Try single interrupt MSI */ 1261 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 1262 efx->n_channels = 1; 1263 efx->n_rx_channels = 1; 1264 efx->n_tx_channels = 1; 1265 rc = pci_enable_msi(efx->pci_dev); 1266 if (rc == 0) { 1267 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 1268 } else { 1269 netif_err(efx, drv, efx->net_dev, 1270 "could not enable MSI\n"); 1271 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 1272 } 1273 } 1274 1275 /* Assume legacy interrupts */ 1276 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 1277 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); 1278 efx->n_rx_channels = 1; 1279 efx->n_tx_channels = 1; 1280 efx->legacy_irq = efx->pci_dev->irq; 1281 } 1282 1283 return 0; 1284} 1285 1286static void efx_remove_interrupts(struct efx_nic *efx) 1287{ 1288 struct efx_channel *channel; 1289 1290 /* Remove MSI/MSI-X interrupts */ 1291 efx_for_each_channel(channel, efx) 1292 channel->irq = 0; 1293 pci_disable_msi(efx->pci_dev); 1294 pci_disable_msix(efx->pci_dev); 1295 1296 /* Remove legacy interrupt */ 1297 efx->legacy_irq = 0; 1298} 1299 1300static void efx_set_channels(struct efx_nic *efx) 1301{ 1302 struct efx_channel *channel; 1303 struct efx_tx_queue *tx_queue; 1304 1305 efx->tx_channel_offset = 1306 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; 1307 1308 /* We need to adjust the TX queue numbers if we have separate 1309 * RX-only and TX-only channels. 1310 */ 1311 efx_for_each_channel(channel, efx) { 1312 efx_for_each_channel_tx_queue(tx_queue, channel) 1313 tx_queue->queue -= (efx->tx_channel_offset * 1314 EFX_TXQ_TYPES); 1315 } 1316} 1317 1318static int efx_probe_nic(struct efx_nic *efx) 1319{ 1320 size_t i; 1321 int rc; 1322 1323 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); 1324 1325 /* Carry out hardware-type specific initialisation */ 1326 rc = efx->type->probe(efx); 1327 if (rc) 1328 return rc; 1329 1330 /* Determine the number of channels and queues by trying to hook 1331 * in MSI-X interrupts. */ 1332 rc = efx_probe_interrupts(efx); 1333 if (rc) 1334 goto fail; 1335 1336 if (efx->n_channels > 1) 1337 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); 1338 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) 1339 efx->rx_indir_table[i] = 1340 ethtool_rxfh_indir_default(i, efx->n_rx_channels); 1341 1342 efx_set_channels(efx); 1343 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1344 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1345 1346 /* Initialise the interrupt moderation settings */ 1347 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, 1348 true); 1349 1350 return 0; 1351 1352fail: 1353 efx->type->remove(efx); 1354 return rc; 1355} 1356 1357static void efx_remove_nic(struct efx_nic *efx) 1358{ 1359 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); 1360 1361 efx_remove_interrupts(efx); 1362 efx->type->remove(efx); 1363} 1364 1365/************************************************************************** 1366 * 1367 * NIC startup/shutdown 1368 * 1369 *************************************************************************/ 1370 1371static int efx_probe_all(struct efx_nic *efx) 1372{ 1373 int rc; 1374 1375 rc = efx_probe_nic(efx); 1376 if (rc) { 1377 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); 1378 goto fail1; 1379 } 1380 1381 rc = efx_probe_port(efx); 1382 if (rc) { 1383 netif_err(efx, probe, efx->net_dev, "failed to create port\n"); 1384 goto fail2; 1385 } 1386 1387 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; 1388 rc = efx_probe_channels(efx); 1389 if (rc) 1390 goto fail3; 1391 1392 rc = efx_probe_filters(efx); 1393 if (rc) { 1394 netif_err(efx, probe, efx->net_dev, 1395 "failed to create filter tables\n"); 1396 goto fail4; 1397 } 1398 1399 return 0; 1400 1401 fail4: 1402 efx_remove_channels(efx); 1403 fail3: 1404 efx_remove_port(efx); 1405 fail2: 1406 efx_remove_nic(efx); 1407 fail1: 1408 return rc; 1409} 1410 1411/* Called after previous invocation(s) of efx_stop_all, restarts the 1412 * port, kernel transmit queue, NAPI processing and hardware interrupts, 1413 * and ensures that the port is scheduled to be reconfigured. 1414 * This function is safe to call multiple times when the NIC is in any 1415 * state. */ 1416static void efx_start_all(struct efx_nic *efx) 1417{ 1418 struct efx_channel *channel; 1419 1420 EFX_ASSERT_RESET_SERIALISED(efx); 1421 1422 /* Check that it is appropriate to restart the interface. All 1423 * of these flags are safe to read under just the rtnl lock */ 1424 if (efx->port_enabled) 1425 return; 1426 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) 1427 return; 1428 if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) 1429 return; 1430 1431 /* Mark the port as enabled so port reconfigurations can start, then 1432 * restart the transmit interface early so the watchdog timer stops */ 1433 efx_start_port(efx); 1434 1435 if (efx_dev_registered(efx) && netif_device_present(efx->net_dev)) 1436 netif_tx_wake_all_queues(efx->net_dev); 1437 1438 efx_for_each_channel(channel, efx) 1439 efx_start_channel(channel); 1440 1441 if (efx->legacy_irq) 1442 efx->legacy_irq_enabled = true; 1443 efx_nic_enable_interrupts(efx); 1444 1445 /* Switch to event based MCDI completions after enabling interrupts. 1446 * If a reset has been scheduled, then we need to stay in polled mode. 1447 * Rather than serialising efx_mcdi_mode_event() [which sleeps] and 1448 * reset_pending [modified from an atomic context], we instead guarantee 1449 * that efx_mcdi_mode_poll() isn't reverted erroneously */ 1450 efx_mcdi_mode_event(efx); 1451 if (efx->reset_pending) 1452 efx_mcdi_mode_poll(efx); 1453 1454 /* Start the hardware monitor if there is one. Otherwise (we're link 1455 * event driven), we have to poll the PHY because after an event queue 1456 * flush, we could have a missed a link state change */ 1457 if (efx->type->monitor != NULL) { 1458 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1459 efx_monitor_interval); 1460 } else { 1461 mutex_lock(&efx->mac_lock); 1462 if (efx->phy_op->poll(efx)) 1463 efx_link_status_changed(efx); 1464 mutex_unlock(&efx->mac_lock); 1465 } 1466 1467 efx->type->start_stats(efx); 1468} 1469 1470/* Flush all delayed work. Should only be called when no more delayed work 1471 * will be scheduled. This doesn't flush pending online resets (efx_reset), 1472 * since we're holding the rtnl_lock at this point. */ 1473static void efx_flush_all(struct efx_nic *efx) 1474{ 1475 /* Make sure the hardware monitor is stopped */ 1476 cancel_delayed_work_sync(&efx->monitor_work); 1477 /* Stop scheduled port reconfigurations */ 1478 cancel_work_sync(&efx->mac_work); 1479} 1480 1481/* Quiesce hardware and software without bringing the link down. 1482 * Safe to call multiple times, when the nic and interface is in any 1483 * state. The caller is guaranteed to subsequently be in a position 1484 * to modify any hardware and software state they see fit without 1485 * taking locks. */ 1486static void efx_stop_all(struct efx_nic *efx) 1487{ 1488 struct efx_channel *channel; 1489 1490 EFX_ASSERT_RESET_SERIALISED(efx); 1491 1492 /* port_enabled can be read safely under the rtnl lock */ 1493 if (!efx->port_enabled) 1494 return; 1495 1496 efx->type->stop_stats(efx); 1497 1498 /* Switch to MCDI polling on Siena before disabling interrupts */ 1499 efx_mcdi_mode_poll(efx); 1500 1501 /* Disable interrupts and wait for ISR to complete */ 1502 efx_nic_disable_interrupts(efx); 1503 if (efx->legacy_irq) { 1504 synchronize_irq(efx->legacy_irq); 1505 efx->legacy_irq_enabled = false; 1506 } 1507 efx_for_each_channel(channel, efx) { 1508 if (channel->irq) 1509 synchronize_irq(channel->irq); 1510 } 1511 1512 /* Stop all NAPI processing and synchronous rx refills */ 1513 efx_for_each_channel(channel, efx) 1514 efx_stop_channel(channel); 1515 1516 /* Stop all asynchronous port reconfigurations. Since all 1517 * event processing has already been stopped, there is no 1518 * window to loose phy events */ 1519 efx_stop_port(efx); 1520 1521 /* Flush efx_mac_work(), refill_workqueue, monitor_work */ 1522 efx_flush_all(efx); 1523 1524 /* Stop the kernel transmit interface late, so the watchdog 1525 * timer isn't ticking over the flush */ 1526 if (efx_dev_registered(efx)) { 1527 netif_tx_stop_all_queues(efx->net_dev); 1528 netif_tx_lock_bh(efx->net_dev); 1529 netif_tx_unlock_bh(efx->net_dev); 1530 } 1531} 1532 1533static void efx_remove_all(struct efx_nic *efx) 1534{ 1535 efx_remove_filters(efx); 1536 efx_remove_channels(efx); 1537 efx_remove_port(efx); 1538 efx_remove_nic(efx); 1539} 1540 1541/************************************************************************** 1542 * 1543 * Interrupt moderation 1544 * 1545 **************************************************************************/ 1546 1547static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int resolution) 1548{ 1549 if (usecs == 0) 1550 return 0; 1551 if (usecs < resolution) 1552 return 1; /* never round down to 0 */ 1553 return usecs / resolution; 1554} 1555 1556/* Set interrupt moderation parameters */ 1557int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, 1558 unsigned int rx_usecs, bool rx_adaptive, 1559 bool rx_may_override_tx) 1560{ 1561 struct efx_channel *channel; 1562 unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); 1563 unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); 1564 1565 EFX_ASSERT_RESET_SERIALISED(efx); 1566 1567 if (tx_ticks > EFX_IRQ_MOD_MAX || rx_ticks > EFX_IRQ_MOD_MAX) 1568 return -EINVAL; 1569 1570 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && 1571 !rx_may_override_tx) { 1572 netif_err(efx, drv, efx->net_dev, "Channels are shared. " 1573 "RX and TX IRQ moderation must be equal\n"); 1574 return -EINVAL; 1575 } 1576 1577 efx->irq_rx_adaptive = rx_adaptive; 1578 efx->irq_rx_moderation = rx_ticks; 1579 efx_for_each_channel(channel, efx) { 1580 if (efx_channel_has_rx_queue(channel)) 1581 channel->irq_moderation = rx_ticks; 1582 else if (efx_channel_has_tx_queues(channel)) 1583 channel->irq_moderation = tx_ticks; 1584 } 1585 1586 return 0; 1587} 1588 1589void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, 1590 unsigned int *rx_usecs, bool *rx_adaptive) 1591{ 1592 *rx_adaptive = efx->irq_rx_adaptive; 1593 *rx_usecs = efx->irq_rx_moderation * EFX_IRQ_MOD_RESOLUTION; 1594 1595 /* If channels are shared between RX and TX, so is IRQ 1596 * moderation. Otherwise, IRQ moderation is the same for all 1597 * TX channels and is not adaptive. 1598 */ 1599 if (efx->tx_channel_offset == 0) 1600 *tx_usecs = *rx_usecs; 1601 else 1602 *tx_usecs = 1603 efx->channel[efx->tx_channel_offset]->irq_moderation * 1604 EFX_IRQ_MOD_RESOLUTION; 1605} 1606 1607/************************************************************************** 1608 * 1609 * Hardware monitor 1610 * 1611 **************************************************************************/ 1612 1613/* Run periodically off the general workqueue */ 1614static void efx_monitor(struct work_struct *data) 1615{ 1616 struct efx_nic *efx = container_of(data, struct efx_nic, 1617 monitor_work.work); 1618 1619 netif_vdbg(efx, timer, efx->net_dev, 1620 "hardware monitor executing on CPU %d\n", 1621 raw_smp_processor_id()); 1622 BUG_ON(efx->type->monitor == NULL); 1623 1624 /* If the mac_lock is already held then it is likely a port 1625 * reconfiguration is already in place, which will likely do 1626 * most of the work of monitor() anyway. */ 1627 if (mutex_trylock(&efx->mac_lock)) { 1628 if (efx->port_enabled) 1629 efx->type->monitor(efx); 1630 mutex_unlock(&efx->mac_lock); 1631 } 1632 1633 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1634 efx_monitor_interval); 1635} 1636 1637/************************************************************************** 1638 * 1639 * ioctls 1640 * 1641 *************************************************************************/ 1642 1643/* Net device ioctl 1644 * Context: process, rtnl_lock() held. 1645 */ 1646static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1647{ 1648 struct efx_nic *efx = netdev_priv(net_dev); 1649 struct mii_ioctl_data *data = if_mii(ifr); 1650 1651 EFX_ASSERT_RESET_SERIALISED(efx); 1652 1653 /* Convert phy_id from older PRTAD/DEVAD format */ 1654 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 1655 (data->phy_id & 0xfc00) == 0x0400) 1656 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 1657 1658 return mdio_mii_ioctl(&efx->mdio, data, cmd); 1659} 1660 1661/************************************************************************** 1662 * 1663 * NAPI interface 1664 * 1665 **************************************************************************/ 1666 1667static void efx_init_napi(struct efx_nic *efx) 1668{ 1669 struct efx_channel *channel; 1670 1671 efx_for_each_channel(channel, efx) { 1672 channel->napi_dev = efx->net_dev; 1673 netif_napi_add(channel->napi_dev, &channel->napi_str, 1674 efx_poll, napi_weight); 1675 } 1676} 1677 1678static void efx_fini_napi_channel(struct efx_channel *channel) 1679{ 1680 if (channel->napi_dev) 1681 netif_napi_del(&channel->napi_str); 1682 channel->napi_dev = NULL; 1683} 1684 1685static void efx_fini_napi(struct efx_nic *efx) 1686{ 1687 struct efx_channel *channel; 1688 1689 efx_for_each_channel(channel, efx) 1690 efx_fini_napi_channel(channel); 1691} 1692 1693/************************************************************************** 1694 * 1695 * Kernel netpoll interface 1696 * 1697 *************************************************************************/ 1698 1699#ifdef CONFIG_NET_POLL_CONTROLLER 1700 1701/* Although in the common case interrupts will be disabled, this is not 1702 * guaranteed. However, all our work happens inside the NAPI callback, 1703 * so no locking is required. 1704 */ 1705static void efx_netpoll(struct net_device *net_dev) 1706{ 1707 struct efx_nic *efx = netdev_priv(net_dev); 1708 struct efx_channel *channel; 1709 1710 efx_for_each_channel(channel, efx) 1711 efx_schedule_channel(channel); 1712} 1713 1714#endif 1715 1716/************************************************************************** 1717 * 1718 * Kernel net device interface 1719 * 1720 *************************************************************************/ 1721 1722/* Context: process, rtnl_lock() held. */ 1723static int efx_net_open(struct net_device *net_dev) 1724{ 1725 struct efx_nic *efx = netdev_priv(net_dev); 1726 EFX_ASSERT_RESET_SERIALISED(efx); 1727 1728 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", 1729 raw_smp_processor_id()); 1730 1731 if (efx->state == STATE_DISABLED) 1732 return -EIO; 1733 if (efx->phy_mode & PHY_MODE_SPECIAL) 1734 return -EBUSY; 1735 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) 1736 return -EIO; 1737 1738 /* Notify the kernel of the link state polled during driver load, 1739 * before the monitor starts running */ 1740 efx_link_status_changed(efx); 1741 1742 efx_start_all(efx); 1743 return 0; 1744} 1745 1746/* Context: process, rtnl_lock() held. 1747 * Note that the kernel will ignore our return code; this method 1748 * should really be a void. 1749 */ 1750static int efx_net_stop(struct net_device *net_dev) 1751{ 1752 struct efx_nic *efx = netdev_priv(net_dev); 1753 1754 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", 1755 raw_smp_processor_id()); 1756 1757 if (efx->state != STATE_DISABLED) { 1758 /* Stop the device and flush all the channels */ 1759 efx_stop_all(efx); 1760 efx_fini_channels(efx); 1761 efx_init_channels(efx); 1762 } 1763 1764 return 0; 1765} 1766 1767/* Context: process, dev_base_lock or RTNL held, non-blocking. */ 1768static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats) 1769{ 1770 struct efx_nic *efx = netdev_priv(net_dev); 1771 struct efx_mac_stats *mac_stats = &efx->mac_stats; 1772 1773 spin_lock_bh(&efx->stats_lock); 1774 efx->type->update_stats(efx); 1775 spin_unlock_bh(&efx->stats_lock); 1776 1777 stats->rx_packets = mac_stats->rx_packets; 1778 stats->tx_packets = mac_stats->tx_packets; 1779 stats->rx_bytes = mac_stats->rx_bytes; 1780 stats->tx_bytes = mac_stats->tx_bytes; 1781 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; 1782 stats->multicast = mac_stats->rx_multicast; 1783 stats->collisions = mac_stats->tx_collision; 1784 stats->rx_length_errors = (mac_stats->rx_gtjumbo + 1785 mac_stats->rx_length_error); 1786 stats->rx_crc_errors = mac_stats->rx_bad; 1787 stats->rx_frame_errors = mac_stats->rx_align_error; 1788 stats->rx_fifo_errors = mac_stats->rx_overflow; 1789 stats->rx_missed_errors = mac_stats->rx_missed; 1790 stats->tx_window_errors = mac_stats->tx_late_collision; 1791 1792 stats->rx_errors = (stats->rx_length_errors + 1793 stats->rx_crc_errors + 1794 stats->rx_frame_errors + 1795 mac_stats->rx_symbol_error); 1796 stats->tx_errors = (stats->tx_window_errors + 1797 mac_stats->tx_bad); 1798 1799 return stats; 1800} 1801 1802/* Context: netif_tx_lock held, BHs disabled. */ 1803static void efx_watchdog(struct net_device *net_dev) 1804{ 1805 struct efx_nic *efx = netdev_priv(net_dev); 1806 1807 netif_err(efx, tx_err, efx->net_dev, 1808 "TX stuck with port_enabled=%d: resetting channels\n", 1809 efx->port_enabled); 1810 1811 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); 1812} 1813 1814 1815/* Context: process, rtnl_lock() held. */ 1816static int efx_change_mtu(struct net_device *net_dev, int new_mtu) 1817{ 1818 struct efx_nic *efx = netdev_priv(net_dev); 1819 int rc = 0; 1820 1821 EFX_ASSERT_RESET_SERIALISED(efx); 1822 1823 if (new_mtu > EFX_MAX_MTU) 1824 return -EINVAL; 1825 1826 efx_stop_all(efx); 1827 1828 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); 1829 1830 efx_fini_channels(efx); 1831 1832 mutex_lock(&efx->mac_lock); 1833 /* Reconfigure the MAC before enabling the dma queues so that 1834 * the RX buffers don't overflow */ 1835 net_dev->mtu = new_mtu; 1836 efx->mac_op->reconfigure(efx); 1837 mutex_unlock(&efx->mac_lock); 1838 1839 efx_init_channels(efx); 1840 1841 efx_start_all(efx); 1842 return rc; 1843} 1844 1845static int efx_set_mac_address(struct net_device *net_dev, void *data) 1846{ 1847 struct efx_nic *efx = netdev_priv(net_dev); 1848 struct sockaddr *addr = data; 1849 char *new_addr = addr->sa_data; 1850 1851 EFX_ASSERT_RESET_SERIALISED(efx); 1852 1853 if (!is_valid_ether_addr(new_addr)) { 1854 netif_err(efx, drv, efx->net_dev, 1855 "invalid ethernet MAC address requested: %pM\n", 1856 new_addr); 1857 return -EINVAL; 1858 } 1859 1860 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); 1861 1862 /* Reconfigure the MAC */ 1863 mutex_lock(&efx->mac_lock); 1864 efx->mac_op->reconfigure(efx); 1865 mutex_unlock(&efx->mac_lock); 1866 1867 return 0; 1868} 1869 1870/* Context: netif_addr_lock held, BHs disabled. */ 1871static void efx_set_multicast_list(struct net_device *net_dev) 1872{ 1873 struct efx_nic *efx = netdev_priv(net_dev); 1874 struct netdev_hw_addr *ha; 1875 union efx_multicast_hash *mc_hash = &efx->multicast_hash; 1876 u32 crc; 1877 int bit; 1878 1879 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); 1880 1881 /* Build multicast hash table */ 1882 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { 1883 memset(mc_hash, 0xff, sizeof(*mc_hash)); 1884 } else { 1885 memset(mc_hash, 0x00, sizeof(*mc_hash)); 1886 netdev_for_each_mc_addr(ha, net_dev) { 1887 crc = ether_crc_le(ETH_ALEN, ha->addr); 1888 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); 1889 set_bit_le(bit, mc_hash->byte); 1890 } 1891 1892 /* Broadcast packets go through the multicast hash filter. 1893 * ether_crc_le() of the broadcast address is 0xbe2612ff 1894 * so we always add bit 0xff to the mask. 1895 */ 1896 set_bit_le(0xff, mc_hash->byte); 1897 } 1898 1899 if (efx->port_enabled) 1900 queue_work(efx->workqueue, &efx->mac_work); 1901 /* Otherwise efx_start_port() will do this */ 1902} 1903 1904static int efx_set_features(struct net_device *net_dev, netdev_features_t data) 1905{ 1906 struct efx_nic *efx = netdev_priv(net_dev); 1907 1908 /* If disabling RX n-tuple filtering, clear existing filters */ 1909 if (net_dev->features & ~data & NETIF_F_NTUPLE) 1910 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); 1911 1912 return 0; 1913} 1914 1915static const struct net_device_ops efx_netdev_ops = { 1916 .ndo_open = efx_net_open, 1917 .ndo_stop = efx_net_stop, 1918 .ndo_get_stats64 = efx_net_stats, 1919 .ndo_tx_timeout = efx_watchdog, 1920 .ndo_start_xmit = efx_hard_start_xmit, 1921 .ndo_validate_addr = eth_validate_addr, 1922 .ndo_do_ioctl = efx_ioctl, 1923 .ndo_change_mtu = efx_change_mtu, 1924 .ndo_set_mac_address = efx_set_mac_address, 1925 .ndo_set_rx_mode = efx_set_multicast_list, 1926 .ndo_set_features = efx_set_features, 1927#ifdef CONFIG_NET_POLL_CONTROLLER 1928 .ndo_poll_controller = efx_netpoll, 1929#endif 1930 .ndo_setup_tc = efx_setup_tc, 1931#ifdef CONFIG_RFS_ACCEL 1932 .ndo_rx_flow_steer = efx_filter_rfs, 1933#endif 1934}; 1935 1936static void efx_update_name(struct efx_nic *efx) 1937{ 1938 strcpy(efx->name, efx->net_dev->name); 1939 efx_mtd_rename(efx); 1940 efx_set_channel_names(efx); 1941} 1942 1943static int efx_netdev_event(struct notifier_block *this, 1944 unsigned long event, void *ptr) 1945{ 1946 struct net_device *net_dev = ptr; 1947 1948 if (net_dev->netdev_ops == &efx_netdev_ops && 1949 event == NETDEV_CHANGENAME) 1950 efx_update_name(netdev_priv(net_dev)); 1951 1952 return NOTIFY_DONE; 1953} 1954 1955static struct notifier_block efx_netdev_notifier = { 1956 .notifier_call = efx_netdev_event, 1957}; 1958 1959static ssize_t 1960show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) 1961{ 1962 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 1963 return sprintf(buf, "%d\n", efx->phy_type); 1964} 1965static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); 1966 1967static int efx_register_netdev(struct efx_nic *efx) 1968{ 1969 struct net_device *net_dev = efx->net_dev; 1970 struct efx_channel *channel; 1971 int rc; 1972 1973 net_dev->watchdog_timeo = 5 * HZ; 1974 net_dev->irq = efx->pci_dev->irq; 1975 net_dev->netdev_ops = &efx_netdev_ops; 1976 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); 1977 1978 /* Clear MAC statistics */ 1979 efx->mac_op->update_stats(efx); 1980 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); 1981 1982 rtnl_lock(); 1983 1984 rc = dev_alloc_name(net_dev, net_dev->name); 1985 if (rc < 0) 1986 goto fail_locked; 1987 efx_update_name(efx); 1988 1989 rc = register_netdevice(net_dev); 1990 if (rc) 1991 goto fail_locked; 1992 1993 efx_for_each_channel(channel, efx) { 1994 struct efx_tx_queue *tx_queue; 1995 efx_for_each_channel_tx_queue(tx_queue, channel) 1996 efx_init_tx_queue_core_txq(tx_queue); 1997 } 1998 1999 /* Always start with carrier off; PHY events will detect the link */ 2000 netif_carrier_off(efx->net_dev); 2001 2002 rtnl_unlock(); 2003 2004 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2005 if (rc) { 2006 netif_err(efx, drv, efx->net_dev, 2007 "failed to init net dev attributes\n"); 2008 goto fail_registered; 2009 } 2010 2011 return 0; 2012 2013fail_locked: 2014 rtnl_unlock(); 2015 netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); 2016 return rc; 2017 2018fail_registered: 2019 unregister_netdev(net_dev); 2020 return rc; 2021} 2022 2023static void efx_unregister_netdev(struct efx_nic *efx) 2024{ 2025 struct efx_channel *channel; 2026 struct efx_tx_queue *tx_queue; 2027 2028 if (!efx->net_dev) 2029 return; 2030 2031 BUG_ON(netdev_priv(efx->net_dev) != efx); 2032 2033 /* Free up any skbs still remaining. This has to happen before 2034 * we try to unregister the netdev as running their destructors 2035 * may be needed to get the device ref. count to 0. */ 2036 efx_for_each_channel(channel, efx) { 2037 efx_for_each_channel_tx_queue(tx_queue, channel) 2038 efx_release_tx_buffers(tx_queue); 2039 } 2040 2041 if (efx_dev_registered(efx)) { 2042 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); 2043 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2044 unregister_netdev(efx->net_dev); 2045 } 2046} 2047 2048/************************************************************************** 2049 * 2050 * Device reset and suspend 2051 * 2052 **************************************************************************/ 2053 2054/* Tears down the entire software state and most of the hardware state 2055 * before reset. */ 2056void efx_reset_down(struct efx_nic *efx, enum reset_type method) 2057{ 2058 EFX_ASSERT_RESET_SERIALISED(efx); 2059 2060 efx_stop_all(efx); 2061 mutex_lock(&efx->mac_lock); 2062 2063 efx_fini_channels(efx); 2064 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) 2065 efx->phy_op->fini(efx); 2066 efx->type->fini(efx); 2067} 2068 2069/* This function will always ensure that the locks acquired in 2070 * efx_reset_down() are released. A failure return code indicates 2071 * that we were unable to reinitialise the hardware, and the 2072 * driver should be disabled. If ok is false, then the rx and tx 2073 * engines are not restarted, pending a RESET_DISABLE. */ 2074int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) 2075{ 2076 int rc; 2077 2078 EFX_ASSERT_RESET_SERIALISED(efx); 2079 2080 rc = efx->type->init(efx); 2081 if (rc) { 2082 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); 2083 goto fail; 2084 } 2085 2086 if (!ok) 2087 goto fail; 2088 2089 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { 2090 rc = efx->phy_op->init(efx); 2091 if (rc) 2092 goto fail; 2093 if (efx->phy_op->reconfigure(efx)) 2094 netif_err(efx, drv, efx->net_dev, 2095 "could not restore PHY settings\n"); 2096 } 2097 2098 efx->mac_op->reconfigure(efx); 2099 2100 efx_init_channels(efx); 2101 efx_restore_filters(efx); 2102 2103 mutex_unlock(&efx->mac_lock); 2104 2105 efx_start_all(efx); 2106 2107 return 0; 2108 2109fail: 2110 efx->port_initialized = false; 2111 2112 mutex_unlock(&efx->mac_lock); 2113 2114 return rc; 2115} 2116 2117/* Reset the NIC using the specified method. Note that the reset may 2118 * fail, in which case the card will be left in an unusable state. 2119 * 2120 * Caller must hold the rtnl_lock. 2121 */ 2122int efx_reset(struct efx_nic *efx, enum reset_type method) 2123{ 2124 int rc, rc2; 2125 bool disabled; 2126 2127 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", 2128 RESET_TYPE(method)); 2129 2130 netif_device_detach(efx->net_dev); 2131 efx_reset_down(efx, method); 2132 2133 rc = efx->type->reset(efx, method); 2134 if (rc) { 2135 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); 2136 goto out; 2137 } 2138 2139 /* Clear flags for the scopes we covered. We assume the NIC and 2140 * driver are now quiescent so that there is no race here. 2141 */ 2142 efx->reset_pending &= -(1 << (method + 1)); 2143 2144 /* Reinitialise bus-mastering, which may have been turned off before 2145 * the reset was scheduled. This is still appropriate, even in the 2146 * RESET_TYPE_DISABLE since this driver generally assumes the hardware 2147 * can respond to requests. */ 2148 pci_set_master(efx->pci_dev); 2149 2150out: 2151 /* Leave device stopped if necessary */ 2152 disabled = rc || method == RESET_TYPE_DISABLE; 2153 rc2 = efx_reset_up(efx, method, !disabled); 2154 if (rc2) { 2155 disabled = true; 2156 if (!rc) 2157 rc = rc2; 2158 } 2159 2160 if (disabled) { 2161 dev_close(efx->net_dev); 2162 netif_err(efx, drv, efx->net_dev, "has been disabled\n"); 2163 efx->state = STATE_DISABLED; 2164 } else { 2165 netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); 2166 netif_device_attach(efx->net_dev); 2167 } 2168 return rc; 2169} 2170 2171/* The worker thread exists so that code that cannot sleep can 2172 * schedule a reset for later. 2173 */ 2174static void efx_reset_work(struct work_struct *data) 2175{ 2176 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); 2177 unsigned long pending = ACCESS_ONCE(efx->reset_pending); 2178 2179 if (!pending) 2180 return; 2181 2182 /* If we're not RUNNING then don't reset. Leave the reset_pending 2183 * flags set so that efx_pci_probe_main will be retried */ 2184 if (efx->state != STATE_RUNNING) { 2185 netif_info(efx, drv, efx->net_dev, 2186 "scheduled reset quenched. NIC not RUNNING\n"); 2187 return; 2188 } 2189 2190 rtnl_lock(); 2191 (void)efx_reset(efx, fls(pending) - 1); 2192 rtnl_unlock(); 2193} 2194 2195void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) 2196{ 2197 enum reset_type method; 2198 2199 switch (type) { 2200 case RESET_TYPE_INVISIBLE: 2201 case RESET_TYPE_ALL: 2202 case RESET_TYPE_WORLD: 2203 case RESET_TYPE_DISABLE: 2204 method = type; 2205 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", 2206 RESET_TYPE(method)); 2207 break; 2208 default: 2209 method = efx->type->map_reset_reason(type); 2210 netif_dbg(efx, drv, efx->net_dev, 2211 "scheduling %s reset for %s\n", 2212 RESET_TYPE(method), RESET_TYPE(type)); 2213 break; 2214 } 2215 2216 set_bit(method, &efx->reset_pending); 2217 2218 /* efx_process_channel() will no longer read events once a 2219 * reset is scheduled. So switch back to poll'd MCDI completions. */ 2220 efx_mcdi_mode_poll(efx); 2221 2222 queue_work(reset_workqueue, &efx->reset_work); 2223} 2224 2225/************************************************************************** 2226 * 2227 * List of NICs we support 2228 * 2229 **************************************************************************/ 2230 2231/* PCI device ID table */ 2232static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { 2233 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2234 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), 2235 .driver_data = (unsigned long) &falcon_a1_nic_type}, 2236 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2237 PCI_DEVICE_ID_SOLARFLARE_SFC4000B), 2238 .driver_data = (unsigned long) &falcon_b0_nic_type}, 2239 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ 2240 .driver_data = (unsigned long) &siena_a0_nic_type}, 2241 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ 2242 .driver_data = (unsigned long) &siena_a0_nic_type}, 2243 {0} /* end of list */ 2244}; 2245 2246/************************************************************************** 2247 * 2248 * Dummy PHY/MAC operations 2249 * 2250 * Can be used for some unimplemented operations 2251 * Needed so all function pointers are valid and do not have to be tested 2252 * before use 2253 * 2254 **************************************************************************/ 2255int efx_port_dummy_op_int(struct efx_nic *efx) 2256{ 2257 return 0; 2258} 2259void efx_port_dummy_op_void(struct efx_nic *efx) {} 2260 2261static bool efx_port_dummy_op_poll(struct efx_nic *efx) 2262{ 2263 return false; 2264} 2265 2266static const struct efx_phy_operations efx_dummy_phy_operations = { 2267 .init = efx_port_dummy_op_int, 2268 .reconfigure = efx_port_dummy_op_int, 2269 .poll = efx_port_dummy_op_poll, 2270 .fini = efx_port_dummy_op_void, 2271}; 2272 2273/************************************************************************** 2274 * 2275 * Data housekeeping 2276 * 2277 **************************************************************************/ 2278 2279/* This zeroes out and then fills in the invariants in a struct 2280 * efx_nic (including all sub-structures). 2281 */ 2282static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type, 2283 struct pci_dev *pci_dev, struct net_device *net_dev) 2284{ 2285 int i; 2286 2287 /* Initialise common structures */ 2288 memset(efx, 0, sizeof(*efx)); 2289 spin_lock_init(&efx->biu_lock); 2290#ifdef CONFIG_SFC_MTD 2291 INIT_LIST_HEAD(&efx->mtd_list); 2292#endif 2293 INIT_WORK(&efx->reset_work, efx_reset_work); 2294 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); 2295 efx->pci_dev = pci_dev; 2296 efx->msg_enable = debug; 2297 efx->state = STATE_INIT; 2298 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); 2299 2300 efx->net_dev = net_dev; 2301 spin_lock_init(&efx->stats_lock); 2302 mutex_init(&efx->mac_lock); 2303 efx->mac_op = type->default_mac_ops; 2304 efx->phy_op = &efx_dummy_phy_operations; 2305 efx->mdio.dev = net_dev; 2306 INIT_WORK(&efx->mac_work, efx_mac_work); 2307 2308 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 2309 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 2310 if (!efx->channel[i]) 2311 goto fail; 2312 } 2313 2314 efx->type = type; 2315 2316 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); 2317 2318 /* Higher numbered interrupt modes are less capable! */ 2319 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 2320 interrupt_mode); 2321 2322 /* Would be good to use the net_dev name, but we're too early */ 2323 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", 2324 pci_name(pci_dev)); 2325 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); 2326 if (!efx->workqueue) 2327 goto fail; 2328 2329 return 0; 2330 2331fail: 2332 efx_fini_struct(efx); 2333 return -ENOMEM; 2334} 2335 2336static void efx_fini_struct(struct efx_nic *efx) 2337{ 2338 int i; 2339 2340 for (i = 0; i < EFX_MAX_CHANNELS; i++) 2341 kfree(efx->channel[i]); 2342 2343 if (efx->workqueue) { 2344 destroy_workqueue(efx->workqueue); 2345 efx->workqueue = NULL; 2346 } 2347} 2348 2349/************************************************************************** 2350 * 2351 * PCI interface 2352 * 2353 **************************************************************************/ 2354 2355/* Main body of final NIC shutdown code 2356 * This is called only at module unload (or hotplug removal). 2357 */ 2358static void efx_pci_remove_main(struct efx_nic *efx) 2359{ 2360#ifdef CONFIG_RFS_ACCEL 2361 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 2362 efx->net_dev->rx_cpu_rmap = NULL; 2363#endif 2364 efx_nic_fini_interrupt(efx); 2365 efx_fini_channels(efx); 2366 efx_fini_port(efx); 2367 efx->type->fini(efx); 2368 efx_fini_napi(efx); 2369 efx_remove_all(efx); 2370} 2371 2372/* Final NIC shutdown 2373 * This is called only at module unload (or hotplug removal). 2374 */ 2375static void efx_pci_remove(struct pci_dev *pci_dev) 2376{ 2377 struct efx_nic *efx; 2378 2379 efx = pci_get_drvdata(pci_dev); 2380 if (!efx) 2381 return; 2382 2383 /* Mark the NIC as fini, then stop the interface */ 2384 rtnl_lock(); 2385 efx->state = STATE_FINI; 2386 dev_close(efx->net_dev); 2387 2388 /* Allow any queued efx_resets() to complete */ 2389 rtnl_unlock(); 2390 2391 efx_unregister_netdev(efx); 2392 2393 efx_mtd_remove(efx); 2394 2395 /* Wait for any scheduled resets to complete. No more will be 2396 * scheduled from this point because efx_stop_all() has been 2397 * called, we are no longer registered with driverlink, and 2398 * the net_device's have been removed. */ 2399 cancel_work_sync(&efx->reset_work); 2400 2401 efx_pci_remove_main(efx); 2402 2403 efx_fini_io(efx); 2404 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); 2405 2406 pci_set_drvdata(pci_dev, NULL); 2407 efx_fini_struct(efx); 2408 free_netdev(efx->net_dev); 2409}; 2410 2411/* Main body of NIC initialisation 2412 * This is called at module load (or hotplug insertion, theoretically). 2413 */ 2414static int efx_pci_probe_main(struct efx_nic *efx) 2415{ 2416 int rc; 2417 2418 /* Do start-of-day initialisation */ 2419 rc = efx_probe_all(efx); 2420 if (rc) 2421 goto fail1; 2422 2423 efx_init_napi(efx); 2424 2425 rc = efx->type->init(efx); 2426 if (rc) { 2427 netif_err(efx, probe, efx->net_dev, 2428 "failed to initialise NIC\n"); 2429 goto fail3; 2430 } 2431 2432 rc = efx_init_port(efx); 2433 if (rc) { 2434 netif_err(efx, probe, efx->net_dev, 2435 "failed to initialise port\n"); 2436 goto fail4; 2437 } 2438 2439 efx_init_channels(efx); 2440 2441 rc = efx_nic_init_interrupt(efx); 2442 if (rc) 2443 goto fail5; 2444 2445 return 0; 2446 2447 fail5: 2448 efx_fini_channels(efx); 2449 efx_fini_port(efx); 2450 fail4: 2451 efx->type->fini(efx); 2452 fail3: 2453 efx_fini_napi(efx); 2454 efx_remove_all(efx); 2455 fail1: 2456 return rc; 2457} 2458 2459/* NIC initialisation 2460 * 2461 * This is called at module load (or hotplug insertion, 2462 * theoretically). It sets up PCI mappings, tests and resets the NIC, 2463 * sets up and registers the network devices with the kernel and hooks 2464 * the interrupt service routine. It does not prepare the device for 2465 * transmission; this is left to the first time one of the network 2466 * interfaces is brought up (i.e. efx_net_open). 2467 */ 2468static int __devinit efx_pci_probe(struct pci_dev *pci_dev, 2469 const struct pci_device_id *entry) 2470{ 2471 const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data; 2472 struct net_device *net_dev; 2473 struct efx_nic *efx; 2474 int i, rc; 2475 2476 /* Allocate and initialise a struct net_device and struct efx_nic */ 2477 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, 2478 EFX_MAX_RX_QUEUES); 2479 if (!net_dev) 2480 return -ENOMEM; 2481 net_dev->features |= (type->offload_features | NETIF_F_SG | 2482 NETIF_F_HIGHDMA | NETIF_F_TSO | 2483 NETIF_F_RXCSUM); 2484 if (type->offload_features & NETIF_F_V6_CSUM) 2485 net_dev->features |= NETIF_F_TSO6; 2486 /* Mask for features that also apply to VLAN devices */ 2487 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | 2488 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | 2489 NETIF_F_RXCSUM); 2490 /* All offloads can be toggled */ 2491 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; 2492 efx = netdev_priv(net_dev); 2493 pci_set_drvdata(pci_dev, efx); 2494 SET_NETDEV_DEV(net_dev, &pci_dev->dev); 2495 rc = efx_init_struct(efx, type, pci_dev, net_dev); 2496 if (rc) 2497 goto fail1; 2498 2499 netif_info(efx, probe, efx->net_dev, 2500 "Solarflare NIC detected\n"); 2501 2502 /* Set up basic I/O (BAR mappings etc) */ 2503 rc = efx_init_io(efx); 2504 if (rc) 2505 goto fail2; 2506 2507 /* No serialisation is required with the reset path because 2508 * we're in STATE_INIT. */ 2509 for (i = 0; i < 5; i++) { 2510 rc = efx_pci_probe_main(efx); 2511 2512 /* Serialise against efx_reset(). No more resets will be 2513 * scheduled since efx_stop_all() has been called, and we 2514 * have not and never have been registered with either 2515 * the rtnetlink or driverlink layers. */ 2516 cancel_work_sync(&efx->reset_work); 2517 2518 if (rc == 0) { 2519 if (efx->reset_pending) { 2520 /* If there was a scheduled reset during 2521 * probe, the NIC is probably hosed anyway */ 2522 efx_pci_remove_main(efx); 2523 rc = -EIO; 2524 } else { 2525 break; 2526 } 2527 } 2528 2529 /* Retry if a recoverably reset event has been scheduled */ 2530 if (efx->reset_pending & 2531 ~(1 << RESET_TYPE_INVISIBLE | 1 << RESET_TYPE_ALL) || 2532 !efx->reset_pending) 2533 goto fail3; 2534 2535 efx->reset_pending = 0; 2536 } 2537 2538 if (rc) { 2539 netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n"); 2540 goto fail4; 2541 } 2542 2543 /* Switch to the running state before we expose the device to the OS, 2544 * so that dev_open()|efx_start_all() will actually start the device */ 2545 efx->state = STATE_RUNNING; 2546 2547 rc = efx_register_netdev(efx); 2548 if (rc) 2549 goto fail5; 2550 2551 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); 2552 2553 rtnl_lock(); 2554 efx_mtd_probe(efx); /* allowed to fail */ 2555 rtnl_unlock(); 2556 return 0; 2557 2558 fail5: 2559 efx_pci_remove_main(efx); 2560 fail4: 2561 fail3: 2562 efx_fini_io(efx); 2563 fail2: 2564 efx_fini_struct(efx); 2565 fail1: 2566 WARN_ON(rc > 0); 2567 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); 2568 free_netdev(net_dev); 2569 return rc; 2570} 2571 2572static int efx_pm_freeze(struct device *dev) 2573{ 2574 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2575 2576 efx->state = STATE_FINI; 2577 2578 netif_device_detach(efx->net_dev); 2579 2580 efx_stop_all(efx); 2581 efx_fini_channels(efx); 2582 2583 return 0; 2584} 2585 2586static int efx_pm_thaw(struct device *dev) 2587{ 2588 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2589 2590 efx->state = STATE_INIT; 2591 2592 efx_init_channels(efx); 2593 2594 mutex_lock(&efx->mac_lock); 2595 efx->phy_op->reconfigure(efx); 2596 mutex_unlock(&efx->mac_lock); 2597 2598 efx_start_all(efx); 2599 2600 netif_device_attach(efx->net_dev); 2601 2602 efx->state = STATE_RUNNING; 2603 2604 efx->type->resume_wol(efx); 2605 2606 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ 2607 queue_work(reset_workqueue, &efx->reset_work); 2608 2609 return 0; 2610} 2611 2612static int efx_pm_poweroff(struct device *dev) 2613{ 2614 struct pci_dev *pci_dev = to_pci_dev(dev); 2615 struct efx_nic *efx = pci_get_drvdata(pci_dev); 2616 2617 efx->type->fini(efx); 2618 2619 efx->reset_pending = 0; 2620 2621 pci_save_state(pci_dev); 2622 return pci_set_power_state(pci_dev, PCI_D3hot); 2623} 2624 2625/* Used for both resume and restore */ 2626static int efx_pm_resume(struct device *dev) 2627{ 2628 struct pci_dev *pci_dev = to_pci_dev(dev); 2629 struct efx_nic *efx = pci_get_drvdata(pci_dev); 2630 int rc; 2631 2632 rc = pci_set_power_state(pci_dev, PCI_D0); 2633 if (rc) 2634 return rc; 2635 pci_restore_state(pci_dev); 2636 rc = pci_enable_device(pci_dev); 2637 if (rc) 2638 return rc; 2639 pci_set_master(efx->pci_dev); 2640 rc = efx->type->reset(efx, RESET_TYPE_ALL); 2641 if (rc) 2642 return rc; 2643 rc = efx->type->init(efx); 2644 if (rc) 2645 return rc; 2646 efx_pm_thaw(dev); 2647 return 0; 2648} 2649 2650static int efx_pm_suspend(struct device *dev) 2651{ 2652 int rc; 2653 2654 efx_pm_freeze(dev); 2655 rc = efx_pm_poweroff(dev); 2656 if (rc) 2657 efx_pm_resume(dev); 2658 return rc; 2659} 2660 2661static struct dev_pm_ops efx_pm_ops = { 2662 .suspend = efx_pm_suspend, 2663 .resume = efx_pm_resume, 2664 .freeze = efx_pm_freeze, 2665 .thaw = efx_pm_thaw, 2666 .poweroff = efx_pm_poweroff, 2667 .restore = efx_pm_resume, 2668}; 2669 2670static struct pci_driver efx_pci_driver = { 2671 .name = KBUILD_MODNAME, 2672 .id_table = efx_pci_table, 2673 .probe = efx_pci_probe, 2674 .remove = efx_pci_remove, 2675 .driver.pm = &efx_pm_ops, 2676}; 2677 2678/************************************************************************** 2679 * 2680 * Kernel module interface 2681 * 2682 *************************************************************************/ 2683 2684module_param(interrupt_mode, uint, 0444); 2685MODULE_PARM_DESC(interrupt_mode, 2686 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 2687 2688static int __init efx_init_module(void) 2689{ 2690 int rc; 2691 2692 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); 2693 2694 rc = register_netdevice_notifier(&efx_netdev_notifier); 2695 if (rc) 2696 goto err_notifier; 2697 2698 reset_workqueue = create_singlethread_workqueue("sfc_reset"); 2699 if (!reset_workqueue) { 2700 rc = -ENOMEM; 2701 goto err_reset; 2702 } 2703 2704 rc = pci_register_driver(&efx_pci_driver); 2705 if (rc < 0) 2706 goto err_pci; 2707 2708 return 0; 2709 2710 err_pci: 2711 destroy_workqueue(reset_workqueue); 2712 err_reset: 2713 unregister_netdevice_notifier(&efx_netdev_notifier); 2714 err_notifier: 2715 return rc; 2716} 2717 2718static void __exit efx_exit_module(void) 2719{ 2720 printk(KERN_INFO "Solarflare NET driver unloading\n"); 2721 2722 pci_unregister_driver(&efx_pci_driver); 2723 destroy_workqueue(reset_workqueue); 2724 unregister_netdevice_notifier(&efx_netdev_notifier); 2725 2726} 2727 2728module_init(efx_init_module); 2729module_exit(efx_exit_module); 2730 2731MODULE_AUTHOR("Solarflare Communications and " 2732 "Michael Brown <mbrown@fensystems.co.uk>"); 2733MODULE_DESCRIPTION("Solarflare Communications network driver"); 2734MODULE_LICENSE("GPL"); 2735MODULE_DEVICE_TABLE(pci, efx_pci_table); 2736