eeprom_4k.c revision 4ddfcd7daf57247ff718b849a152d97a80b7ae4d
1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "hw.h" 18#include "ar9002_phy.h" 19 20static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 21{ 22 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF); 23} 24 25static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) 26{ 27 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF); 28} 29 30static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 31{ 32#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 33 struct ath_common *common = ath9k_hw_common(ah); 34 u16 *eep_data = (u16 *)&ah->eeprom.map4k; 35 int addr, eep_start_loc = 0; 36 37 eep_start_loc = 64; 38 39 if (!ath9k_hw_use_flash(ah)) { 40 ath_dbg(common, ATH_DBG_EEPROM, 41 "Reading from EEPROM, not flash\n"); 42 } 43 44 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 45 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { 46 ath_dbg(common, ATH_DBG_EEPROM, 47 "Unable to read eeprom region\n"); 48 return false; 49 } 50 eep_data++; 51 } 52 53 return true; 54#undef SIZE_EEPROM_4K 55} 56 57static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) 58{ 59#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 60 struct ath_common *common = ath9k_hw_common(ah); 61 struct ar5416_eeprom_4k *eep = 62 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; 63 u16 *eepdata, temp, magic, magic2; 64 u32 sum = 0, el; 65 bool need_swap = false; 66 int i, addr; 67 68 69 if (!ath9k_hw_use_flash(ah)) { 70 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, 71 &magic)) { 72 ath_err(common, "Reading Magic # failed\n"); 73 return false; 74 } 75 76 ath_dbg(common, ATH_DBG_EEPROM, 77 "Read Magic = 0x%04X\n", magic); 78 79 if (magic != AR5416_EEPROM_MAGIC) { 80 magic2 = swab16(magic); 81 82 if (magic2 == AR5416_EEPROM_MAGIC) { 83 need_swap = true; 84 eepdata = (u16 *) (&ah->eeprom); 85 86 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { 87 temp = swab16(*eepdata); 88 *eepdata = temp; 89 eepdata++; 90 } 91 } else { 92 ath_err(common, 93 "Invalid EEPROM Magic. Endianness mismatch.\n"); 94 return -EINVAL; 95 } 96 } 97 } 98 99 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 100 need_swap ? "True" : "False"); 101 102 if (need_swap) 103 el = swab16(ah->eeprom.map4k.baseEepHeader.length); 104 else 105 el = ah->eeprom.map4k.baseEepHeader.length; 106 107 if (el > sizeof(struct ar5416_eeprom_4k)) 108 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); 109 else 110 el = el / sizeof(u16); 111 112 eepdata = (u16 *)(&ah->eeprom); 113 114 for (i = 0; i < el; i++) 115 sum ^= *eepdata++; 116 117 if (need_swap) { 118 u32 integer; 119 u16 word; 120 121 ath_dbg(common, ATH_DBG_EEPROM, 122 "EEPROM Endianness is not native.. Changing\n"); 123 124 word = swab16(eep->baseEepHeader.length); 125 eep->baseEepHeader.length = word; 126 127 word = swab16(eep->baseEepHeader.checksum); 128 eep->baseEepHeader.checksum = word; 129 130 word = swab16(eep->baseEepHeader.version); 131 eep->baseEepHeader.version = word; 132 133 word = swab16(eep->baseEepHeader.regDmn[0]); 134 eep->baseEepHeader.regDmn[0] = word; 135 136 word = swab16(eep->baseEepHeader.regDmn[1]); 137 eep->baseEepHeader.regDmn[1] = word; 138 139 word = swab16(eep->baseEepHeader.rfSilent); 140 eep->baseEepHeader.rfSilent = word; 141 142 word = swab16(eep->baseEepHeader.blueToothOptions); 143 eep->baseEepHeader.blueToothOptions = word; 144 145 word = swab16(eep->baseEepHeader.deviceCap); 146 eep->baseEepHeader.deviceCap = word; 147 148 integer = swab32(eep->modalHeader.antCtrlCommon); 149 eep->modalHeader.antCtrlCommon = integer; 150 151 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { 152 integer = swab32(eep->modalHeader.antCtrlChain[i]); 153 eep->modalHeader.antCtrlChain[i] = integer; 154 } 155 156 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 157 word = swab16(eep->modalHeader.spurChans[i].spurChan); 158 eep->modalHeader.spurChans[i].spurChan = word; 159 } 160 } 161 162 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 163 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 164 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 165 sum, ah->eep_ops->get_eeprom_ver(ah)); 166 return -EINVAL; 167 } 168 169 return 0; 170#undef EEPROM_4K_SIZE 171} 172 173static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, 174 enum eeprom_param param) 175{ 176 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 177 struct modal_eep_4k_header *pModal = &eep->modalHeader; 178 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 179 u16 ver_minor; 180 181 ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK; 182 183 switch (param) { 184 case EEP_NFTHRESH_2: 185 return pModal->noiseFloorThreshCh[0]; 186 case EEP_MAC_LSW: 187 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 188 case EEP_MAC_MID: 189 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 190 case EEP_MAC_MSW: 191 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 192 case EEP_REG_0: 193 return pBase->regDmn[0]; 194 case EEP_REG_1: 195 return pBase->regDmn[1]; 196 case EEP_OP_CAP: 197 return pBase->deviceCap; 198 case EEP_OP_MODE: 199 return pBase->opCapFlags; 200 case EEP_RF_SILENT: 201 return pBase->rfSilent; 202 case EEP_OB_2: 203 return pModal->ob_0; 204 case EEP_DB_2: 205 return pModal->db1_1; 206 case EEP_MINOR_REV: 207 return ver_minor; 208 case EEP_TX_MASK: 209 return pBase->txMask; 210 case EEP_RX_MASK: 211 return pBase->rxMask; 212 case EEP_FRAC_N_5G: 213 return 0; 214 case EEP_PWR_TABLE_OFFSET: 215 return AR5416_PWR_TABLE_OFFSET_DB; 216 case EEP_MODAL_VER: 217 return pModal->version; 218 case EEP_ANT_DIV_CTL1: 219 return pModal->antdiv_ctl1; 220 case EEP_TXGAIN_TYPE: 221 if (ver_minor >= AR5416_EEP_MINOR_VER_19) 222 return pBase->txGainType; 223 else 224 return AR5416_EEP_TXGAIN_ORIGINAL; 225 default: 226 return 0; 227 } 228} 229 230static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, 231 struct ath9k_channel *chan, 232 struct cal_data_per_freq_4k *pRawDataSet, 233 u8 *bChans, u16 availPiers, 234 u16 tPdGainOverlap, 235 u16 *pPdGainBoundaries, u8 *pPDADCValues, 236 u16 numXpdGains) 237{ 238#define TMP_VAL_VPD_TABLE \ 239 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep)); 240 int i, j, k; 241 int16_t ss; 242 u16 idxL = 0, idxR = 0, numPiers; 243 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS] 244 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 245 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS] 246 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 247 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS] 248 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 249 250 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; 251 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS]; 252 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS]; 253 int16_t vpdStep; 254 int16_t tmpVal; 255 u16 sizeCurrVpdTable, maxIndex, tgtIndex; 256 bool match; 257 int16_t minDelta = 0; 258 struct chan_centers centers; 259#define PD_GAIN_BOUNDARY_DEFAULT 58; 260 261 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS); 262 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 263 264 for (numPiers = 0; numPiers < availPiers; numPiers++) { 265 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) 266 break; 267 } 268 269 match = ath9k_hw_get_lower_upper_index( 270 (u8)FREQ2FBIN(centers.synth_center, 271 IS_CHAN_2GHZ(chan)), bChans, numPiers, 272 &idxL, &idxR); 273 274 if (match) { 275 for (i = 0; i < numXpdGains; i++) { 276 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 277 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 278 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 279 pRawDataSet[idxL].pwrPdg[i], 280 pRawDataSet[idxL].vpdPdg[i], 281 AR5416_PD_GAIN_ICEPTS, 282 vpdTableI[i]); 283 } 284 } else { 285 for (i = 0; i < numXpdGains; i++) { 286 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 287 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 288 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 289 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 290 291 minPwrT4[i] = max(pPwrL[0], pPwrR[0]); 292 293 maxPwrT4[i] = 294 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], 295 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 296 297 298 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 299 pPwrL, pVpdL, 300 AR5416_PD_GAIN_ICEPTS, 301 vpdTableL[i]); 302 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 303 pPwrR, pVpdR, 304 AR5416_PD_GAIN_ICEPTS, 305 vpdTableR[i]); 306 307 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 308 vpdTableI[i][j] = 309 (u8)(ath9k_hw_interpolate((u16) 310 FREQ2FBIN(centers. 311 synth_center, 312 IS_CHAN_2GHZ 313 (chan)), 314 bChans[idxL], bChans[idxR], 315 vpdTableL[i][j], vpdTableR[i][j])); 316 } 317 } 318 } 319 320 k = 0; 321 322 for (i = 0; i < numXpdGains; i++) { 323 if (i == (numXpdGains - 1)) 324 pPdGainBoundaries[i] = 325 (u16)(maxPwrT4[i] / 2); 326 else 327 pPdGainBoundaries[i] = 328 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); 329 330 pPdGainBoundaries[i] = 331 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]); 332 333 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { 334 minDelta = pPdGainBoundaries[0] - 23; 335 pPdGainBoundaries[0] = 23; 336 } else { 337 minDelta = 0; 338 } 339 340 if (i == 0) { 341 if (AR_SREV_9280_20_OR_LATER(ah)) 342 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 343 else 344 ss = 0; 345 } else { 346 ss = (int16_t)((pPdGainBoundaries[i - 1] - 347 (minPwrT4[i] / 2)) - 348 tPdGainOverlap + 1 + minDelta); 349 } 350 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 351 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 352 353 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 354 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 355 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); 356 ss++; 357 } 358 359 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); 360 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - 361 (minPwrT4[i] / 2)); 362 maxIndex = (tgtIndex < sizeCurrVpdTable) ? 363 tgtIndex : sizeCurrVpdTable; 364 365 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) 366 pPDADCValues[k++] = vpdTableI[i][ss++]; 367 368 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - 369 vpdTableI[i][sizeCurrVpdTable - 2]); 370 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 371 372 if (tgtIndex >= maxIndex) { 373 while ((ss <= tgtIndex) && 374 (k < (AR5416_NUM_PDADC_VALUES - 1))) { 375 tmpVal = (int16_t) TMP_VAL_VPD_TABLE; 376 pPDADCValues[k++] = (u8)((tmpVal > 255) ? 377 255 : tmpVal); 378 ss++; 379 } 380 } 381 } 382 383 while (i < AR5416_PD_GAINS_IN_MASK) { 384 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT; 385 i++; 386 } 387 388 while (k < AR5416_NUM_PDADC_VALUES) { 389 pPDADCValues[k] = pPDADCValues[k - 1]; 390 k++; 391 } 392 393 return; 394#undef TMP_VAL_VPD_TABLE 395} 396 397static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 398 struct ath9k_channel *chan, 399 int16_t *pTxPowerIndexOffset) 400{ 401 struct ath_common *common = ath9k_hw_common(ah); 402 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 403 struct cal_data_per_freq_4k *pRawDataset; 404 u8 *pCalBChans = NULL; 405 u16 pdGainOverlap_t2; 406 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 407 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 408 u16 numPiers, i, j; 409 u16 numXpdGain, xpdMask; 410 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; 411 u32 reg32, regOffset, regChainOffset; 412 413 xpdMask = pEepData->modalHeader.xpdGain; 414 415 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 416 AR5416_EEP_MINOR_VER_2) { 417 pdGainOverlap_t2 = 418 pEepData->modalHeader.pdGainOverlap; 419 } else { 420 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), 421 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 422 } 423 424 pCalBChans = pEepData->calFreqPier2G; 425 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS; 426 427 numXpdGain = 0; 428 429 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 430 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 431 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) 432 break; 433 xpdGainValues[numXpdGain] = 434 (u16)(AR5416_PD_GAINS_IN_MASK - i); 435 numXpdGain++; 436 } 437 } 438 439 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 440 (numXpdGain - 1) & 0x3); 441 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 442 xpdGainValues[0]); 443 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, 444 xpdGainValues[1]); 445 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0); 446 447 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { 448 if (AR_SREV_5416_20_OR_LATER(ah) && 449 (ah->rxchainmask == 5 || ah->txchainmask == 5) && 450 (i != 0)) { 451 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 452 } else 453 regChainOffset = i * 0x1000; 454 455 if (pEepData->baseEepHeader.txMask & (1 << i)) { 456 pRawDataset = pEepData->calPierData2G[i]; 457 458 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan, 459 pRawDataset, pCalBChans, 460 numPiers, pdGainOverlap_t2, 461 gainBoundaries, 462 pdadcValues, numXpdGain); 463 464 ENABLE_REGWRITE_BUFFER(ah); 465 466 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 467 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 468 SM(pdGainOverlap_t2, 469 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) 470 | SM(gainBoundaries[0], 471 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) 472 | SM(gainBoundaries[1], 473 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) 474 | SM(gainBoundaries[2], 475 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) 476 | SM(gainBoundaries[3], 477 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 478 } 479 480 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 481 for (j = 0; j < 32; j++) { 482 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 483 ((pdadcValues[4 * j + 1] & 0xFF) << 8) | 484 ((pdadcValues[4 * j + 2] & 0xFF) << 16)| 485 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 486 REG_WRITE(ah, regOffset, reg32); 487 488 ath_dbg(common, ATH_DBG_EEPROM, 489 "PDADC (%d,%4x): %4.4x %8.8x\n", 490 i, regChainOffset, regOffset, 491 reg32); 492 ath_dbg(common, ATH_DBG_EEPROM, 493 "PDADC: Chain %d | " 494 "PDADC %3d Value %3d | " 495 "PDADC %3d Value %3d | " 496 "PDADC %3d Value %3d | " 497 "PDADC %3d Value %3d |\n", 498 i, 4 * j, pdadcValues[4 * j], 499 4 * j + 1, pdadcValues[4 * j + 1], 500 4 * j + 2, pdadcValues[4 * j + 2], 501 4 * j + 3, pdadcValues[4 * j + 3]); 502 503 regOffset += 4; 504 } 505 506 REGWRITE_BUFFER_FLUSH(ah); 507 } 508 } 509 510 *pTxPowerIndexOffset = 0; 511} 512 513static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, 514 struct ath9k_channel *chan, 515 int16_t *ratesArray, 516 u16 cfgCtl, 517 u16 AntennaReduction, 518 u16 twiceMaxRegulatoryPower, 519 u16 powerLimit) 520{ 521#define CMP_TEST_GRP \ 522 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 523 pEepData->ctlIndex[i]) \ 524 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 525 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) 526 527 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 528 int i; 529 int16_t twiceLargestAntenna; 530 u16 twiceMinEdgePower; 531 u16 twiceMaxEdgePower = MAX_RATE_POWER; 532 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 533 u16 numCtlModes; 534 const u16 *pCtlMode; 535 u16 ctlMode, freq; 536 struct chan_centers centers; 537 struct cal_ctl_data_4k *rep; 538 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 539 static const u16 tpScaleReductionTable[5] = 540 { 0, 3, 6, 9, MAX_RATE_POWER }; 541 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 542 0, { 0, 0, 0, 0} 543 }; 544 struct cal_target_power_leg targetPowerOfdmExt = { 545 0, { 0, 0, 0, 0} }, targetPowerCckExt = { 546 0, { 0, 0, 0, 0 } 547 }; 548 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 549 0, {0, 0, 0, 0} 550 }; 551 static const u16 ctlModesFor11g[] = { 552 CTL_11B, CTL_11G, CTL_2GHT20, 553 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 554 }; 555 556 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 557 558 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 559 twiceLargestAntenna = (int16_t)min(AntennaReduction - 560 twiceLargestAntenna, 0); 561 562 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 563 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) { 564 maxRegAllowedPower -= 565 (tpScaleReductionTable[(regulatory->tp_scale)] * 2); 566 } 567 568 scaledPower = min(powerLimit, maxRegAllowedPower); 569 scaledPower = max((u16)0, scaledPower); 570 571 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; 572 pCtlMode = ctlModesFor11g; 573 574 ath9k_hw_get_legacy_target_powers(ah, chan, 575 pEepData->calTargetPowerCck, 576 AR5416_NUM_2G_CCK_TARGET_POWERS, 577 &targetPowerCck, 4, false); 578 ath9k_hw_get_legacy_target_powers(ah, chan, 579 pEepData->calTargetPower2G, 580 AR5416_NUM_2G_20_TARGET_POWERS, 581 &targetPowerOfdm, 4, false); 582 ath9k_hw_get_target_powers(ah, chan, 583 pEepData->calTargetPower2GHT20, 584 AR5416_NUM_2G_20_TARGET_POWERS, 585 &targetPowerHt20, 8, false); 586 587 if (IS_CHAN_HT40(chan)) { 588 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 589 ath9k_hw_get_target_powers(ah, chan, 590 pEepData->calTargetPower2GHT40, 591 AR5416_NUM_2G_40_TARGET_POWERS, 592 &targetPowerHt40, 8, true); 593 ath9k_hw_get_legacy_target_powers(ah, chan, 594 pEepData->calTargetPowerCck, 595 AR5416_NUM_2G_CCK_TARGET_POWERS, 596 &targetPowerCckExt, 4, true); 597 ath9k_hw_get_legacy_target_powers(ah, chan, 598 pEepData->calTargetPower2G, 599 AR5416_NUM_2G_20_TARGET_POWERS, 600 &targetPowerOfdmExt, 4, true); 601 } 602 603 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 604 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 605 (pCtlMode[ctlMode] == CTL_2GHT40); 606 607 if (isHt40CtlMode) 608 freq = centers.synth_center; 609 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 610 freq = centers.ext_center; 611 else 612 freq = centers.ctl_center; 613 614 if (ah->eep_ops->get_eeprom_ver(ah) == 14 && 615 ah->eep_ops->get_eeprom_rev(ah) <= 2) 616 twiceMaxEdgePower = MAX_RATE_POWER; 617 618 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && 619 pEepData->ctlIndex[i]; i++) { 620 621 if (CMP_TEST_GRP) { 622 rep = &(pEepData->ctlData[i]); 623 624 twiceMinEdgePower = ath9k_hw_get_max_edge_power( 625 freq, 626 rep->ctlEdges[ 627 ar5416_get_ntxchains(ah->txchainmask) - 1], 628 IS_CHAN_2GHZ(chan), 629 AR5416_EEP4K_NUM_BAND_EDGES); 630 631 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 632 twiceMaxEdgePower = 633 min(twiceMaxEdgePower, 634 twiceMinEdgePower); 635 } else { 636 twiceMaxEdgePower = twiceMinEdgePower; 637 break; 638 } 639 } 640 } 641 642 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 643 644 switch (pCtlMode[ctlMode]) { 645 case CTL_11B: 646 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 647 targetPowerCck.tPow2x[i] = 648 min((u16)targetPowerCck.tPow2x[i], 649 minCtlPower); 650 } 651 break; 652 case CTL_11G: 653 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { 654 targetPowerOfdm.tPow2x[i] = 655 min((u16)targetPowerOfdm.tPow2x[i], 656 minCtlPower); 657 } 658 break; 659 case CTL_2GHT20: 660 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { 661 targetPowerHt20.tPow2x[i] = 662 min((u16)targetPowerHt20.tPow2x[i], 663 minCtlPower); 664 } 665 break; 666 case CTL_11B_EXT: 667 targetPowerCckExt.tPow2x[0] = 668 min((u16)targetPowerCckExt.tPow2x[0], 669 minCtlPower); 670 break; 671 case CTL_11G_EXT: 672 targetPowerOfdmExt.tPow2x[0] = 673 min((u16)targetPowerOfdmExt.tPow2x[0], 674 minCtlPower); 675 break; 676 case CTL_2GHT40: 677 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 678 targetPowerHt40.tPow2x[i] = 679 min((u16)targetPowerHt40.tPow2x[i], 680 minCtlPower); 681 } 682 break; 683 default: 684 break; 685 } 686 } 687 688 ratesArray[rate6mb] = 689 ratesArray[rate9mb] = 690 ratesArray[rate12mb] = 691 ratesArray[rate18mb] = 692 ratesArray[rate24mb] = 693 targetPowerOfdm.tPow2x[0]; 694 695 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 696 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 697 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 698 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 699 700 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) 701 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 702 703 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 704 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 705 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 706 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 707 708 if (IS_CHAN_HT40(chan)) { 709 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 710 ratesArray[rateHt40_0 + i] = 711 targetPowerHt40.tPow2x[i]; 712 } 713 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 714 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 715 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 716 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 717 } 718 719#undef CMP_TEST_GRP 720} 721 722static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, 723 struct ath9k_channel *chan, 724 u16 cfgCtl, 725 u8 twiceAntennaReduction, 726 u8 twiceMaxRegulatoryPower, 727 u8 powerLimit, bool test) 728{ 729 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 730 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 731 struct modal_eep_4k_header *pModal = &pEepData->modalHeader; 732 int16_t ratesArray[Ar5416RateSize]; 733 int16_t txPowerIndexOffset = 0; 734 u8 ht40PowerIncForPdadc = 2; 735 int i; 736 737 memset(ratesArray, 0, sizeof(ratesArray)); 738 739 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 740 AR5416_EEP_MINOR_VER_2) { 741 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 742 } 743 744 ath9k_hw_set_4k_power_per_rate_table(ah, chan, 745 &ratesArray[0], cfgCtl, 746 twiceAntennaReduction, 747 twiceMaxRegulatoryPower, 748 powerLimit); 749 750 ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset); 751 752 regulatory->max_power_level = 0; 753 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 754 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 755 if (ratesArray[i] > MAX_RATE_POWER) 756 ratesArray[i] = MAX_RATE_POWER; 757 758 if (ratesArray[i] > regulatory->max_power_level) 759 regulatory->max_power_level = ratesArray[i]; 760 } 761 762 if (test) 763 return; 764 765 /* Update regulatory */ 766 i = rate6mb; 767 if (IS_CHAN_HT40(chan)) 768 i = rateHt40_0; 769 else if (IS_CHAN_HT20(chan)) 770 i = rateHt20_0; 771 772 regulatory->max_power_level = ratesArray[i]; 773 774 if (AR_SREV_9280_20_OR_LATER(ah)) { 775 for (i = 0; i < Ar5416RateSize; i++) 776 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 777 } 778 779 ENABLE_REGWRITE_BUFFER(ah); 780 781 /* OFDM power per rate */ 782 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 783 ATH9K_POW_SM(ratesArray[rate18mb], 24) 784 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 785 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 786 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); 787 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 788 ATH9K_POW_SM(ratesArray[rate54mb], 24) 789 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 790 | ATH9K_POW_SM(ratesArray[rate36mb], 8) 791 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); 792 793 /* CCK power per rate */ 794 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 795 ATH9K_POW_SM(ratesArray[rate2s], 24) 796 | ATH9K_POW_SM(ratesArray[rate2l], 16) 797 | ATH9K_POW_SM(ratesArray[rateXr], 8) 798 | ATH9K_POW_SM(ratesArray[rate1l], 0)); 799 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 800 ATH9K_POW_SM(ratesArray[rate11s], 24) 801 | ATH9K_POW_SM(ratesArray[rate11l], 16) 802 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) 803 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); 804 805 /* HT20 power per rate */ 806 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 807 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 808 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 809 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 810 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); 811 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 812 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) 813 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) 814 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) 815 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); 816 817 /* HT40 power per rate */ 818 if (IS_CHAN_HT40(chan)) { 819 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 820 ATH9K_POW_SM(ratesArray[rateHt40_3] + 821 ht40PowerIncForPdadc, 24) 822 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 823 ht40PowerIncForPdadc, 16) 824 | ATH9K_POW_SM(ratesArray[rateHt40_1] + 825 ht40PowerIncForPdadc, 8) 826 | ATH9K_POW_SM(ratesArray[rateHt40_0] + 827 ht40PowerIncForPdadc, 0)); 828 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 829 ATH9K_POW_SM(ratesArray[rateHt40_7] + 830 ht40PowerIncForPdadc, 24) 831 | ATH9K_POW_SM(ratesArray[rateHt40_6] + 832 ht40PowerIncForPdadc, 16) 833 | ATH9K_POW_SM(ratesArray[rateHt40_5] + 834 ht40PowerIncForPdadc, 8) 835 | ATH9K_POW_SM(ratesArray[rateHt40_4] + 836 ht40PowerIncForPdadc, 0)); 837 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 838 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 839 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 840 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 841 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 842 } 843 844 REGWRITE_BUFFER_FLUSH(ah); 845} 846 847static void ath9k_hw_4k_set_addac(struct ath_hw *ah, 848 struct ath9k_channel *chan) 849{ 850 struct modal_eep_4k_header *pModal; 851 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 852 u8 biaslevel; 853 854 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) 855 return; 856 857 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) 858 return; 859 860 pModal = &eep->modalHeader; 861 862 if (pModal->xpaBiasLvl != 0xff) { 863 biaslevel = pModal->xpaBiasLvl; 864 INI_RA(&ah->iniAddac, 7, 1) = 865 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; 866 } 867} 868 869static void ath9k_hw_4k_set_gain(struct ath_hw *ah, 870 struct modal_eep_4k_header *pModal, 871 struct ar5416_eeprom_4k *eep, 872 u8 txRxAttenLocal) 873{ 874 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 875 pModal->antCtrlChain[0]); 876 877 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), 878 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & 879 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 880 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 881 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 882 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 883 884 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 885 AR5416_EEP_MINOR_VER_3) { 886 txRxAttenLocal = pModal->txRxAttenCh[0]; 887 888 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 889 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 890 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 891 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 892 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 893 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 894 pModal->xatten2Margin[0]); 895 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 896 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 897 898 /* Set the block 1 value to block 0 value */ 899 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 900 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 901 pModal->bswMargin[0]); 902 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 903 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 904 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 905 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 906 pModal->xatten2Margin[0]); 907 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 908 AR_PHY_GAIN_2GHZ_XATTEN2_DB, 909 pModal->xatten2Db[0]); 910 } 911 912 REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 913 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 914 REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 915 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 916 917 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 918 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 919 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 920 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 921} 922 923/* 924 * Read EEPROM header info and program the device for correct operation 925 * given the channel value. 926 */ 927static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, 928 struct ath9k_channel *chan) 929{ 930 struct modal_eep_4k_header *pModal; 931 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 932 u8 txRxAttenLocal; 933 u8 ob[5], db1[5], db2[5]; 934 u8 ant_div_control1, ant_div_control2; 935 u32 regVal; 936 937 pModal = &eep->modalHeader; 938 txRxAttenLocal = 23; 939 940 REG_WRITE(ah, AR_PHY_SWITCH_COM, 941 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); 942 943 /* Single chain for 4K EEPROM*/ 944 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal); 945 946 /* Initialize Ant Diversity settings from EEPROM */ 947 if (pModal->version >= 3) { 948 ant_div_control1 = pModal->antdiv_ctl1; 949 ant_div_control2 = pModal->antdiv_ctl2; 950 951 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 952 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 953 954 regVal |= SM(ant_div_control1, 955 AR_PHY_9285_ANT_DIV_CTL); 956 regVal |= SM(ant_div_control2, 957 AR_PHY_9285_ANT_DIV_ALT_LNACONF); 958 regVal |= SM((ant_div_control2 >> 2), 959 AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 960 regVal |= SM((ant_div_control1 >> 1), 961 AR_PHY_9285_ANT_DIV_ALT_GAINTB); 962 regVal |= SM((ant_div_control1 >> 2), 963 AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 964 965 966 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 967 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 968 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); 969 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 970 regVal |= SM((ant_div_control1 >> 3), 971 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 972 973 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 974 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); 975 } 976 977 if (pModal->version >= 2) { 978 ob[0] = pModal->ob_0; 979 ob[1] = pModal->ob_1; 980 ob[2] = pModal->ob_2; 981 ob[3] = pModal->ob_3; 982 ob[4] = pModal->ob_4; 983 984 db1[0] = pModal->db1_0; 985 db1[1] = pModal->db1_1; 986 db1[2] = pModal->db1_2; 987 db1[3] = pModal->db1_3; 988 db1[4] = pModal->db1_4; 989 990 db2[0] = pModal->db2_0; 991 db2[1] = pModal->db2_1; 992 db2[2] = pModal->db2_2; 993 db2[3] = pModal->db2_3; 994 db2[4] = pModal->db2_4; 995 } else if (pModal->version == 1) { 996 ob[0] = pModal->ob_0; 997 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 998 db1[0] = pModal->db1_0; 999 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 1000 db2[0] = pModal->db2_0; 1001 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 1002 } else { 1003 int i; 1004 1005 for (i = 0; i < 5; i++) { 1006 ob[i] = pModal->ob_0; 1007 db1[i] = pModal->db1_0; 1008 db2[i] = pModal->db1_0; 1009 } 1010 } 1011 1012 if (AR_SREV_9271(ah)) { 1013 ath9k_hw_analog_shift_rmw(ah, 1014 AR9285_AN_RF2G3, 1015 AR9271_AN_RF2G3_OB_cck, 1016 AR9271_AN_RF2G3_OB_cck_S, 1017 ob[0]); 1018 ath9k_hw_analog_shift_rmw(ah, 1019 AR9285_AN_RF2G3, 1020 AR9271_AN_RF2G3_OB_psk, 1021 AR9271_AN_RF2G3_OB_psk_S, 1022 ob[1]); 1023 ath9k_hw_analog_shift_rmw(ah, 1024 AR9285_AN_RF2G3, 1025 AR9271_AN_RF2G3_OB_qam, 1026 AR9271_AN_RF2G3_OB_qam_S, 1027 ob[2]); 1028 ath9k_hw_analog_shift_rmw(ah, 1029 AR9285_AN_RF2G3, 1030 AR9271_AN_RF2G3_DB_1, 1031 AR9271_AN_RF2G3_DB_1_S, 1032 db1[0]); 1033 ath9k_hw_analog_shift_rmw(ah, 1034 AR9285_AN_RF2G4, 1035 AR9271_AN_RF2G4_DB_2, 1036 AR9271_AN_RF2G4_DB_2_S, 1037 db2[0]); 1038 } else { 1039 ath9k_hw_analog_shift_rmw(ah, 1040 AR9285_AN_RF2G3, 1041 AR9285_AN_RF2G3_OB_0, 1042 AR9285_AN_RF2G3_OB_0_S, 1043 ob[0]); 1044 ath9k_hw_analog_shift_rmw(ah, 1045 AR9285_AN_RF2G3, 1046 AR9285_AN_RF2G3_OB_1, 1047 AR9285_AN_RF2G3_OB_1_S, 1048 ob[1]); 1049 ath9k_hw_analog_shift_rmw(ah, 1050 AR9285_AN_RF2G3, 1051 AR9285_AN_RF2G3_OB_2, 1052 AR9285_AN_RF2G3_OB_2_S, 1053 ob[2]); 1054 ath9k_hw_analog_shift_rmw(ah, 1055 AR9285_AN_RF2G3, 1056 AR9285_AN_RF2G3_OB_3, 1057 AR9285_AN_RF2G3_OB_3_S, 1058 ob[3]); 1059 ath9k_hw_analog_shift_rmw(ah, 1060 AR9285_AN_RF2G3, 1061 AR9285_AN_RF2G3_OB_4, 1062 AR9285_AN_RF2G3_OB_4_S, 1063 ob[4]); 1064 1065 ath9k_hw_analog_shift_rmw(ah, 1066 AR9285_AN_RF2G3, 1067 AR9285_AN_RF2G3_DB1_0, 1068 AR9285_AN_RF2G3_DB1_0_S, 1069 db1[0]); 1070 ath9k_hw_analog_shift_rmw(ah, 1071 AR9285_AN_RF2G3, 1072 AR9285_AN_RF2G3_DB1_1, 1073 AR9285_AN_RF2G3_DB1_1_S, 1074 db1[1]); 1075 ath9k_hw_analog_shift_rmw(ah, 1076 AR9285_AN_RF2G3, 1077 AR9285_AN_RF2G3_DB1_2, 1078 AR9285_AN_RF2G3_DB1_2_S, 1079 db1[2]); 1080 ath9k_hw_analog_shift_rmw(ah, 1081 AR9285_AN_RF2G4, 1082 AR9285_AN_RF2G4_DB1_3, 1083 AR9285_AN_RF2G4_DB1_3_S, 1084 db1[3]); 1085 ath9k_hw_analog_shift_rmw(ah, 1086 AR9285_AN_RF2G4, 1087 AR9285_AN_RF2G4_DB1_4, 1088 AR9285_AN_RF2G4_DB1_4_S, db1[4]); 1089 1090 ath9k_hw_analog_shift_rmw(ah, 1091 AR9285_AN_RF2G4, 1092 AR9285_AN_RF2G4_DB2_0, 1093 AR9285_AN_RF2G4_DB2_0_S, 1094 db2[0]); 1095 ath9k_hw_analog_shift_rmw(ah, 1096 AR9285_AN_RF2G4, 1097 AR9285_AN_RF2G4_DB2_1, 1098 AR9285_AN_RF2G4_DB2_1_S, 1099 db2[1]); 1100 ath9k_hw_analog_shift_rmw(ah, 1101 AR9285_AN_RF2G4, 1102 AR9285_AN_RF2G4_DB2_2, 1103 AR9285_AN_RF2G4_DB2_2_S, 1104 db2[2]); 1105 ath9k_hw_analog_shift_rmw(ah, 1106 AR9285_AN_RF2G4, 1107 AR9285_AN_RF2G4_DB2_3, 1108 AR9285_AN_RF2G4_DB2_3_S, 1109 db2[3]); 1110 ath9k_hw_analog_shift_rmw(ah, 1111 AR9285_AN_RF2G4, 1112 AR9285_AN_RF2G4_DB2_4, 1113 AR9285_AN_RF2G4_DB2_4_S, 1114 db2[4]); 1115 } 1116 1117 1118 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 1119 pModal->switchSettling); 1120 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 1121 pModal->adcDesiredSize); 1122 1123 REG_WRITE(ah, AR_PHY_RF_CTL4, 1124 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 1125 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 1126 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 1127 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1128 1129 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1130 pModal->txEndToRxOn); 1131 1132 if (AR_SREV_9271_10(ah)) 1133 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1134 pModal->txEndToRxOn); 1135 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1136 pModal->thresh62); 1137 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1138 pModal->thresh62); 1139 1140 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1141 AR5416_EEP_MINOR_VER_2) { 1142 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, 1143 pModal->txFrameToDataStart); 1144 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, 1145 pModal->txFrameToPaOn); 1146 } 1147 1148 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1149 AR5416_EEP_MINOR_VER_3) { 1150 if (IS_CHAN_HT40(chan)) 1151 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 1152 AR_PHY_SETTLING_SWITCH, 1153 pModal->swSettleHt40); 1154 } 1155} 1156 1157static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, 1158 struct ath9k_channel *chan) 1159{ 1160 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 1161 struct modal_eep_4k_header *pModal = &eep->modalHeader; 1162 1163 return pModal->antCtrlCommon; 1164} 1165 1166static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah, 1167 enum ath9k_hal_freq_band freq_band) 1168{ 1169 return 1; 1170} 1171 1172static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 1173{ 1174#define EEP_MAP4K_SPURCHAN \ 1175 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) 1176 struct ath_common *common = ath9k_hw_common(ah); 1177 1178 u16 spur_val = AR_NO_SPUR; 1179 1180 ath_dbg(common, ATH_DBG_ANI, 1181 "Getting spur idx:%d is2Ghz:%d val:%x\n", 1182 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1183 1184 switch (ah->config.spurmode) { 1185 case SPUR_DISABLE: 1186 break; 1187 case SPUR_ENABLE_IOCTL: 1188 spur_val = ah->config.spurchans[i][is2GHz]; 1189 ath_dbg(common, ATH_DBG_ANI, 1190 "Getting spur val from new loc. %d\n", spur_val); 1191 break; 1192 case SPUR_ENABLE_EEPROM: 1193 spur_val = EEP_MAP4K_SPURCHAN; 1194 break; 1195 } 1196 1197 return spur_val; 1198 1199#undef EEP_MAP4K_SPURCHAN 1200} 1201 1202const struct eeprom_ops eep_4k_ops = { 1203 .check_eeprom = ath9k_hw_4k_check_eeprom, 1204 .get_eeprom = ath9k_hw_4k_get_eeprom, 1205 .fill_eeprom = ath9k_hw_4k_fill_eeprom, 1206 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, 1207 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, 1208 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config, 1209 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg, 1210 .set_board_values = ath9k_hw_4k_set_board_values, 1211 .set_addac = ath9k_hw_4k_set_addac, 1212 .set_txpower = ath9k_hw_4k_set_txpower, 1213 .get_spur_channel = ath9k_hw_4k_get_spur_channel 1214}; 1215