1/****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 4 * 5 * Portions of this file are derived from the ipw3945 project, as well 6 * as portions of the ieee80211 subsystem header files. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of version 2 of the GNU General Public License as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 20 * 21 * The full GNU General Public License is included in this distribution in the 22 * file called LICENSE. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <ilw@linux.intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 *****************************************************************************/ 29 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 31 32#include <linux/kernel.h> 33#include <linux/module.h> 34#include <linux/init.h> 35#include <linux/pci.h> 36#include <linux/pci-aspm.h> 37#include <linux/slab.h> 38#include <linux/dma-mapping.h> 39#include <linux/delay.h> 40#include <linux/sched.h> 41#include <linux/skbuff.h> 42#include <linux/netdevice.h> 43#include <linux/firmware.h> 44#include <linux/etherdevice.h> 45#include <linux/if_arp.h> 46 47#include <net/mac80211.h> 48 49#include <asm/div64.h> 50 51#define DRV_NAME "iwl4965" 52 53#include "common.h" 54#include "4965.h" 55 56/****************************************************************************** 57 * 58 * module boiler plate 59 * 60 ******************************************************************************/ 61 62/* 63 * module name, copyright, version, etc. 64 */ 65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux" 66 67#ifdef CONFIG_IWLEGACY_DEBUG 68#define VD "d" 69#else 70#define VD 71#endif 72 73#define DRV_VERSION IWLWIFI_VERSION VD 74 75MODULE_DESCRIPTION(DRV_DESCRIPTION); 76MODULE_VERSION(DRV_VERSION); 77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); 78MODULE_LICENSE("GPL"); 79MODULE_ALIAS("iwl4965"); 80 81void 82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status) 83{ 84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) { 85 IL_ERR("Tx flush command to flush out all frames\n"); 86 if (!test_bit(S_EXIT_PENDING, &il->status)) 87 queue_work(il->workqueue, &il->tx_flush); 88 } 89} 90 91/* 92 * EEPROM 93 */ 94struct il_mod_params il4965_mod_params = { 95 .amsdu_size_8K = 1, 96 .restart_fw = 1, 97 /* the rest are 0 by default */ 98}; 99 100void 101il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq) 102{ 103 unsigned long flags; 104 int i; 105 spin_lock_irqsave(&rxq->lock, flags); 106 INIT_LIST_HEAD(&rxq->rx_free); 107 INIT_LIST_HEAD(&rxq->rx_used); 108 /* Fill the rx_used queue with _all_ of the Rx buffers */ 109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { 110 /* In the reset function, these buffers may have been allocated 111 * to an SKB, so we need to unmap and free potential storage */ 112 if (rxq->pool[i].page != NULL) { 113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, 114 PAGE_SIZE << il->hw_params.rx_page_order, 115 PCI_DMA_FROMDEVICE); 116 __il_free_pages(il, rxq->pool[i].page); 117 rxq->pool[i].page = NULL; 118 } 119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used); 120 } 121 122 for (i = 0; i < RX_QUEUE_SIZE; i++) 123 rxq->queue[i] = NULL; 124 125 /* Set us so that we have processed and used all buffers, but have 126 * not restocked the Rx queue with fresh buffers */ 127 rxq->read = rxq->write = 0; 128 rxq->write_actual = 0; 129 rxq->free_count = 0; 130 spin_unlock_irqrestore(&rxq->lock, flags); 131} 132 133int 134il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 135{ 136 u32 rb_size; 137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 138 u32 rb_timeout = 0; 139 140 if (il->cfg->mod_params->amsdu_size_8K) 141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 142 else 143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 144 145 /* Stop Rx DMA */ 146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); 147 148 /* Reset driver's Rx queue write idx */ 149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 150 151 /* Tell device where to find RBD circular buffer in DRAM */ 152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8)); 153 154 /* Tell device where in DRAM to update its Rx status */ 155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4); 156 157 /* Enable Rx DMA 158 * Direct rx interrupts to hosts 159 * Rx buffer size 4 or 8k 160 * RB timeout 0x10 161 * 256 RBDs 162 */ 163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | 167 rb_size | 168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 170 171 /* Set interrupt coalescing timer to default (2048 usecs) */ 172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF); 173 174 return 0; 175} 176 177static void 178il4965_set_pwr_vmain(struct il_priv *il) 179{ 180/* 181 * (for documentation purposes) 182 * to set power to V_AUX, do: 183 184 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) 185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 187 ~APMG_PS_CTRL_MSK_PWR_SRC); 188 */ 189 190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 192 ~APMG_PS_CTRL_MSK_PWR_SRC); 193} 194 195int 196il4965_hw_nic_init(struct il_priv *il) 197{ 198 unsigned long flags; 199 struct il_rx_queue *rxq = &il->rxq; 200 int ret; 201 202 /* nic_init */ 203 spin_lock_irqsave(&il->lock, flags); 204 il->cfg->ops->lib->apm_ops.init(il); 205 206 /* Set interrupt coalescing calibration timer to default (512 usecs) */ 207 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF); 208 209 spin_unlock_irqrestore(&il->lock, flags); 210 211 il4965_set_pwr_vmain(il); 212 213 il->cfg->ops->lib->apm_ops.config(il); 214 215 /* Allocate the RX queue, or reset if it is already allocated */ 216 if (!rxq->bd) { 217 ret = il_rx_queue_alloc(il); 218 if (ret) { 219 IL_ERR("Unable to initialize Rx queue\n"); 220 return -ENOMEM; 221 } 222 } else 223 il4965_rx_queue_reset(il, rxq); 224 225 il4965_rx_replenish(il); 226 227 il4965_rx_init(il, rxq); 228 229 spin_lock_irqsave(&il->lock, flags); 230 231 rxq->need_update = 1; 232 il_rx_queue_update_write_ptr(il, rxq); 233 234 spin_unlock_irqrestore(&il->lock, flags); 235 236 /* Allocate or reset and init all Tx and Command queues */ 237 if (!il->txq) { 238 ret = il4965_txq_ctx_alloc(il); 239 if (ret) 240 return ret; 241 } else 242 il4965_txq_ctx_reset(il); 243 244 set_bit(S_INIT, &il->status); 245 246 return 0; 247} 248 249/** 250 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 251 */ 252static inline __le32 253il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr) 254{ 255 return cpu_to_le32((u32) (dma_addr >> 8)); 256} 257 258/** 259 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool 260 * 261 * If there are slots in the RX queue that need to be restocked, 262 * and we have free pre-allocated buffers, fill the ranks as much 263 * as we can, pulling from rx_free. 264 * 265 * This moves the 'write' idx forward to catch up with 'processed', and 266 * also updates the memory address in the firmware to reference the new 267 * target buffer. 268 */ 269void 270il4965_rx_queue_restock(struct il_priv *il) 271{ 272 struct il_rx_queue *rxq = &il->rxq; 273 struct list_head *element; 274 struct il_rx_buf *rxb; 275 unsigned long flags; 276 277 spin_lock_irqsave(&rxq->lock, flags); 278 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) { 279 /* The overwritten rxb must be a used one */ 280 rxb = rxq->queue[rxq->write]; 281 BUG_ON(rxb && rxb->page); 282 283 /* Get next free Rx buffer, remove from free list */ 284 element = rxq->rx_free.next; 285 rxb = list_entry(element, struct il_rx_buf, list); 286 list_del(element); 287 288 /* Point to Rx buffer via next RBD in circular buffer */ 289 rxq->bd[rxq->write] = 290 il4965_dma_addr2rbd_ptr(il, rxb->page_dma); 291 rxq->queue[rxq->write] = rxb; 292 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 293 rxq->free_count--; 294 } 295 spin_unlock_irqrestore(&rxq->lock, flags); 296 /* If the pre-allocated buffer pool is dropping low, schedule to 297 * refill it */ 298 if (rxq->free_count <= RX_LOW_WATERMARK) 299 queue_work(il->workqueue, &il->rx_replenish); 300 301 /* If we've added more space for the firmware to place data, tell it. 302 * Increment device's write pointer in multiples of 8. */ 303 if (rxq->write_actual != (rxq->write & ~0x7)) { 304 spin_lock_irqsave(&rxq->lock, flags); 305 rxq->need_update = 1; 306 spin_unlock_irqrestore(&rxq->lock, flags); 307 il_rx_queue_update_write_ptr(il, rxq); 308 } 309} 310 311/** 312 * il4965_rx_replenish - Move all used packet from rx_used to rx_free 313 * 314 * When moving to rx_free an SKB is allocated for the slot. 315 * 316 * Also restock the Rx queue via il_rx_queue_restock. 317 * This is called as a scheduled work item (except for during initialization) 318 */ 319static void 320il4965_rx_allocate(struct il_priv *il, gfp_t priority) 321{ 322 struct il_rx_queue *rxq = &il->rxq; 323 struct list_head *element; 324 struct il_rx_buf *rxb; 325 struct page *page; 326 unsigned long flags; 327 gfp_t gfp_mask = priority; 328 329 while (1) { 330 spin_lock_irqsave(&rxq->lock, flags); 331 if (list_empty(&rxq->rx_used)) { 332 spin_unlock_irqrestore(&rxq->lock, flags); 333 return; 334 } 335 spin_unlock_irqrestore(&rxq->lock, flags); 336 337 if (rxq->free_count > RX_LOW_WATERMARK) 338 gfp_mask |= __GFP_NOWARN; 339 340 if (il->hw_params.rx_page_order > 0) 341 gfp_mask |= __GFP_COMP; 342 343 /* Alloc a new receive buffer */ 344 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order); 345 if (!page) { 346 if (net_ratelimit()) 347 D_INFO("alloc_pages failed, " "order: %d\n", 348 il->hw_params.rx_page_order); 349 350 if (rxq->free_count <= RX_LOW_WATERMARK && 351 net_ratelimit()) 352 IL_ERR("Failed to alloc_pages with %s. " 353 "Only %u free buffers remaining.\n", 354 priority == 355 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", 356 rxq->free_count); 357 /* We don't reschedule replenish work here -- we will 358 * call the restock method and if it still needs 359 * more buffers it will schedule replenish */ 360 return; 361 } 362 363 spin_lock_irqsave(&rxq->lock, flags); 364 365 if (list_empty(&rxq->rx_used)) { 366 spin_unlock_irqrestore(&rxq->lock, flags); 367 __free_pages(page, il->hw_params.rx_page_order); 368 return; 369 } 370 element = rxq->rx_used.next; 371 rxb = list_entry(element, struct il_rx_buf, list); 372 list_del(element); 373 374 spin_unlock_irqrestore(&rxq->lock, flags); 375 376 BUG_ON(rxb->page); 377 rxb->page = page; 378 /* Get physical address of the RB */ 379 rxb->page_dma = 380 pci_map_page(il->pci_dev, page, 0, 381 PAGE_SIZE << il->hw_params.rx_page_order, 382 PCI_DMA_FROMDEVICE); 383 /* dma address must be no more than 36 bits */ 384 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); 385 /* and also 256 byte aligned! */ 386 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); 387 388 spin_lock_irqsave(&rxq->lock, flags); 389 390 list_add_tail(&rxb->list, &rxq->rx_free); 391 rxq->free_count++; 392 il->alloc_rxb_page++; 393 394 spin_unlock_irqrestore(&rxq->lock, flags); 395 } 396} 397 398void 399il4965_rx_replenish(struct il_priv *il) 400{ 401 unsigned long flags; 402 403 il4965_rx_allocate(il, GFP_KERNEL); 404 405 spin_lock_irqsave(&il->lock, flags); 406 il4965_rx_queue_restock(il); 407 spin_unlock_irqrestore(&il->lock, flags); 408} 409 410void 411il4965_rx_replenish_now(struct il_priv *il) 412{ 413 il4965_rx_allocate(il, GFP_ATOMIC); 414 415 il4965_rx_queue_restock(il); 416} 417 418/* Assumes that the skb field of the buffers in 'pool' is kept accurate. 419 * If an SKB has been detached, the POOL needs to have its SKB set to NULL 420 * This free routine walks the list of POOL entries and if SKB is set to 421 * non NULL it is unmapped and freed 422 */ 423void 424il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq) 425{ 426 int i; 427 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { 428 if (rxq->pool[i].page != NULL) { 429 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, 430 PAGE_SIZE << il->hw_params.rx_page_order, 431 PCI_DMA_FROMDEVICE); 432 __il_free_pages(il, rxq->pool[i].page); 433 rxq->pool[i].page = NULL; 434 } 435 } 436 437 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, 438 rxq->bd_dma); 439 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status), 440 rxq->rb_stts, rxq->rb_stts_dma); 441 rxq->bd = NULL; 442 rxq->rb_stts = NULL; 443} 444 445int 446il4965_rxq_stop(struct il_priv *il) 447{ 448 449 /* stop Rx DMA */ 450 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); 451 il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG, 452 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 453 454 return 0; 455} 456 457int 458il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band) 459{ 460 int idx = 0; 461 int band_offset = 0; 462 463 /* HT rate format: mac80211 wants an MCS number, which is just LSB */ 464 if (rate_n_flags & RATE_MCS_HT_MSK) { 465 idx = (rate_n_flags & 0xff); 466 return idx; 467 /* Legacy rate format, search for match in table */ 468 } else { 469 if (band == IEEE80211_BAND_5GHZ) 470 band_offset = IL_FIRST_OFDM_RATE; 471 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++) 472 if (il_rates[idx].plcp == (rate_n_flags & 0xFF)) 473 return idx - band_offset; 474 } 475 476 return -1; 477} 478 479static int 480il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp) 481{ 482 /* data from PHY/DSP regarding signal strength, etc., 483 * contents are always there, not configurable by host. */ 484 struct il4965_rx_non_cfg_phy *ncphy = 485 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 486 u32 agc = 487 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >> 488 IL49_AGC_DB_POS; 489 490 u32 valid_antennae = 491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK) 492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET; 493 u8 max_rssi = 0; 494 u32 i; 495 496 /* Find max rssi among 3 possible receivers. 497 * These values are measured by the digital signal processor (DSP). 498 * They should stay fairly constant even as the signal strength varies, 499 * if the radio's automatic gain control (AGC) is working right. 500 * AGC value (see below) will provide the "interesting" info. */ 501 for (i = 0; i < 3; i++) 502 if (valid_antennae & (1 << i)) 503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); 504 505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", 506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], 507 max_rssi, agc); 508 509 /* dBm = max_rssi dB - agc dB - constant. 510 * Higher AGC (higher radio gain) means lower signal. */ 511 return max_rssi - agc - IL4965_RSSI_OFFSET; 512} 513 514static u32 515il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in) 516{ 517 u32 decrypt_out = 0; 518 519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == 520 RX_RES_STATUS_STATION_FOUND) 521 decrypt_out |= 522 (RX_RES_STATUS_STATION_FOUND | 523 RX_RES_STATUS_NO_STATION_INFO_MISMATCH); 524 525 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); 526 527 /* packet was not encrypted */ 528 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 529 RX_RES_STATUS_SEC_TYPE_NONE) 530 return decrypt_out; 531 532 /* packet was encrypted with unknown alg */ 533 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 534 RX_RES_STATUS_SEC_TYPE_ERR) 535 return decrypt_out; 536 537 /* decryption was not done in HW */ 538 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != 539 RX_MPDU_RES_STATUS_DEC_DONE_MSK) 540 return decrypt_out; 541 542 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { 543 544 case RX_RES_STATUS_SEC_TYPE_CCMP: 545 /* alg is CCM: check MIC only */ 546 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) 547 /* Bad MIC */ 548 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 549 else 550 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 551 552 break; 553 554 case RX_RES_STATUS_SEC_TYPE_TKIP: 555 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { 556 /* Bad TTAK */ 557 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; 558 break; 559 } 560 /* fall through if TTAK OK */ 561 default: 562 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) 563 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 564 else 565 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 566 break; 567 } 568 569 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out); 570 571 return decrypt_out; 572} 573 574static void 575il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr, 576 u16 len, u32 ampdu_status, struct il_rx_buf *rxb, 577 struct ieee80211_rx_status *stats) 578{ 579 struct sk_buff *skb; 580 __le16 fc = hdr->frame_control; 581 582 /* We only process data packets if the interface is open */ 583 if (unlikely(!il->is_open)) { 584 D_DROP("Dropping packet while interface is not open.\n"); 585 return; 586 } 587 588 /* In case of HW accelerated crypto and bad decryption, drop */ 589 if (!il->cfg->mod_params->sw_crypto && 590 il_set_decrypted_flag(il, hdr, ampdu_status, stats)) 591 return; 592 593 skb = dev_alloc_skb(128); 594 if (!skb) { 595 IL_ERR("dev_alloc_skb failed\n"); 596 return; 597 } 598 599 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len); 600 601 il_update_stats(il, false, fc, len); 602 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); 603 604 ieee80211_rx(il->hw, skb); 605 il->alloc_rxb_page--; 606 rxb->page = NULL; 607} 608 609/* Called for N_RX (legacy ABG frames), or 610 * N_RX_MPDU (HT high-throughput N frames). */ 611void 612il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb) 613{ 614 struct ieee80211_hdr *header; 615 struct ieee80211_rx_status rx_status; 616 struct il_rx_pkt *pkt = rxb_addr(rxb); 617 struct il_rx_phy_res *phy_res; 618 __le32 rx_pkt_status; 619 struct il_rx_mpdu_res_start *amsdu; 620 u32 len; 621 u32 ampdu_status; 622 u32 rate_n_flags; 623 624 /** 625 * N_RX and N_RX_MPDU are handled differently. 626 * N_RX: physical layer info is in this buffer 627 * N_RX_MPDU: physical layer info was sent in separate 628 * command and cached in il->last_phy_res 629 * 630 * Here we set up local variables depending on which command is 631 * received. 632 */ 633 if (pkt->hdr.cmd == N_RX) { 634 phy_res = (struct il_rx_phy_res *)pkt->u.raw; 635 header = 636 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) + 637 phy_res->cfg_phy_cnt); 638 639 len = le16_to_cpu(phy_res->byte_count); 640 rx_pkt_status = 641 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) + 642 phy_res->cfg_phy_cnt + len); 643 ampdu_status = le32_to_cpu(rx_pkt_status); 644 } else { 645 if (!il->_4965.last_phy_res_valid) { 646 IL_ERR("MPDU frame without cached PHY data\n"); 647 return; 648 } 649 phy_res = &il->_4965.last_phy_res; 650 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw; 651 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); 652 len = le16_to_cpu(amsdu->byte_count); 653 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len); 654 ampdu_status = 655 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status)); 656 } 657 658 if ((unlikely(phy_res->cfg_phy_cnt > 20))) { 659 D_DROP("dsp size out of range [0,20]: %d/n", 660 phy_res->cfg_phy_cnt); 661 return; 662 } 663 664 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || 665 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { 666 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status)); 667 return; 668 } 669 670 /* This will be used in several places later */ 671 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); 672 673 /* rx_status carries information about the packet to mac80211 */ 674 rx_status.mactime = le64_to_cpu(phy_res->timestamp); 675 rx_status.band = 676 (phy_res-> 677 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ : 678 IEEE80211_BAND_5GHZ; 679 rx_status.freq = 680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel), 681 rx_status.band); 682 rx_status.rate_idx = 683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band); 684 rx_status.flag = 0; 685 686 /* TSF isn't reliable. In order to allow smooth user experience, 687 * this W/A doesn't propagate it to the mac80211 */ 688 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU; */ 689 690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); 691 692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */ 693 rx_status.signal = il4965_calc_rssi(il, phy_res); 694 695 il_dbg_log_rx_data_frame(il, len, header); 696 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal, 697 (unsigned long long)rx_status.mactime); 698 699 /* 700 * "antenna number" 701 * 702 * It seems that the antenna field in the phy flags value 703 * is actually a bit field. This is undefined by radiotap, 704 * it wants an actual antenna number but I always get "7" 705 * for most legacy frames I receive indicating that the 706 * same frame was received on all three RX chains. 707 * 708 * I think this field should be removed in favor of a 709 * new 802.11n radiotap field "RX chains" that is defined 710 * as a bitmask. 711 */ 712 rx_status.antenna = 713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 714 RX_RES_PHY_FLAGS_ANTENNA_POS; 715 716 /* set the preamble flag if appropriate */ 717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) 718 rx_status.flag |= RX_FLAG_SHORTPRE; 719 720 /* Set up the HT phy flags */ 721 if (rate_n_flags & RATE_MCS_HT_MSK) 722 rx_status.flag |= RX_FLAG_HT; 723 if (rate_n_flags & RATE_MCS_HT40_MSK) 724 rx_status.flag |= RX_FLAG_40MHZ; 725 if (rate_n_flags & RATE_MCS_SGI_MSK) 726 rx_status.flag |= RX_FLAG_SHORT_GI; 727 728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb, 729 &rx_status); 730} 731 732/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY). 733 * This will be used later in il_hdl_rx() for N_RX_MPDU. */ 734void 735il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb) 736{ 737 struct il_rx_pkt *pkt = rxb_addr(rxb); 738 il->_4965.last_phy_res_valid = true; 739 memcpy(&il->_4965.last_phy_res, pkt->u.raw, 740 sizeof(struct il_rx_phy_res)); 741} 742 743static int 744il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif, 745 enum ieee80211_band band, u8 is_active, 746 u8 n_probes, struct il_scan_channel *scan_ch) 747{ 748 struct ieee80211_channel *chan; 749 const struct ieee80211_supported_band *sband; 750 const struct il_channel_info *ch_info; 751 u16 passive_dwell = 0; 752 u16 active_dwell = 0; 753 int added, i; 754 u16 channel; 755 756 sband = il_get_hw_mode(il, band); 757 if (!sband) 758 return 0; 759 760 active_dwell = il_get_active_dwell_time(il, band, n_probes); 761 passive_dwell = il_get_passive_dwell_time(il, band, vif); 762 763 if (passive_dwell <= active_dwell) 764 passive_dwell = active_dwell + 1; 765 766 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) { 767 chan = il->scan_request->channels[i]; 768 769 if (chan->band != band) 770 continue; 771 772 channel = chan->hw_value; 773 scan_ch->channel = cpu_to_le16(channel); 774 775 ch_info = il_get_channel_info(il, band, channel); 776 if (!il_is_channel_valid(ch_info)) { 777 D_SCAN("Channel %d is INVALID for this band.\n", 778 channel); 779 continue; 780 } 781 782 if (!is_active || il_is_channel_passive(ch_info) || 783 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) 784 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE; 785 else 786 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE; 787 788 if (n_probes) 789 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes); 790 791 scan_ch->active_dwell = cpu_to_le16(active_dwell); 792 scan_ch->passive_dwell = cpu_to_le16(passive_dwell); 793 794 /* Set txpower levels to defaults */ 795 scan_ch->dsp_atten = 110; 796 797 /* NOTE: if we were doing 6Mb OFDM for scans we'd use 798 * power level: 799 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3; 800 */ 801 if (band == IEEE80211_BAND_5GHZ) 802 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; 803 else 804 scan_ch->tx_gain = ((1 << 5) | (5 << 3)); 805 806 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel, 807 le32_to_cpu(scan_ch->type), 808 (scan_ch-> 809 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE", 810 (scan_ch-> 811 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell : 812 passive_dwell); 813 814 scan_ch++; 815 added++; 816 } 817 818 D_SCAN("total channels to scan %d\n", added); 819 return added; 820} 821 822static void 823il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid) 824{ 825 int i; 826 u8 ind = *ant; 827 828 for (i = 0; i < RATE_ANT_NUM - 1; i++) { 829 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; 830 if (valid & BIT(ind)) { 831 *ant = ind; 832 return; 833 } 834 } 835} 836 837int 838il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif) 839{ 840 struct il_host_cmd cmd = { 841 .id = C_SCAN, 842 .len = sizeof(struct il_scan_cmd), 843 .flags = CMD_SIZE_HUGE, 844 }; 845 struct il_scan_cmd *scan; 846 struct il_rxon_context *ctx = &il->ctx; 847 u32 rate_flags = 0; 848 u16 cmd_len; 849 u16 rx_chain = 0; 850 enum ieee80211_band band; 851 u8 n_probes = 0; 852 u8 rx_ant = il->hw_params.valid_rx_ant; 853 u8 rate; 854 bool is_active = false; 855 int chan_mod; 856 u8 active_chains; 857 u8 scan_tx_antennas = il->hw_params.valid_tx_ant; 858 int ret; 859 860 lockdep_assert_held(&il->mutex); 861 862 ctx = il_rxon_ctx_from_vif(vif); 863 864 if (!il->scan_cmd) { 865 il->scan_cmd = 866 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE, 867 GFP_KERNEL); 868 if (!il->scan_cmd) { 869 D_SCAN("fail to allocate memory for scan\n"); 870 return -ENOMEM; 871 } 872 } 873 scan = il->scan_cmd; 874 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE); 875 876 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH; 877 scan->quiet_time = IL_ACTIVE_QUIET_TIME; 878 879 if (il_is_any_associated(il)) { 880 u16 interval; 881 u32 extra; 882 u32 suspend_time = 100; 883 u32 scan_suspend_time = 100; 884 885 D_INFO("Scanning while associated...\n"); 886 interval = vif->bss_conf.beacon_int; 887 888 scan->suspend_time = 0; 889 scan->max_out_time = cpu_to_le32(200 * 1024); 890 if (!interval) 891 interval = suspend_time; 892 893 extra = (suspend_time / interval) << 22; 894 scan_suspend_time = 895 (extra | ((suspend_time % interval) * 1024)); 896 scan->suspend_time = cpu_to_le32(scan_suspend_time); 897 D_SCAN("suspend_time 0x%X beacon interval %d\n", 898 scan_suspend_time, interval); 899 } 900 901 if (il->scan_request->n_ssids) { 902 int i, p = 0; 903 D_SCAN("Kicking off active scan\n"); 904 for (i = 0; i < il->scan_request->n_ssids; i++) { 905 /* always does wildcard anyway */ 906 if (!il->scan_request->ssids[i].ssid_len) 907 continue; 908 scan->direct_scan[p].id = WLAN_EID_SSID; 909 scan->direct_scan[p].len = 910 il->scan_request->ssids[i].ssid_len; 911 memcpy(scan->direct_scan[p].ssid, 912 il->scan_request->ssids[i].ssid, 913 il->scan_request->ssids[i].ssid_len); 914 n_probes++; 915 p++; 916 } 917 is_active = true; 918 } else 919 D_SCAN("Start passive scan.\n"); 920 921 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; 922 scan->tx_cmd.sta_id = ctx->bcast_sta_id; 923 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 924 925 switch (il->scan_band) { 926 case IEEE80211_BAND_2GHZ: 927 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; 928 chan_mod = 929 le32_to_cpu(il->ctx.active. 930 flags & RXON_FLG_CHANNEL_MODE_MSK) >> 931 RXON_FLG_CHANNEL_MODE_POS; 932 if (chan_mod == CHANNEL_MODE_PURE_40) { 933 rate = RATE_6M_PLCP; 934 } else { 935 rate = RATE_1M_PLCP; 936 rate_flags = RATE_MCS_CCK_MSK; 937 } 938 break; 939 case IEEE80211_BAND_5GHZ: 940 rate = RATE_6M_PLCP; 941 break; 942 default: 943 IL_WARN("Invalid scan band\n"); 944 return -EIO; 945 } 946 947 /* 948 * If active scanning is requested but a certain channel is 949 * marked passive, we can do active scanning if we detect 950 * transmissions. 951 * 952 * There is an issue with some firmware versions that triggers 953 * a sysassert on a "good CRC threshold" of zero (== disabled), 954 * on a radar channel even though this means that we should NOT 955 * send probes. 956 * 957 * The "good CRC threshold" is the number of frames that we 958 * need to receive during our dwell time on a channel before 959 * sending out probes -- setting this to a huge value will 960 * mean we never reach it, but at the same time work around 961 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER 962 * here instead of IL_GOOD_CRC_TH_DISABLED. 963 */ 964 scan->good_CRC_th = 965 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER; 966 967 band = il->scan_band; 968 969 if (il->cfg->scan_rx_antennas[band]) 970 rx_ant = il->cfg->scan_rx_antennas[band]; 971 972 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas); 973 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS; 974 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags); 975 976 /* In power save mode use one chain, otherwise use all chains */ 977 if (test_bit(S_POWER_PMI, &il->status)) { 978 /* rx_ant has been set to all valid chains previously */ 979 active_chains = 980 rx_ant & ((u8) (il->chain_noise_data.active_chains)); 981 if (!active_chains) 982 active_chains = rx_ant; 983 984 D_SCAN("chain_noise_data.active_chains: %u\n", 985 il->chain_noise_data.active_chains); 986 987 rx_ant = il4965_first_antenna(active_chains); 988 } 989 990 /* MIMO is not used here, but value is required */ 991 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS; 992 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; 993 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS; 994 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; 995 scan->rx_chain = cpu_to_le16(rx_chain); 996 997 cmd_len = 998 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data, 999 vif->addr, il->scan_request->ie, 1000 il->scan_request->ie_len, 1001 IL_MAX_SCAN_SIZE - sizeof(*scan)); 1002 scan->tx_cmd.len = cpu_to_le16(cmd_len); 1003 1004 scan->filter_flags |= 1005 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK); 1006 1007 scan->channel_count = 1008 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes, 1009 (void *)&scan->data[cmd_len]); 1010 if (scan->channel_count == 0) { 1011 D_SCAN("channel count %d\n", scan->channel_count); 1012 return -EIO; 1013 } 1014 1015 cmd.len += 1016 le16_to_cpu(scan->tx_cmd.len) + 1017 scan->channel_count * sizeof(struct il_scan_channel); 1018 cmd.data = scan; 1019 scan->len = cpu_to_le16(cmd.len); 1020 1021 set_bit(S_SCAN_HW, &il->status); 1022 1023 ret = il_send_cmd_sync(il, &cmd); 1024 if (ret) 1025 clear_bit(S_SCAN_HW, &il->status); 1026 1027 return ret; 1028} 1029 1030int 1031il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, 1032 bool add) 1033{ 1034 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 1035 1036 if (add) 1037 return il4965_add_bssid_station(il, vif_priv->ctx, 1038 vif->bss_conf.bssid, 1039 &vif_priv->ibss_bssid_sta_id); 1040 return il_remove_station(il, vif_priv->ibss_bssid_sta_id, 1041 vif->bss_conf.bssid); 1042} 1043 1044void 1045il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed) 1046{ 1047 lockdep_assert_held(&il->sta_lock); 1048 1049 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed) 1050 il->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1051 else { 1052 D_TX("free more than tfds_in_queue (%u:%d)\n", 1053 il->stations[sta_id].tid[tid].tfds_in_queue, freed); 1054 il->stations[sta_id].tid[tid].tfds_in_queue = 0; 1055 } 1056} 1057 1058#define IL_TX_QUEUE_MSK 0xfffff 1059 1060static bool 1061il4965_is_single_rx_stream(struct il_priv *il) 1062{ 1063 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC || 1064 il->current_ht_config.single_chain_sufficient; 1065} 1066 1067#define IL_NUM_RX_CHAINS_MULTIPLE 3 1068#define IL_NUM_RX_CHAINS_SINGLE 2 1069#define IL_NUM_IDLE_CHAINS_DUAL 2 1070#define IL_NUM_IDLE_CHAINS_SINGLE 1 1071 1072/* 1073 * Determine how many receiver/antenna chains to use. 1074 * 1075 * More provides better reception via diversity. Fewer saves power 1076 * at the expense of throughput, but only when not in powersave to 1077 * start with. 1078 * 1079 * MIMO (dual stream) requires at least 2, but works better with 3. 1080 * This does not determine *which* chains to use, just how many. 1081 */ 1082static int 1083il4965_get_active_rx_chain_count(struct il_priv *il) 1084{ 1085 /* # of Rx chains to use when expecting MIMO. */ 1086 if (il4965_is_single_rx_stream(il)) 1087 return IL_NUM_RX_CHAINS_SINGLE; 1088 else 1089 return IL_NUM_RX_CHAINS_MULTIPLE; 1090} 1091 1092/* 1093 * When we are in power saving mode, unless device support spatial 1094 * multiplexing power save, use the active count for rx chain count. 1095 */ 1096static int 1097il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt) 1098{ 1099 /* # Rx chains when idling, depending on SMPS mode */ 1100 switch (il->current_ht_config.smps) { 1101 case IEEE80211_SMPS_STATIC: 1102 case IEEE80211_SMPS_DYNAMIC: 1103 return IL_NUM_IDLE_CHAINS_SINGLE; 1104 case IEEE80211_SMPS_OFF: 1105 return active_cnt; 1106 default: 1107 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps); 1108 return active_cnt; 1109 } 1110} 1111 1112/* up to 4 chains */ 1113static u8 1114il4965_count_chain_bitmap(u32 chain_bitmap) 1115{ 1116 u8 res; 1117 res = (chain_bitmap & BIT(0)) >> 0; 1118 res += (chain_bitmap & BIT(1)) >> 1; 1119 res += (chain_bitmap & BIT(2)) >> 2; 1120 res += (chain_bitmap & BIT(3)) >> 3; 1121 return res; 1122} 1123 1124/** 1125 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image 1126 * 1127 * Selects how many and which Rx receivers/antennas/chains to use. 1128 * This should not be used for scan command ... it puts data in wrong place. 1129 */ 1130void 1131il4965_set_rxon_chain(struct il_priv *il, struct il_rxon_context *ctx) 1132{ 1133 bool is_single = il4965_is_single_rx_stream(il); 1134 bool is_cam = !test_bit(S_POWER_PMI, &il->status); 1135 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt; 1136 u32 active_chains; 1137 u16 rx_chain; 1138 1139 /* Tell uCode which antennas are actually connected. 1140 * Before first association, we assume all antennas are connected. 1141 * Just after first association, il4965_chain_noise_calibration() 1142 * checks which antennas actually *are* connected. */ 1143 if (il->chain_noise_data.active_chains) 1144 active_chains = il->chain_noise_data.active_chains; 1145 else 1146 active_chains = il->hw_params.valid_rx_ant; 1147 1148 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS; 1149 1150 /* How many receivers should we use? */ 1151 active_rx_cnt = il4965_get_active_rx_chain_count(il); 1152 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt); 1153 1154 /* correct rx chain count according hw settings 1155 * and chain noise calibration 1156 */ 1157 valid_rx_cnt = il4965_count_chain_bitmap(active_chains); 1158 if (valid_rx_cnt < active_rx_cnt) 1159 active_rx_cnt = valid_rx_cnt; 1160 1161 if (valid_rx_cnt < idle_rx_cnt) 1162 idle_rx_cnt = valid_rx_cnt; 1163 1164 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS; 1165 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS; 1166 1167 ctx->staging.rx_chain = cpu_to_le16(rx_chain); 1168 1169 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam) 1170 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; 1171 else 1172 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; 1173 1174 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", ctx->staging.rx_chain, 1175 active_rx_cnt, idle_rx_cnt); 1176 1177 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || 1178 active_rx_cnt < idle_rx_cnt); 1179} 1180 1181static const char * 1182il4965_get_fh_string(int cmd) 1183{ 1184 switch (cmd) { 1185 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG); 1186 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG); 1187 IL_CMD(FH49_RSCSR_CHNL0_WPTR); 1188 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG); 1189 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG); 1190 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG); 1191 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); 1192 IL_CMD(FH49_TSSR_TX_STATUS_REG); 1193 IL_CMD(FH49_TSSR_TX_ERROR_REG); 1194 default: 1195 return "UNKNOWN"; 1196 } 1197} 1198 1199int 1200il4965_dump_fh(struct il_priv *il, char **buf, bool display) 1201{ 1202 int i; 1203#ifdef CONFIG_IWLEGACY_DEBUG 1204 int pos = 0; 1205 size_t bufsz = 0; 1206#endif 1207 static const u32 fh_tbl[] = { 1208 FH49_RSCSR_CHNL0_STTS_WPTR_REG, 1209 FH49_RSCSR_CHNL0_RBDCB_BASE_REG, 1210 FH49_RSCSR_CHNL0_WPTR, 1211 FH49_MEM_RCSR_CHNL0_CONFIG_REG, 1212 FH49_MEM_RSSR_SHARED_CTRL_REG, 1213 FH49_MEM_RSSR_RX_STATUS_REG, 1214 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, 1215 FH49_TSSR_TX_STATUS_REG, 1216 FH49_TSSR_TX_ERROR_REG 1217 }; 1218#ifdef CONFIG_IWLEGACY_DEBUG 1219 if (display) { 1220 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; 1221 *buf = kmalloc(bufsz, GFP_KERNEL); 1222 if (!*buf) 1223 return -ENOMEM; 1224 pos += 1225 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n"); 1226 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1227 pos += 1228 scnprintf(*buf + pos, bufsz - pos, 1229 " %34s: 0X%08x\n", 1230 il4965_get_fh_string(fh_tbl[i]), 1231 il_rd(il, fh_tbl[i])); 1232 } 1233 return pos; 1234 } 1235#endif 1236 IL_ERR("FH register values:\n"); 1237 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1238 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]), 1239 il_rd(il, fh_tbl[i])); 1240 } 1241 return 0; 1242} 1243 1244void 1245il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb) 1246{ 1247 struct il_rx_pkt *pkt = rxb_addr(rxb); 1248 struct il_missed_beacon_notif *missed_beacon; 1249 1250 missed_beacon = &pkt->u.missed_beacon; 1251 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) > 1252 il->missed_beacon_threshold) { 1253 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n", 1254 le32_to_cpu(missed_beacon->consecutive_missed_beacons), 1255 le32_to_cpu(missed_beacon->total_missed_becons), 1256 le32_to_cpu(missed_beacon->num_recvd_beacons), 1257 le32_to_cpu(missed_beacon->num_expected_beacons)); 1258 if (!test_bit(S_SCANNING, &il->status)) 1259 il4965_init_sensitivity(il); 1260 } 1261} 1262 1263/* Calculate noise level, based on measurements during network silence just 1264 * before arriving beacon. This measurement can be done only if we know 1265 * exactly when to expect beacons, therefore only when we're associated. */ 1266static void 1267il4965_rx_calc_noise(struct il_priv *il) 1268{ 1269 struct stats_rx_non_phy *rx_info; 1270 int num_active_rx = 0; 1271 int total_silence = 0; 1272 int bcn_silence_a, bcn_silence_b, bcn_silence_c; 1273 int last_rx_noise; 1274 1275 rx_info = &(il->_4965.stats.rx.general); 1276 bcn_silence_a = 1277 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; 1278 bcn_silence_b = 1279 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; 1280 bcn_silence_c = 1281 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; 1282 1283 if (bcn_silence_a) { 1284 total_silence += bcn_silence_a; 1285 num_active_rx++; 1286 } 1287 if (bcn_silence_b) { 1288 total_silence += bcn_silence_b; 1289 num_active_rx++; 1290 } 1291 if (bcn_silence_c) { 1292 total_silence += bcn_silence_c; 1293 num_active_rx++; 1294 } 1295 1296 /* Average among active antennas */ 1297 if (num_active_rx) 1298 last_rx_noise = (total_silence / num_active_rx) - 107; 1299 else 1300 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE; 1301 1302 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a, 1303 bcn_silence_b, bcn_silence_c, last_rx_noise); 1304} 1305 1306#ifdef CONFIG_IWLEGACY_DEBUGFS 1307/* 1308 * based on the assumption of all stats counter are in DWORD 1309 * FIXME: This function is for debugging, do not deal with 1310 * the case of counters roll-over. 1311 */ 1312static void 1313il4965_accumulative_stats(struct il_priv *il, __le32 * stats) 1314{ 1315 int i, size; 1316 __le32 *prev_stats; 1317 u32 *accum_stats; 1318 u32 *delta, *max_delta; 1319 struct stats_general_common *general, *accum_general; 1320 struct stats_tx *tx, *accum_tx; 1321 1322 prev_stats = (__le32 *) &il->_4965.stats; 1323 accum_stats = (u32 *) &il->_4965.accum_stats; 1324 size = sizeof(struct il_notif_stats); 1325 general = &il->_4965.stats.general.common; 1326 accum_general = &il->_4965.accum_stats.general.common; 1327 tx = &il->_4965.stats.tx; 1328 accum_tx = &il->_4965.accum_stats.tx; 1329 delta = (u32 *) &il->_4965.delta_stats; 1330 max_delta = (u32 *) &il->_4965.max_delta; 1331 1332 for (i = sizeof(__le32); i < size; 1333 i += 1334 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++, 1335 accum_stats++) { 1336 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { 1337 *delta = 1338 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats)); 1339 *accum_stats += *delta; 1340 if (*delta > *max_delta) 1341 *max_delta = *delta; 1342 } 1343 } 1344 1345 /* reset accumulative stats for "no-counter" type stats */ 1346 accum_general->temperature = general->temperature; 1347 accum_general->ttl_timestamp = general->ttl_timestamp; 1348} 1349#endif 1350 1351#define REG_RECALIB_PERIOD (60) 1352 1353void 1354il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb) 1355{ 1356 int change; 1357 struct il_rx_pkt *pkt = rxb_addr(rxb); 1358 1359 D_RX("Statistics notification received (%d vs %d).\n", 1360 (int)sizeof(struct il_notif_stats), 1361 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK); 1362 1363 change = 1364 ((il->_4965.stats.general.common.temperature != 1365 pkt->u.stats.general.common.temperature) || 1366 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) != 1367 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK))); 1368#ifdef CONFIG_IWLEGACY_DEBUGFS 1369 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats); 1370#endif 1371 1372 /* TODO: reading some of stats is unneeded */ 1373 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats)); 1374 1375 set_bit(S_STATS, &il->status); 1376 1377 /* Reschedule the stats timer to occur in 1378 * REG_RECALIB_PERIOD seconds to ensure we get a 1379 * thermal update even if the uCode doesn't give 1380 * us one */ 1381 mod_timer(&il->stats_periodic, 1382 jiffies + msecs_to_jiffies(REG_RECALIB_PERIOD * 1000)); 1383 1384 if (unlikely(!test_bit(S_SCANNING, &il->status)) && 1385 (pkt->hdr.cmd == N_STATS)) { 1386 il4965_rx_calc_noise(il); 1387 queue_work(il->workqueue, &il->run_time_calib_work); 1388 } 1389 if (il->cfg->ops->lib->temp_ops.temperature && change) 1390 il->cfg->ops->lib->temp_ops.temperature(il); 1391} 1392 1393void 1394il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb) 1395{ 1396 struct il_rx_pkt *pkt = rxb_addr(rxb); 1397 1398 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) { 1399#ifdef CONFIG_IWLEGACY_DEBUGFS 1400 memset(&il->_4965.accum_stats, 0, 1401 sizeof(struct il_notif_stats)); 1402 memset(&il->_4965.delta_stats, 0, 1403 sizeof(struct il_notif_stats)); 1404 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats)); 1405#endif 1406 D_RX("Statistics have been cleared\n"); 1407 } 1408 il4965_hdl_stats(il, rxb); 1409} 1410 1411 1412/* 1413 * mac80211 queues, ACs, hardware queues, FIFOs. 1414 * 1415 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues 1416 * 1417 * Mac80211 uses the following numbers, which we get as from it 1418 * by way of skb_get_queue_mapping(skb): 1419 * 1420 * VO 0 1421 * VI 1 1422 * BE 2 1423 * BK 3 1424 * 1425 * 1426 * Regular (not A-MPDU) frames are put into hardware queues corresponding 1427 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their 1428 * own queue per aggregation session (RA/TID combination), such queues are 1429 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In 1430 * order to map frames to the right queue, we also need an AC->hw queue 1431 * mapping. This is implemented here. 1432 * 1433 * Due to the way hw queues are set up (by the hw specific modules like 1434 * 4965.c), the AC->hw queue mapping is the identity 1435 * mapping. 1436 */ 1437 1438static const u8 tid_to_ac[] = { 1439 IEEE80211_AC_BE, 1440 IEEE80211_AC_BK, 1441 IEEE80211_AC_BK, 1442 IEEE80211_AC_BE, 1443 IEEE80211_AC_VI, 1444 IEEE80211_AC_VI, 1445 IEEE80211_AC_VO, 1446 IEEE80211_AC_VO 1447}; 1448 1449static inline int 1450il4965_get_ac_from_tid(u16 tid) 1451{ 1452 if (likely(tid < ARRAY_SIZE(tid_to_ac))) 1453 return tid_to_ac[tid]; 1454 1455 /* no support for TIDs 8-15 yet */ 1456 return -EINVAL; 1457} 1458 1459static inline int 1460il4965_get_fifo_from_tid(struct il_rxon_context *ctx, u16 tid) 1461{ 1462 if (likely(tid < ARRAY_SIZE(tid_to_ac))) 1463 return ctx->ac_to_fifo[tid_to_ac[tid]]; 1464 1465 /* no support for TIDs 8-15 yet */ 1466 return -EINVAL; 1467} 1468 1469/* 1470 * handle build C_TX command notification. 1471 */ 1472static void 1473il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb, 1474 struct il_tx_cmd *tx_cmd, 1475 struct ieee80211_tx_info *info, 1476 struct ieee80211_hdr *hdr, u8 std_id) 1477{ 1478 __le16 fc = hdr->frame_control; 1479 __le32 tx_flags = tx_cmd->tx_flags; 1480 1481 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 1482 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 1483 tx_flags |= TX_CMD_FLG_ACK_MSK; 1484 if (ieee80211_is_mgmt(fc)) 1485 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1486 if (ieee80211_is_probe_resp(fc) && 1487 !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) 1488 tx_flags |= TX_CMD_FLG_TSF_MSK; 1489 } else { 1490 tx_flags &= (~TX_CMD_FLG_ACK_MSK); 1491 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1492 } 1493 1494 if (ieee80211_is_back_req(fc)) 1495 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; 1496 1497 tx_cmd->sta_id = std_id; 1498 if (ieee80211_has_morefrags(fc)) 1499 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; 1500 1501 if (ieee80211_is_data_qos(fc)) { 1502 u8 *qc = ieee80211_get_qos_ctl(hdr); 1503 tx_cmd->tid_tspec = qc[0] & 0xf; 1504 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; 1505 } else { 1506 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1507 } 1508 1509 il_tx_cmd_protection(il, info, fc, &tx_flags); 1510 1511 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); 1512 if (ieee80211_is_mgmt(fc)) { 1513 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) 1514 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); 1515 else 1516 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); 1517 } else { 1518 tx_cmd->timeout.pm_frame_timeout = 0; 1519 } 1520 1521 tx_cmd->driver_txop = 0; 1522 tx_cmd->tx_flags = tx_flags; 1523 tx_cmd->next_frame_len = 0; 1524} 1525 1526static void 1527il4965_tx_cmd_build_rate(struct il_priv *il, struct il_tx_cmd *tx_cmd, 1528 struct ieee80211_tx_info *info, __le16 fc) 1529{ 1530 const u8 rts_retry_limit = 60; 1531 u32 rate_flags; 1532 int rate_idx; 1533 u8 data_retry_limit; 1534 u8 rate_plcp; 1535 1536 /* Set retry limit on DATA packets and Probe Responses */ 1537 if (ieee80211_is_probe_resp(fc)) 1538 data_retry_limit = 3; 1539 else 1540 data_retry_limit = IL4965_DEFAULT_TX_RETRY; 1541 tx_cmd->data_retry_limit = data_retry_limit; 1542 /* Set retry limit on RTS packets */ 1543 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit); 1544 1545 /* DATA packets will use the uCode station table for rate/antenna 1546 * selection */ 1547 if (ieee80211_is_data(fc)) { 1548 tx_cmd->initial_rate_idx = 0; 1549 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; 1550 return; 1551 } 1552 1553 /** 1554 * If the current TX rate stored in mac80211 has the MCS bit set, it's 1555 * not really a TX rate. Thus, we use the lowest supported rate for 1556 * this band. Also use the lowest supported rate if the stored rate 1557 * idx is invalid. 1558 */ 1559 rate_idx = info->control.rates[0].idx; 1560 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0 1561 || rate_idx > RATE_COUNT_LEGACY) 1562 rate_idx = 1563 rate_lowest_index(&il->bands[info->band], 1564 info->control.sta); 1565 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ 1566 if (info->band == IEEE80211_BAND_5GHZ) 1567 rate_idx += IL_FIRST_OFDM_RATE; 1568 /* Get PLCP rate for tx_cmd->rate_n_flags */ 1569 rate_plcp = il_rates[rate_idx].plcp; 1570 /* Zero out flags for this packet */ 1571 rate_flags = 0; 1572 1573 /* Set CCK flag as needed */ 1574 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE) 1575 rate_flags |= RATE_MCS_CCK_MSK; 1576 1577 /* Set up antennas */ 1578 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); 1579 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; 1580 1581 /* Set the rate in the TX cmd */ 1582 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags); 1583} 1584 1585static void 1586il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info, 1587 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag, 1588 int sta_id) 1589{ 1590 struct ieee80211_key_conf *keyconf = info->control.hw_key; 1591 1592 switch (keyconf->cipher) { 1593 case WLAN_CIPHER_SUITE_CCMP: 1594 tx_cmd->sec_ctl = TX_CMD_SEC_CCM; 1595 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); 1596 if (info->flags & IEEE80211_TX_CTL_AMPDU) 1597 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; 1598 D_TX("tx_cmd with AES hwcrypto\n"); 1599 break; 1600 1601 case WLAN_CIPHER_SUITE_TKIP: 1602 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; 1603 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key); 1604 D_TX("tx_cmd with tkip hwcrypto\n"); 1605 break; 1606 1607 case WLAN_CIPHER_SUITE_WEP104: 1608 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; 1609 /* fall through */ 1610 case WLAN_CIPHER_SUITE_WEP40: 1611 tx_cmd->sec_ctl |= 1612 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) << 1613 TX_CMD_SEC_SHIFT); 1614 1615 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); 1616 1617 D_TX("Configuring packet for WEP encryption " "with key %d\n", 1618 keyconf->keyidx); 1619 break; 1620 1621 default: 1622 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher); 1623 break; 1624 } 1625} 1626 1627/* 1628 * start C_TX command process 1629 */ 1630int 1631il4965_tx_skb(struct il_priv *il, struct sk_buff *skb) 1632{ 1633 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1634 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1635 struct ieee80211_sta *sta = info->control.sta; 1636 struct il_station_priv *sta_priv = NULL; 1637 struct il_tx_queue *txq; 1638 struct il_queue *q; 1639 struct il_device_cmd *out_cmd; 1640 struct il_cmd_meta *out_meta; 1641 struct il_tx_cmd *tx_cmd; 1642 struct il_rxon_context *ctx = &il->ctx; 1643 int txq_id; 1644 dma_addr_t phys_addr; 1645 dma_addr_t txcmd_phys; 1646 dma_addr_t scratch_phys; 1647 u16 len, firstlen, secondlen; 1648 u16 seq_number = 0; 1649 __le16 fc; 1650 u8 hdr_len; 1651 u8 sta_id; 1652 u8 wait_write_ptr = 0; 1653 u8 tid = 0; 1654 u8 *qc = NULL; 1655 unsigned long flags; 1656 bool is_agg = false; 1657 1658 if (info->control.vif) 1659 ctx = il_rxon_ctx_from_vif(info->control.vif); 1660 1661 spin_lock_irqsave(&il->lock, flags); 1662 if (il_is_rfkill(il)) { 1663 D_DROP("Dropping - RF KILL\n"); 1664 goto drop_unlock; 1665 } 1666 1667 fc = hdr->frame_control; 1668 1669#ifdef CONFIG_IWLEGACY_DEBUG 1670 if (ieee80211_is_auth(fc)) 1671 D_TX("Sending AUTH frame\n"); 1672 else if (ieee80211_is_assoc_req(fc)) 1673 D_TX("Sending ASSOC frame\n"); 1674 else if (ieee80211_is_reassoc_req(fc)) 1675 D_TX("Sending REASSOC frame\n"); 1676#endif 1677 1678 hdr_len = ieee80211_hdrlen(fc); 1679 1680 /* For management frames use broadcast id to do not break aggregation */ 1681 if (!ieee80211_is_data(fc)) 1682 sta_id = ctx->bcast_sta_id; 1683 else { 1684 /* Find idx into station table for destination station */ 1685 sta_id = il_sta_id_or_broadcast(il, ctx, info->control.sta); 1686 1687 if (sta_id == IL_INVALID_STATION) { 1688 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1); 1689 goto drop_unlock; 1690 } 1691 } 1692 1693 D_TX("station Id %d\n", sta_id); 1694 1695 if (sta) 1696 sta_priv = (void *)sta->drv_priv; 1697 1698 if (sta_priv && sta_priv->asleep && 1699 (info->flags & IEEE80211_TX_CTL_POLL_RESPONSE)) { 1700 /* 1701 * This sends an asynchronous command to the device, 1702 * but we can rely on it being processed before the 1703 * next frame is processed -- and the next frame to 1704 * this station is the one that will consume this 1705 * counter. 1706 * For now set the counter to just 1 since we do not 1707 * support uAPSD yet. 1708 */ 1709 il4965_sta_modify_sleep_tx_count(il, sta_id, 1); 1710 } 1711 1712 /* 1713 * Send this frame after DTIM -- there's a special queue 1714 * reserved for this for contexts that support AP mode. 1715 */ 1716 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { 1717 txq_id = ctx->mcast_queue; 1718 /* 1719 * The microcode will clear the more data 1720 * bit in the last frame it transmits. 1721 */ 1722 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); 1723 } else 1724 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)]; 1725 1726 /* irqs already disabled/saved above when locking il->lock */ 1727 spin_lock(&il->sta_lock); 1728 1729 if (ieee80211_is_data_qos(fc)) { 1730 qc = ieee80211_get_qos_ctl(hdr); 1731 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 1732 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) { 1733 spin_unlock(&il->sta_lock); 1734 goto drop_unlock; 1735 } 1736 seq_number = il->stations[sta_id].tid[tid].seq_number; 1737 seq_number &= IEEE80211_SCTL_SEQ; 1738 hdr->seq_ctrl = 1739 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG); 1740 hdr->seq_ctrl |= cpu_to_le16(seq_number); 1741 seq_number += 0x10; 1742 /* aggregation is on for this <sta,tid> */ 1743 if (info->flags & IEEE80211_TX_CTL_AMPDU && 1744 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) { 1745 txq_id = il->stations[sta_id].tid[tid].agg.txq_id; 1746 is_agg = true; 1747 } 1748 } 1749 1750 txq = &il->txq[txq_id]; 1751 q = &txq->q; 1752 1753 if (unlikely(il_queue_space(q) < q->high_mark)) { 1754 spin_unlock(&il->sta_lock); 1755 goto drop_unlock; 1756 } 1757 1758 if (ieee80211_is_data_qos(fc)) { 1759 il->stations[sta_id].tid[tid].tfds_in_queue++; 1760 if (!ieee80211_has_morefrags(fc)) 1761 il->stations[sta_id].tid[tid].seq_number = seq_number; 1762 } 1763 1764 spin_unlock(&il->sta_lock); 1765 1766 /* Set up driver data for this TFD */ 1767 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info)); 1768 txq->txb[q->write_ptr].skb = skb; 1769 txq->txb[q->write_ptr].ctx = ctx; 1770 1771 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 1772 out_cmd = txq->cmd[q->write_ptr]; 1773 out_meta = &txq->meta[q->write_ptr]; 1774 tx_cmd = &out_cmd->cmd.tx; 1775 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); 1776 memset(tx_cmd, 0, sizeof(struct il_tx_cmd)); 1777 1778 /* 1779 * Set up the Tx-command (not MAC!) header. 1780 * Store the chosen Tx queue and TFD idx within the sequence field; 1781 * after Tx, uCode's Tx response will return this value so driver can 1782 * locate the frame within the tx queue and do post-tx processing. 1783 */ 1784 out_cmd->hdr.cmd = C_TX; 1785 out_cmd->hdr.sequence = 1786 cpu_to_le16((u16) 1787 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr))); 1788 1789 /* Copy MAC header from skb into command buffer */ 1790 memcpy(tx_cmd->hdr, hdr, hdr_len); 1791 1792 /* Total # bytes to be transmitted */ 1793 len = (u16) skb->len; 1794 tx_cmd->len = cpu_to_le16(len); 1795 1796 if (info->control.hw_key) 1797 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id); 1798 1799 /* TODO need this for burst mode later on */ 1800 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id); 1801 il_dbg_log_tx_data_frame(il, len, hdr); 1802 1803 il4965_tx_cmd_build_rate(il, tx_cmd, info, fc); 1804 1805 il_update_stats(il, true, fc, len); 1806 /* 1807 * Use the first empty entry in this queue's command buffer array 1808 * to contain the Tx command and MAC header concatenated together 1809 * (payload data will be in another buffer). 1810 * Size of this varies, due to varying MAC header length. 1811 * If end is not dword aligned, we'll have 2 extra bytes at the end 1812 * of the MAC header (device reads on dword boundaries). 1813 * We'll tell device about this padding later. 1814 */ 1815 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len; 1816 firstlen = (len + 3) & ~3; 1817 1818 /* Tell NIC about any 2-byte padding after MAC header */ 1819 if (firstlen != len) 1820 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 1821 1822 /* Physical address of this Tx command's header (not MAC header!), 1823 * within command buffer array. */ 1824 txcmd_phys = 1825 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen, 1826 PCI_DMA_BIDIRECTIONAL); 1827 dma_unmap_addr_set(out_meta, mapping, txcmd_phys); 1828 dma_unmap_len_set(out_meta, len, firstlen); 1829 /* Add buffer containing Tx command and MAC(!) header to TFD's 1830 * first entry */ 1831 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1832 1, 0); 1833 1834 if (!ieee80211_has_morefrags(hdr->frame_control)) { 1835 txq->need_update = 1; 1836 } else { 1837 wait_write_ptr = 1; 1838 txq->need_update = 0; 1839 } 1840 1841 /* Set up TFD's 2nd entry to point directly to remainder of skb, 1842 * if any (802.11 null frames have no payload). */ 1843 secondlen = skb->len - hdr_len; 1844 if (secondlen > 0) { 1845 phys_addr = 1846 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen, 1847 PCI_DMA_TODEVICE); 1848 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, 1849 secondlen, 0, 0); 1850 } 1851 1852 scratch_phys = 1853 txcmd_phys + sizeof(struct il_cmd_header) + 1854 offsetof(struct il_tx_cmd, scratch); 1855 1856 /* take back ownership of DMA buffer to enable update */ 1857 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen, 1858 PCI_DMA_BIDIRECTIONAL); 1859 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 1860 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys); 1861 1862 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence)); 1863 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); 1864 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd)); 1865 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len); 1866 1867 /* Set up entry for this TFD in Tx byte-count array */ 1868 if (info->flags & IEEE80211_TX_CTL_AMPDU) 1869 il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq, 1870 le16_to_cpu(tx_cmd-> 1871 len)); 1872 1873 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen, 1874 PCI_DMA_BIDIRECTIONAL); 1875 1876 /* Tell device the write idx *just past* this latest filled TFD */ 1877 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd); 1878 il_txq_update_write_ptr(il, txq); 1879 spin_unlock_irqrestore(&il->lock, flags); 1880 1881 /* 1882 * At this point the frame is "transmitted" successfully 1883 * and we will get a TX status notification eventually, 1884 * regardless of the value of ret. "ret" only indicates 1885 * whether or not we should update the write pointer. 1886 */ 1887 1888 /* 1889 * Avoid atomic ops if it isn't an associated client. 1890 * Also, if this is a packet for aggregation, don't 1891 * increase the counter because the ucode will stop 1892 * aggregation queues when their respective station 1893 * goes to sleep. 1894 */ 1895 if (sta_priv && sta_priv->client && !is_agg) 1896 atomic_inc(&sta_priv->pending_frames); 1897 1898 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) { 1899 if (wait_write_ptr) { 1900 spin_lock_irqsave(&il->lock, flags); 1901 txq->need_update = 1; 1902 il_txq_update_write_ptr(il, txq); 1903 spin_unlock_irqrestore(&il->lock, flags); 1904 } else { 1905 il_stop_queue(il, txq); 1906 } 1907 } 1908 1909 return 0; 1910 1911drop_unlock: 1912 spin_unlock_irqrestore(&il->lock, flags); 1913 return -1; 1914} 1915 1916static inline int 1917il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size) 1918{ 1919 ptr->addr = 1920 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL); 1921 if (!ptr->addr) 1922 return -ENOMEM; 1923 ptr->size = size; 1924 return 0; 1925} 1926 1927static inline void 1928il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr) 1929{ 1930 if (unlikely(!ptr->addr)) 1931 return; 1932 1933 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma); 1934 memset(ptr, 0, sizeof(*ptr)); 1935} 1936 1937/** 1938 * il4965_hw_txq_ctx_free - Free TXQ Context 1939 * 1940 * Destroy all TX DMA queues and structures 1941 */ 1942void 1943il4965_hw_txq_ctx_free(struct il_priv *il) 1944{ 1945 int txq_id; 1946 1947 /* Tx queues */ 1948 if (il->txq) { 1949 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 1950 if (txq_id == il->cmd_queue) 1951 il_cmd_queue_free(il); 1952 else 1953 il_tx_queue_free(il, txq_id); 1954 } 1955 il4965_free_dma_ptr(il, &il->kw); 1956 1957 il4965_free_dma_ptr(il, &il->scd_bc_tbls); 1958 1959 /* free tx queue structure */ 1960 il_txq_mem(il); 1961} 1962 1963/** 1964 * il4965_txq_ctx_alloc - allocate TX queue context 1965 * Allocate all Tx DMA structures and initialize them 1966 * 1967 * @param il 1968 * @return error code 1969 */ 1970int 1971il4965_txq_ctx_alloc(struct il_priv *il) 1972{ 1973 int ret; 1974 int txq_id, slots_num; 1975 unsigned long flags; 1976 1977 /* Free all tx/cmd queues and keep-warm buffer */ 1978 il4965_hw_txq_ctx_free(il); 1979 1980 ret = 1981 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls, 1982 il->hw_params.scd_bc_tbls_size); 1983 if (ret) { 1984 IL_ERR("Scheduler BC Table allocation failed\n"); 1985 goto error_bc_tbls; 1986 } 1987 /* Alloc keep-warm buffer */ 1988 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE); 1989 if (ret) { 1990 IL_ERR("Keep Warm allocation failed\n"); 1991 goto error_kw; 1992 } 1993 1994 /* allocate tx queue structure */ 1995 ret = il_alloc_txq_mem(il); 1996 if (ret) 1997 goto error; 1998 1999 spin_lock_irqsave(&il->lock, flags); 2000 2001 /* Turn off all Tx DMA fifos */ 2002 il4965_txq_set_sched(il, 0); 2003 2004 /* Tell NIC where to find the "keep warm" buffer */ 2005 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); 2006 2007 spin_unlock_irqrestore(&il->lock, flags); 2008 2009 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 2010 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 2011 slots_num = 2012 (txq_id == 2013 il->cmd_queue) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 2014 ret = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id); 2015 if (ret) { 2016 IL_ERR("Tx %d queue init failed\n", txq_id); 2017 goto error; 2018 } 2019 } 2020 2021 return ret; 2022 2023error: 2024 il4965_hw_txq_ctx_free(il); 2025 il4965_free_dma_ptr(il, &il->kw); 2026error_kw: 2027 il4965_free_dma_ptr(il, &il->scd_bc_tbls); 2028error_bc_tbls: 2029 return ret; 2030} 2031 2032void 2033il4965_txq_ctx_reset(struct il_priv *il) 2034{ 2035 int txq_id, slots_num; 2036 unsigned long flags; 2037 2038 spin_lock_irqsave(&il->lock, flags); 2039 2040 /* Turn off all Tx DMA fifos */ 2041 il4965_txq_set_sched(il, 0); 2042 2043 /* Tell NIC where to find the "keep warm" buffer */ 2044 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); 2045 2046 spin_unlock_irqrestore(&il->lock, flags); 2047 2048 /* Alloc and init all Tx queues, including the command queue (#4) */ 2049 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 2050 slots_num = 2051 txq_id == il->cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 2052 il_tx_queue_reset(il, &il->txq[txq_id], slots_num, txq_id); 2053 } 2054} 2055 2056/** 2057 * il4965_txq_ctx_stop - Stop all Tx DMA channels 2058 */ 2059void 2060il4965_txq_ctx_stop(struct il_priv *il) 2061{ 2062 int ch, txq_id; 2063 unsigned long flags; 2064 2065 /* Turn off all Tx DMA fifos */ 2066 spin_lock_irqsave(&il->lock, flags); 2067 2068 il4965_txq_set_sched(il, 0); 2069 2070 /* Stop each Tx DMA channel, and wait for it to be idle */ 2071 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { 2072 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 2073 if (il_poll_bit 2074 (il, FH49_TSSR_TX_STATUS_REG, 2075 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000)) 2076 IL_ERR("Failing on timeout while stopping" 2077 " DMA channel %d [0x%08x]", ch, 2078 il_rd(il, FH49_TSSR_TX_STATUS_REG)); 2079 } 2080 spin_unlock_irqrestore(&il->lock, flags); 2081 2082 if (!il->txq) 2083 return; 2084 2085 /* Unmap DMA from host system and free skb's */ 2086 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2087 if (txq_id == il->cmd_queue) 2088 il_cmd_queue_unmap(il); 2089 else 2090 il_tx_queue_unmap(il, txq_id); 2091} 2092 2093/* 2094 * Find first available (lowest unused) Tx Queue, mark it "active". 2095 * Called only when finding queue for aggregation. 2096 * Should never return anything < 7, because they should already 2097 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) 2098 */ 2099static int 2100il4965_txq_ctx_activate_free(struct il_priv *il) 2101{ 2102 int txq_id; 2103 2104 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2105 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk)) 2106 return txq_id; 2107 return -1; 2108} 2109 2110/** 2111 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration 2112 */ 2113static void 2114il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id) 2115{ 2116 /* Simply stop the queue, but don't change any configuration; 2117 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 2118 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), 2119 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 2120 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 2121} 2122 2123/** 2124 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue 2125 */ 2126static int 2127il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id) 2128{ 2129 u32 tbl_dw_addr; 2130 u32 tbl_dw; 2131 u16 scd_q2ratid; 2132 2133 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 2134 2135 tbl_dw_addr = 2136 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 2137 2138 tbl_dw = il_read_targ_mem(il, tbl_dw_addr); 2139 2140 if (txq_id & 0x1) 2141 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 2142 else 2143 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 2144 2145 il_write_targ_mem(il, tbl_dw_addr, tbl_dw); 2146 2147 return 0; 2148} 2149 2150/** 2151 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue 2152 * 2153 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE, 2154 * i.e. it must be one of the higher queues used for aggregation 2155 */ 2156static int 2157il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id, 2158 int tid, u16 ssn_idx) 2159{ 2160 unsigned long flags; 2161 u16 ra_tid; 2162 int ret; 2163 2164 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || 2165 (IL49_FIRST_AMPDU_QUEUE + 2166 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) { 2167 IL_WARN("queue number out of range: %d, must be %d to %d\n", 2168 txq_id, IL49_FIRST_AMPDU_QUEUE, 2169 IL49_FIRST_AMPDU_QUEUE + 2170 il->cfg->base_params->num_of_ampdu_queues - 1); 2171 return -EINVAL; 2172 } 2173 2174 ra_tid = BUILD_RAxTID(sta_id, tid); 2175 2176 /* Modify device's station table to Tx this TID */ 2177 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid); 2178 if (ret) 2179 return ret; 2180 2181 spin_lock_irqsave(&il->lock, flags); 2182 2183 /* Stop this Tx queue before configuring it */ 2184 il4965_tx_queue_stop_scheduler(il, txq_id); 2185 2186 /* Map receiver-address / traffic-ID to this queue */ 2187 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id); 2188 2189 /* Set this queue as a chain-building queue */ 2190 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 2191 2192 /* Place first TFD at idx corresponding to start sequence number. 2193 * Assumes that ssn_idx is valid (!= 0xFFF) */ 2194 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 2195 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 2196 il4965_set_wr_ptrs(il, txq_id, ssn_idx); 2197 2198 /* Set up Tx win size and frame limit for this queue */ 2199 il_write_targ_mem(il, 2200 il->scd_base_addr + 2201 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id), 2202 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) 2203 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 2204 2205 il_write_targ_mem(il, 2206 il->scd_base_addr + 2207 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 2208 (SCD_FRAME_LIMIT << 2209 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 2210 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 2211 2212 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 2213 2214 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 2215 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1); 2216 2217 spin_unlock_irqrestore(&il->lock, flags); 2218 2219 return 0; 2220} 2221 2222int 2223il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif, 2224 struct ieee80211_sta *sta, u16 tid, u16 * ssn) 2225{ 2226 int sta_id; 2227 int tx_fifo; 2228 int txq_id; 2229 int ret; 2230 unsigned long flags; 2231 struct il_tid_data *tid_data; 2232 2233 tx_fifo = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid); 2234 if (unlikely(tx_fifo < 0)) 2235 return tx_fifo; 2236 2237 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid); 2238 2239 sta_id = il_sta_id(sta); 2240 if (sta_id == IL_INVALID_STATION) { 2241 IL_ERR("Start AGG on invalid station\n"); 2242 return -ENXIO; 2243 } 2244 if (unlikely(tid >= MAX_TID_COUNT)) 2245 return -EINVAL; 2246 2247 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) { 2248 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n"); 2249 return -ENXIO; 2250 } 2251 2252 txq_id = il4965_txq_ctx_activate_free(il); 2253 if (txq_id == -1) { 2254 IL_ERR("No free aggregation queue available\n"); 2255 return -ENXIO; 2256 } 2257 2258 spin_lock_irqsave(&il->sta_lock, flags); 2259 tid_data = &il->stations[sta_id].tid[tid]; 2260 *ssn = SEQ_TO_SN(tid_data->seq_number); 2261 tid_data->agg.txq_id = txq_id; 2262 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id); 2263 spin_unlock_irqrestore(&il->sta_lock, flags); 2264 2265 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn); 2266 if (ret) 2267 return ret; 2268 2269 spin_lock_irqsave(&il->sta_lock, flags); 2270 tid_data = &il->stations[sta_id].tid[tid]; 2271 if (tid_data->tfds_in_queue == 0) { 2272 D_HT("HW queue is empty\n"); 2273 tid_data->agg.state = IL_AGG_ON; 2274 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2275 } else { 2276 D_HT("HW queue is NOT empty: %d packets in HW queue\n", 2277 tid_data->tfds_in_queue); 2278 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA; 2279 } 2280 spin_unlock_irqrestore(&il->sta_lock, flags); 2281 return ret; 2282} 2283 2284/** 2285 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE 2286 * il->lock must be held by the caller 2287 */ 2288static int 2289il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo) 2290{ 2291 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || 2292 (IL49_FIRST_AMPDU_QUEUE + 2293 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) { 2294 IL_WARN("queue number out of range: %d, must be %d to %d\n", 2295 txq_id, IL49_FIRST_AMPDU_QUEUE, 2296 IL49_FIRST_AMPDU_QUEUE + 2297 il->cfg->base_params->num_of_ampdu_queues - 1); 2298 return -EINVAL; 2299 } 2300 2301 il4965_tx_queue_stop_scheduler(il, txq_id); 2302 2303 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 2304 2305 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 2306 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 2307 /* supposes that ssn_idx is valid (!= 0xFFF) */ 2308 il4965_set_wr_ptrs(il, txq_id, ssn_idx); 2309 2310 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 2311 il_txq_ctx_deactivate(il, txq_id); 2312 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0); 2313 2314 return 0; 2315} 2316 2317int 2318il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif, 2319 struct ieee80211_sta *sta, u16 tid) 2320{ 2321 int tx_fifo_id, txq_id, sta_id, ssn; 2322 struct il_tid_data *tid_data; 2323 int write_ptr, read_ptr; 2324 unsigned long flags; 2325 2326 tx_fifo_id = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid); 2327 if (unlikely(tx_fifo_id < 0)) 2328 return tx_fifo_id; 2329 2330 sta_id = il_sta_id(sta); 2331 2332 if (sta_id == IL_INVALID_STATION) { 2333 IL_ERR("Invalid station for AGG tid %d\n", tid); 2334 return -ENXIO; 2335 } 2336 2337 spin_lock_irqsave(&il->sta_lock, flags); 2338 2339 tid_data = &il->stations[sta_id].tid[tid]; 2340 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; 2341 txq_id = tid_data->agg.txq_id; 2342 2343 switch (il->stations[sta_id].tid[tid].agg.state) { 2344 case IL_EMPTYING_HW_QUEUE_ADDBA: 2345 /* 2346 * This can happen if the peer stops aggregation 2347 * again before we've had a chance to drain the 2348 * queue we selected previously, i.e. before the 2349 * session was really started completely. 2350 */ 2351 D_HT("AGG stop before setup done\n"); 2352 goto turn_off; 2353 case IL_AGG_ON: 2354 break; 2355 default: 2356 IL_WARN("Stopping AGG while state not ON or starting\n"); 2357 } 2358 2359 write_ptr = il->txq[txq_id].q.write_ptr; 2360 read_ptr = il->txq[txq_id].q.read_ptr; 2361 2362 /* The queue is not empty */ 2363 if (write_ptr != read_ptr) { 2364 D_HT("Stopping a non empty AGG HW QUEUE\n"); 2365 il->stations[sta_id].tid[tid].agg.state = 2366 IL_EMPTYING_HW_QUEUE_DELBA; 2367 spin_unlock_irqrestore(&il->sta_lock, flags); 2368 return 0; 2369 } 2370 2371 D_HT("HW queue is empty\n"); 2372turn_off: 2373 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF; 2374 2375 /* do not restore/save irqs */ 2376 spin_unlock(&il->sta_lock); 2377 spin_lock(&il->lock); 2378 2379 /* 2380 * the only reason this call can fail is queue number out of range, 2381 * which can happen if uCode is reloaded and all the station 2382 * information are lost. if it is outside the range, there is no need 2383 * to deactivate the uCode queue, just return "success" to allow 2384 * mac80211 to clean up it own data. 2385 */ 2386 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id); 2387 spin_unlock_irqrestore(&il->lock, flags); 2388 2389 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2390 2391 return 0; 2392} 2393 2394int 2395il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id) 2396{ 2397 struct il_queue *q = &il->txq[txq_id].q; 2398 u8 *addr = il->stations[sta_id].sta.sta.addr; 2399 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid]; 2400 struct il_rxon_context *ctx; 2401 2402 ctx = &il->ctx; 2403 2404 lockdep_assert_held(&il->sta_lock); 2405 2406 switch (il->stations[sta_id].tid[tid].agg.state) { 2407 case IL_EMPTYING_HW_QUEUE_DELBA: 2408 /* We are reclaiming the last packet of the */ 2409 /* aggregated HW queue */ 2410 if (txq_id == tid_data->agg.txq_id && 2411 q->read_ptr == q->write_ptr) { 2412 u16 ssn = SEQ_TO_SN(tid_data->seq_number); 2413 int tx_fifo = il4965_get_fifo_from_tid(ctx, tid); 2414 D_HT("HW queue empty: continue DELBA flow\n"); 2415 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo); 2416 tid_data->agg.state = IL_AGG_OFF; 2417 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid); 2418 } 2419 break; 2420 case IL_EMPTYING_HW_QUEUE_ADDBA: 2421 /* We are reclaiming the last packet of the queue */ 2422 if (tid_data->tfds_in_queue == 0) { 2423 D_HT("HW queue empty: continue ADDBA flow\n"); 2424 tid_data->agg.state = IL_AGG_ON; 2425 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid); 2426 } 2427 break; 2428 } 2429 2430 return 0; 2431} 2432 2433static void 2434il4965_non_agg_tx_status(struct il_priv *il, struct il_rxon_context *ctx, 2435 const u8 *addr1) 2436{ 2437 struct ieee80211_sta *sta; 2438 struct il_station_priv *sta_priv; 2439 2440 rcu_read_lock(); 2441 sta = ieee80211_find_sta(ctx->vif, addr1); 2442 if (sta) { 2443 sta_priv = (void *)sta->drv_priv; 2444 /* avoid atomic ops if this isn't a client */ 2445 if (sta_priv->client && 2446 atomic_dec_return(&sta_priv->pending_frames) == 0) 2447 ieee80211_sta_block_awake(il->hw, sta, false); 2448 } 2449 rcu_read_unlock(); 2450} 2451 2452static void 2453il4965_tx_status(struct il_priv *il, struct il_tx_info *tx_info, bool is_agg) 2454{ 2455 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 2456 2457 if (!is_agg) 2458 il4965_non_agg_tx_status(il, tx_info->ctx, hdr->addr1); 2459 2460 ieee80211_tx_status_irqsafe(il->hw, tx_info->skb); 2461} 2462 2463int 2464il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx) 2465{ 2466 struct il_tx_queue *txq = &il->txq[txq_id]; 2467 struct il_queue *q = &txq->q; 2468 struct il_tx_info *tx_info; 2469 int nfreed = 0; 2470 struct ieee80211_hdr *hdr; 2471 2472 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) { 2473 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, " 2474 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd, 2475 q->write_ptr, q->read_ptr); 2476 return 0; 2477 } 2478 2479 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; 2480 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { 2481 2482 tx_info = &txq->txb[txq->q.read_ptr]; 2483 2484 if (WARN_ON_ONCE(tx_info->skb == NULL)) 2485 continue; 2486 2487 hdr = (struct ieee80211_hdr *)tx_info->skb->data; 2488 if (ieee80211_is_data_qos(hdr->frame_control)) 2489 nfreed++; 2490 2491 il4965_tx_status(il, tx_info, 2492 txq_id >= IL4965_FIRST_AMPDU_QUEUE); 2493 tx_info->skb = NULL; 2494 2495 il->cfg->ops->lib->txq_free_tfd(il, txq); 2496 } 2497 return nfreed; 2498} 2499 2500/** 2501 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack 2502 * 2503 * Go through block-ack's bitmap of ACK'd frames, update driver's record of 2504 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. 2505 */ 2506static int 2507il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg, 2508 struct il_compressed_ba_resp *ba_resp) 2509{ 2510 int i, sh, ack; 2511 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); 2512 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); 2513 int successes = 0; 2514 struct ieee80211_tx_info *info; 2515 u64 bitmap, sent_bitmap; 2516 2517 if (unlikely(!agg->wait_for_ba)) { 2518 if (unlikely(ba_resp->bitmap)) 2519 IL_ERR("Received BA when not expected\n"); 2520 return -EINVAL; 2521 } 2522 2523 /* Mark that the expected block-ack response arrived */ 2524 agg->wait_for_ba = 0; 2525 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); 2526 2527 /* Calculate shift to align block-ack bits with our Tx win bits */ 2528 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4); 2529 if (sh < 0) /* tbw something is wrong with indices */ 2530 sh += 0x100; 2531 2532 if (agg->frame_count > (64 - sh)) { 2533 D_TX_REPLY("more frames than bitmap size"); 2534 return -1; 2535 } 2536 2537 /* don't use 64-bit values for now */ 2538 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; 2539 2540 /* check for success or failure according to the 2541 * transmitted bitmap and block-ack bitmap */ 2542 sent_bitmap = bitmap & agg->bitmap; 2543 2544 /* For each frame attempted in aggregation, 2545 * update driver's record of tx frame's status. */ 2546 i = 0; 2547 while (sent_bitmap) { 2548 ack = sent_bitmap & 1ULL; 2549 successes += ack; 2550 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK", 2551 i, (agg->start_idx + i) & 0xff, agg->start_idx + i); 2552 sent_bitmap >>= 1; 2553 ++i; 2554 } 2555 2556 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap); 2557 2558 info = IEEE80211_SKB_CB(il->txq[scd_flow].txb[agg->start_idx].skb); 2559 memset(&info->status, 0, sizeof(info->status)); 2560 info->flags |= IEEE80211_TX_STAT_ACK; 2561 info->flags |= IEEE80211_TX_STAT_AMPDU; 2562 info->status.ampdu_ack_len = successes; 2563 info->status.ampdu_len = agg->frame_count; 2564 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info); 2565 2566 return 0; 2567} 2568 2569/** 2570 * translate ucode response to mac80211 tx status control values 2571 */ 2572void 2573il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags, 2574 struct ieee80211_tx_info *info) 2575{ 2576 struct ieee80211_tx_rate *r = &info->control.rates[0]; 2577 2578 info->antenna_sel_tx = 2579 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); 2580 if (rate_n_flags & RATE_MCS_HT_MSK) 2581 r->flags |= IEEE80211_TX_RC_MCS; 2582 if (rate_n_flags & RATE_MCS_GF_MSK) 2583 r->flags |= IEEE80211_TX_RC_GREEN_FIELD; 2584 if (rate_n_flags & RATE_MCS_HT40_MSK) 2585 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 2586 if (rate_n_flags & RATE_MCS_DUP_MSK) 2587 r->flags |= IEEE80211_TX_RC_DUP_DATA; 2588 if (rate_n_flags & RATE_MCS_SGI_MSK) 2589 r->flags |= IEEE80211_TX_RC_SHORT_GI; 2590 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band); 2591} 2592 2593/** 2594 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA 2595 * 2596 * Handles block-acknowledge notification from device, which reports success 2597 * of frames sent via aggregation. 2598 */ 2599void 2600il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb) 2601{ 2602 struct il_rx_pkt *pkt = rxb_addr(rxb); 2603 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; 2604 struct il_tx_queue *txq = NULL; 2605 struct il_ht_agg *agg; 2606 int idx; 2607 int sta_id; 2608 int tid; 2609 unsigned long flags; 2610 2611 /* "flow" corresponds to Tx queue */ 2612 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); 2613 2614 /* "ssn" is start of block-ack Tx win, corresponds to idx 2615 * (in Tx queue's circular buffer) of first TFD/frame in win */ 2616 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); 2617 2618 if (scd_flow >= il->hw_params.max_txq_num) { 2619 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n"); 2620 return; 2621 } 2622 2623 txq = &il->txq[scd_flow]; 2624 sta_id = ba_resp->sta_id; 2625 tid = ba_resp->tid; 2626 agg = &il->stations[sta_id].tid[tid].agg; 2627 if (unlikely(agg->txq_id != scd_flow)) { 2628 /* 2629 * FIXME: this is a uCode bug which need to be addressed, 2630 * log the information and return for now! 2631 * since it is possible happen very often and in order 2632 * not to fill the syslog, don't enable the logging by default 2633 */ 2634 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n", 2635 scd_flow, agg->txq_id); 2636 return; 2637 } 2638 2639 /* Find idx just before block-ack win */ 2640 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); 2641 2642 spin_lock_irqsave(&il->sta_lock, flags); 2643 2644 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n", 2645 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32, 2646 ba_resp->sta_id); 2647 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = " 2648 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl, 2649 (unsigned long long)le64_to_cpu(ba_resp->bitmap), 2650 ba_resp->scd_flow, ba_resp->scd_ssn); 2651 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx, 2652 (unsigned long long)agg->bitmap); 2653 2654 /* Update driver's record of ACK vs. not for each frame in win */ 2655 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp); 2656 2657 /* Release all TFDs before the SSN, i.e. all TFDs in front of 2658 * block-ack win (we assume that they've been successfully 2659 * transmitted ... if not, it's too late anyway). */ 2660 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { 2661 /* calculate mac80211 ampdu sw queue to wake */ 2662 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx); 2663 il4965_free_tfds_in_queue(il, sta_id, tid, freed); 2664 2665 if (il_queue_space(&txq->q) > txq->q.low_mark && 2666 il->mac80211_registered && 2667 agg->state != IL_EMPTYING_HW_QUEUE_DELBA) 2668 il_wake_queue(il, txq); 2669 2670 il4965_txq_check_empty(il, sta_id, tid, scd_flow); 2671 } 2672 2673 spin_unlock_irqrestore(&il->sta_lock, flags); 2674} 2675 2676#ifdef CONFIG_IWLEGACY_DEBUG 2677const char * 2678il4965_get_tx_fail_reason(u32 status) 2679{ 2680#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x 2681#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x 2682 2683 switch (status & TX_STATUS_MSK) { 2684 case TX_STATUS_SUCCESS: 2685 return "SUCCESS"; 2686 TX_STATUS_POSTPONE(DELAY); 2687 TX_STATUS_POSTPONE(FEW_BYTES); 2688 TX_STATUS_POSTPONE(QUIET_PERIOD); 2689 TX_STATUS_POSTPONE(CALC_TTAK); 2690 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); 2691 TX_STATUS_FAIL(SHORT_LIMIT); 2692 TX_STATUS_FAIL(LONG_LIMIT); 2693 TX_STATUS_FAIL(FIFO_UNDERRUN); 2694 TX_STATUS_FAIL(DRAIN_FLOW); 2695 TX_STATUS_FAIL(RFKILL_FLUSH); 2696 TX_STATUS_FAIL(LIFE_EXPIRE); 2697 TX_STATUS_FAIL(DEST_PS); 2698 TX_STATUS_FAIL(HOST_ABORTED); 2699 TX_STATUS_FAIL(BT_RETRY); 2700 TX_STATUS_FAIL(STA_INVALID); 2701 TX_STATUS_FAIL(FRAG_DROPPED); 2702 TX_STATUS_FAIL(TID_DISABLE); 2703 TX_STATUS_FAIL(FIFO_FLUSHED); 2704 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); 2705 TX_STATUS_FAIL(PASSIVE_NO_RX); 2706 TX_STATUS_FAIL(NO_BEACON_ON_RADAR); 2707 } 2708 2709 return "UNKNOWN"; 2710 2711#undef TX_STATUS_FAIL 2712#undef TX_STATUS_POSTPONE 2713} 2714#endif /* CONFIG_IWLEGACY_DEBUG */ 2715 2716static struct il_link_quality_cmd * 2717il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id) 2718{ 2719 int i, r; 2720 struct il_link_quality_cmd *link_cmd; 2721 u32 rate_flags = 0; 2722 __le32 rate_n_flags; 2723 2724 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL); 2725 if (!link_cmd) { 2726 IL_ERR("Unable to allocate memory for LQ cmd.\n"); 2727 return NULL; 2728 } 2729 /* Set up the rate scaling to start at selected rate, fall back 2730 * all the way down to 1M in IEEE order, and then spin on 1M */ 2731 if (il->band == IEEE80211_BAND_5GHZ) 2732 r = RATE_6M_IDX; 2733 else 2734 r = RATE_1M_IDX; 2735 2736 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE) 2737 rate_flags |= RATE_MCS_CCK_MSK; 2738 2739 rate_flags |= 2740 il4965_first_antenna(il->hw_params. 2741 valid_tx_ant) << RATE_MCS_ANT_POS; 2742 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags); 2743 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) 2744 link_cmd->rs_table[i].rate_n_flags = rate_n_flags; 2745 2746 link_cmd->general_params.single_stream_ant_msk = 2747 il4965_first_antenna(il->hw_params.valid_tx_ant); 2748 2749 link_cmd->general_params.dual_stream_ant_msk = 2750 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params. 2751 valid_tx_ant); 2752 if (!link_cmd->general_params.dual_stream_ant_msk) { 2753 link_cmd->general_params.dual_stream_ant_msk = ANT_AB; 2754 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) { 2755 link_cmd->general_params.dual_stream_ant_msk = 2756 il->hw_params.valid_tx_ant; 2757 } 2758 2759 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF; 2760 link_cmd->agg_params.agg_time_limit = 2761 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF); 2762 2763 link_cmd->sta_id = sta_id; 2764 2765 return link_cmd; 2766} 2767 2768/* 2769 * il4965_add_bssid_station - Add the special IBSS BSSID station 2770 * 2771 * Function sleeps. 2772 */ 2773int 2774il4965_add_bssid_station(struct il_priv *il, struct il_rxon_context *ctx, 2775 const u8 *addr, u8 *sta_id_r) 2776{ 2777 int ret; 2778 u8 sta_id; 2779 struct il_link_quality_cmd *link_cmd; 2780 unsigned long flags; 2781 2782 if (sta_id_r) 2783 *sta_id_r = IL_INVALID_STATION; 2784 2785 ret = il_add_station_common(il, ctx, addr, 0, NULL, &sta_id); 2786 if (ret) { 2787 IL_ERR("Unable to add station %pM\n", addr); 2788 return ret; 2789 } 2790 2791 if (sta_id_r) 2792 *sta_id_r = sta_id; 2793 2794 spin_lock_irqsave(&il->sta_lock, flags); 2795 il->stations[sta_id].used |= IL_STA_LOCAL; 2796 spin_unlock_irqrestore(&il->sta_lock, flags); 2797 2798 /* Set up default rate scaling table in device's station table */ 2799 link_cmd = il4965_sta_alloc_lq(il, sta_id); 2800 if (!link_cmd) { 2801 IL_ERR("Unable to initialize rate scaling for station %pM.\n", 2802 addr); 2803 return -ENOMEM; 2804 } 2805 2806 ret = il_send_lq_cmd(il, ctx, link_cmd, CMD_SYNC, true); 2807 if (ret) 2808 IL_ERR("Link quality command failed (%d)\n", ret); 2809 2810 spin_lock_irqsave(&il->sta_lock, flags); 2811 il->stations[sta_id].lq = link_cmd; 2812 spin_unlock_irqrestore(&il->sta_lock, flags); 2813 2814 return 0; 2815} 2816 2817static int 2818il4965_static_wepkey_cmd(struct il_priv *il, struct il_rxon_context *ctx, 2819 bool send_if_empty) 2820{ 2821 int i, not_empty = 0; 2822 u8 buff[sizeof(struct il_wep_cmd) + 2823 sizeof(struct il_wep_key) * WEP_KEYS_MAX]; 2824 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff; 2825 size_t cmd_size = sizeof(struct il_wep_cmd); 2826 struct il_host_cmd cmd = { 2827 .id = ctx->wep_key_cmd, 2828 .data = wep_cmd, 2829 .flags = CMD_SYNC, 2830 }; 2831 2832 might_sleep(); 2833 2834 memset(wep_cmd, 0, 2835 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX)); 2836 2837 for (i = 0; i < WEP_KEYS_MAX; i++) { 2838 wep_cmd->key[i].key_idx = i; 2839 if (ctx->wep_keys[i].key_size) { 2840 wep_cmd->key[i].key_offset = i; 2841 not_empty = 1; 2842 } else { 2843 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET; 2844 } 2845 2846 wep_cmd->key[i].key_size = ctx->wep_keys[i].key_size; 2847 memcpy(&wep_cmd->key[i].key[3], ctx->wep_keys[i].key, 2848 ctx->wep_keys[i].key_size); 2849 } 2850 2851 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE; 2852 wep_cmd->num_keys = WEP_KEYS_MAX; 2853 2854 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX; 2855 2856 cmd.len = cmd_size; 2857 2858 if (not_empty || send_if_empty) 2859 return il_send_cmd(il, &cmd); 2860 else 2861 return 0; 2862} 2863 2864int 2865il4965_restore_default_wep_keys(struct il_priv *il, struct il_rxon_context *ctx) 2866{ 2867 lockdep_assert_held(&il->mutex); 2868 2869 return il4965_static_wepkey_cmd(il, ctx, false); 2870} 2871 2872int 2873il4965_remove_default_wep_key(struct il_priv *il, struct il_rxon_context *ctx, 2874 struct ieee80211_key_conf *keyconf) 2875{ 2876 int ret; 2877 2878 lockdep_assert_held(&il->mutex); 2879 2880 D_WEP("Removing default WEP key: idx=%d\n", keyconf->keyidx); 2881 2882 memset(&ctx->wep_keys[keyconf->keyidx], 0, sizeof(ctx->wep_keys[0])); 2883 if (il_is_rfkill(il)) { 2884 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n"); 2885 /* but keys in device are clear anyway so return success */ 2886 return 0; 2887 } 2888 ret = il4965_static_wepkey_cmd(il, ctx, 1); 2889 D_WEP("Remove default WEP key: idx=%d ret=%d\n", keyconf->keyidx, ret); 2890 2891 return ret; 2892} 2893 2894int 2895il4965_set_default_wep_key(struct il_priv *il, struct il_rxon_context *ctx, 2896 struct ieee80211_key_conf *keyconf) 2897{ 2898 int ret; 2899 2900 lockdep_assert_held(&il->mutex); 2901 2902 if (keyconf->keylen != WEP_KEY_LEN_128 && 2903 keyconf->keylen != WEP_KEY_LEN_64) { 2904 D_WEP("Bad WEP key length %d\n", keyconf->keylen); 2905 return -EINVAL; 2906 } 2907 2908 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 2909 keyconf->hw_key_idx = HW_KEY_DEFAULT; 2910 il->stations[ctx->ap_sta_id].keyinfo.cipher = keyconf->cipher; 2911 2912 ctx->wep_keys[keyconf->keyidx].key_size = keyconf->keylen; 2913 memcpy(&ctx->wep_keys[keyconf->keyidx].key, &keyconf->key, 2914 keyconf->keylen); 2915 2916 ret = il4965_static_wepkey_cmd(il, ctx, false); 2917 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", keyconf->keylen, 2918 keyconf->keyidx, ret); 2919 2920 return ret; 2921} 2922 2923static int 2924il4965_set_wep_dynamic_key_info(struct il_priv *il, struct il_rxon_context *ctx, 2925 struct ieee80211_key_conf *keyconf, u8 sta_id) 2926{ 2927 unsigned long flags; 2928 __le16 key_flags = 0; 2929 struct il_addsta_cmd sta_cmd; 2930 2931 lockdep_assert_held(&il->mutex); 2932 2933 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 2934 2935 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK); 2936 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 2937 key_flags &= ~STA_KEY_FLG_INVALID; 2938 2939 if (keyconf->keylen == WEP_KEY_LEN_128) 2940 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK; 2941 2942 if (sta_id == ctx->bcast_sta_id) 2943 key_flags |= STA_KEY_MULTICAST_MSK; 2944 2945 spin_lock_irqsave(&il->sta_lock, flags); 2946 2947 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 2948 il->stations[sta_id].keyinfo.keylen = keyconf->keylen; 2949 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx; 2950 2951 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); 2952 2953 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key, 2954 keyconf->keylen); 2955 2956 if ((il->stations[sta_id].sta.key. 2957 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 2958 il->stations[sta_id].sta.key.key_offset = 2959 il_get_free_ucode_key_idx(il); 2960 /* else, we are overriding an existing key => no need to allocated room 2961 * in uCode. */ 2962 2963 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 2964 "no space for a new key"); 2965 2966 il->stations[sta_id].sta.key.key_flags = key_flags; 2967 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 2968 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 2969 2970 memcpy(&sta_cmd, &il->stations[sta_id].sta, 2971 sizeof(struct il_addsta_cmd)); 2972 spin_unlock_irqrestore(&il->sta_lock, flags); 2973 2974 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 2975} 2976 2977static int 2978il4965_set_ccmp_dynamic_key_info(struct il_priv *il, 2979 struct il_rxon_context *ctx, 2980 struct ieee80211_key_conf *keyconf, u8 sta_id) 2981{ 2982 unsigned long flags; 2983 __le16 key_flags = 0; 2984 struct il_addsta_cmd sta_cmd; 2985 2986 lockdep_assert_held(&il->mutex); 2987 2988 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); 2989 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 2990 key_flags &= ~STA_KEY_FLG_INVALID; 2991 2992 if (sta_id == ctx->bcast_sta_id) 2993 key_flags |= STA_KEY_MULTICAST_MSK; 2994 2995 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 2996 2997 spin_lock_irqsave(&il->sta_lock, flags); 2998 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 2999 il->stations[sta_id].keyinfo.keylen = keyconf->keylen; 3000 3001 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); 3002 3003 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen); 3004 3005 if ((il->stations[sta_id].sta.key. 3006 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3007 il->stations[sta_id].sta.key.key_offset = 3008 il_get_free_ucode_key_idx(il); 3009 /* else, we are overriding an existing key => no need to allocated room 3010 * in uCode. */ 3011 3012 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3013 "no space for a new key"); 3014 3015 il->stations[sta_id].sta.key.key_flags = key_flags; 3016 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3017 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3018 3019 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3020 sizeof(struct il_addsta_cmd)); 3021 spin_unlock_irqrestore(&il->sta_lock, flags); 3022 3023 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3024} 3025 3026static int 3027il4965_set_tkip_dynamic_key_info(struct il_priv *il, 3028 struct il_rxon_context *ctx, 3029 struct ieee80211_key_conf *keyconf, u8 sta_id) 3030{ 3031 unsigned long flags; 3032 int ret = 0; 3033 __le16 key_flags = 0; 3034 3035 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); 3036 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3037 key_flags &= ~STA_KEY_FLG_INVALID; 3038 3039 if (sta_id == ctx->bcast_sta_id) 3040 key_flags |= STA_KEY_MULTICAST_MSK; 3041 3042 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3043 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 3044 3045 spin_lock_irqsave(&il->sta_lock, flags); 3046 3047 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 3048 il->stations[sta_id].keyinfo.keylen = 16; 3049 3050 if ((il->stations[sta_id].sta.key. 3051 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3052 il->stations[sta_id].sta.key.key_offset = 3053 il_get_free_ucode_key_idx(il); 3054 /* else, we are overriding an existing key => no need to allocated room 3055 * in uCode. */ 3056 3057 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3058 "no space for a new key"); 3059 3060 il->stations[sta_id].sta.key.key_flags = key_flags; 3061 3062 /* This copy is acutally not needed: we get the key with each TX */ 3063 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16); 3064 3065 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16); 3066 3067 spin_unlock_irqrestore(&il->sta_lock, flags); 3068 3069 return ret; 3070} 3071 3072void 3073il4965_update_tkip_key(struct il_priv *il, struct il_rxon_context *ctx, 3074 struct ieee80211_key_conf *keyconf, 3075 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key) 3076{ 3077 u8 sta_id; 3078 unsigned long flags; 3079 int i; 3080 3081 if (il_scan_cancel(il)) { 3082 /* cancel scan failed, just live w/ bad key and rely 3083 briefly on SW decryption */ 3084 return; 3085 } 3086 3087 sta_id = il_sta_id_or_broadcast(il, ctx, sta); 3088 if (sta_id == IL_INVALID_STATION) 3089 return; 3090 3091 spin_lock_irqsave(&il->sta_lock, flags); 3092 3093 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; 3094 3095 for (i = 0; i < 5; i++) 3096 il->stations[sta_id].sta.key.tkip_rx_ttak[i] = 3097 cpu_to_le16(phase1key[i]); 3098 3099 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3100 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3101 3102 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); 3103 3104 spin_unlock_irqrestore(&il->sta_lock, flags); 3105 3106} 3107 3108int 3109il4965_remove_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx, 3110 struct ieee80211_key_conf *keyconf, u8 sta_id) 3111{ 3112 unsigned long flags; 3113 u16 key_flags; 3114 u8 keyidx; 3115 struct il_addsta_cmd sta_cmd; 3116 3117 lockdep_assert_held(&il->mutex); 3118 3119 ctx->key_mapping_keys--; 3120 3121 spin_lock_irqsave(&il->sta_lock, flags); 3122 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags); 3123 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3; 3124 3125 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id); 3126 3127 if (keyconf->keyidx != keyidx) { 3128 /* We need to remove a key with idx different that the one 3129 * in the uCode. This means that the key we need to remove has 3130 * been replaced by another one with different idx. 3131 * Don't do anything and return ok 3132 */ 3133 spin_unlock_irqrestore(&il->sta_lock, flags); 3134 return 0; 3135 } 3136 3137 if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) { 3138 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx, 3139 key_flags); 3140 spin_unlock_irqrestore(&il->sta_lock, flags); 3141 return 0; 3142 } 3143 3144 if (!test_and_clear_bit 3145 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table)) 3146 IL_ERR("idx %d not used in uCode key table.\n", 3147 il->stations[sta_id].sta.key.key_offset); 3148 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key)); 3149 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo)); 3150 il->stations[sta_id].sta.key.key_flags = 3151 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID; 3152 il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET; 3153 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3154 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3155 3156 if (il_is_rfkill(il)) { 3157 D_WEP 3158 ("Not sending C_ADD_STA command because RFKILL enabled.\n"); 3159 spin_unlock_irqrestore(&il->sta_lock, flags); 3160 return 0; 3161 } 3162 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3163 sizeof(struct il_addsta_cmd)); 3164 spin_unlock_irqrestore(&il->sta_lock, flags); 3165 3166 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3167} 3168 3169int 3170il4965_set_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx, 3171 struct ieee80211_key_conf *keyconf, u8 sta_id) 3172{ 3173 int ret; 3174 3175 lockdep_assert_held(&il->mutex); 3176 3177 ctx->key_mapping_keys++; 3178 keyconf->hw_key_idx = HW_KEY_DYNAMIC; 3179 3180 switch (keyconf->cipher) { 3181 case WLAN_CIPHER_SUITE_CCMP: 3182 ret = 3183 il4965_set_ccmp_dynamic_key_info(il, ctx, keyconf, sta_id); 3184 break; 3185 case WLAN_CIPHER_SUITE_TKIP: 3186 ret = 3187 il4965_set_tkip_dynamic_key_info(il, ctx, keyconf, sta_id); 3188 break; 3189 case WLAN_CIPHER_SUITE_WEP40: 3190 case WLAN_CIPHER_SUITE_WEP104: 3191 ret = il4965_set_wep_dynamic_key_info(il, ctx, keyconf, sta_id); 3192 break; 3193 default: 3194 IL_ERR("Unknown alg: %s cipher = %x\n", __func__, 3195 keyconf->cipher); 3196 ret = -EINVAL; 3197 } 3198 3199 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n", 3200 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret); 3201 3202 return ret; 3203} 3204 3205/** 3206 * il4965_alloc_bcast_station - add broadcast station into driver's station table. 3207 * 3208 * This adds the broadcast station into the driver's station table 3209 * and marks it driver active, so that it will be restored to the 3210 * device at the next best time. 3211 */ 3212int 3213il4965_alloc_bcast_station(struct il_priv *il, struct il_rxon_context *ctx) 3214{ 3215 struct il_link_quality_cmd *link_cmd; 3216 unsigned long flags; 3217 u8 sta_id; 3218 3219 spin_lock_irqsave(&il->sta_lock, flags); 3220 sta_id = il_prep_station(il, ctx, il_bcast_addr, false, NULL); 3221 if (sta_id == IL_INVALID_STATION) { 3222 IL_ERR("Unable to prepare broadcast station\n"); 3223 spin_unlock_irqrestore(&il->sta_lock, flags); 3224 3225 return -EINVAL; 3226 } 3227 3228 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE; 3229 il->stations[sta_id].used |= IL_STA_BCAST; 3230 spin_unlock_irqrestore(&il->sta_lock, flags); 3231 3232 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3233 if (!link_cmd) { 3234 IL_ERR 3235 ("Unable to initialize rate scaling for bcast station.\n"); 3236 return -ENOMEM; 3237 } 3238 3239 spin_lock_irqsave(&il->sta_lock, flags); 3240 il->stations[sta_id].lq = link_cmd; 3241 spin_unlock_irqrestore(&il->sta_lock, flags); 3242 3243 return 0; 3244} 3245 3246/** 3247 * il4965_update_bcast_station - update broadcast station's LQ command 3248 * 3249 * Only used by iwl4965. Placed here to have all bcast station management 3250 * code together. 3251 */ 3252static int 3253il4965_update_bcast_station(struct il_priv *il, struct il_rxon_context *ctx) 3254{ 3255 unsigned long flags; 3256 struct il_link_quality_cmd *link_cmd; 3257 u8 sta_id = ctx->bcast_sta_id; 3258 3259 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3260 if (!link_cmd) { 3261 IL_ERR("Unable to initialize rate scaling for bcast sta.\n"); 3262 return -ENOMEM; 3263 } 3264 3265 spin_lock_irqsave(&il->sta_lock, flags); 3266 if (il->stations[sta_id].lq) 3267 kfree(il->stations[sta_id].lq); 3268 else 3269 D_INFO("Bcast sta rate scaling has not been initialized.\n"); 3270 il->stations[sta_id].lq = link_cmd; 3271 spin_unlock_irqrestore(&il->sta_lock, flags); 3272 3273 return 0; 3274} 3275 3276int 3277il4965_update_bcast_stations(struct il_priv *il) 3278{ 3279 return il4965_update_bcast_station(il, &il->ctx); 3280} 3281 3282/** 3283 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table 3284 */ 3285int 3286il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid) 3287{ 3288 unsigned long flags; 3289 struct il_addsta_cmd sta_cmd; 3290 3291 lockdep_assert_held(&il->mutex); 3292 3293 /* Remove "disable" flag, to enable Tx for this TID */ 3294 spin_lock_irqsave(&il->sta_lock, flags); 3295 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX; 3296 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid)); 3297 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3298 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3299 sizeof(struct il_addsta_cmd)); 3300 spin_unlock_irqrestore(&il->sta_lock, flags); 3301 3302 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3303} 3304 3305int 3306il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid, 3307 u16 ssn) 3308{ 3309 unsigned long flags; 3310 int sta_id; 3311 struct il_addsta_cmd sta_cmd; 3312 3313 lockdep_assert_held(&il->mutex); 3314 3315 sta_id = il_sta_id(sta); 3316 if (sta_id == IL_INVALID_STATION) 3317 return -ENXIO; 3318 3319 spin_lock_irqsave(&il->sta_lock, flags); 3320 il->stations[sta_id].sta.station_flags_msk = 0; 3321 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK; 3322 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid; 3323 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn); 3324 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3325 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3326 sizeof(struct il_addsta_cmd)); 3327 spin_unlock_irqrestore(&il->sta_lock, flags); 3328 3329 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3330} 3331 3332int 3333il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid) 3334{ 3335 unsigned long flags; 3336 int sta_id; 3337 struct il_addsta_cmd sta_cmd; 3338 3339 lockdep_assert_held(&il->mutex); 3340 3341 sta_id = il_sta_id(sta); 3342 if (sta_id == IL_INVALID_STATION) { 3343 IL_ERR("Invalid station for AGG tid %d\n", tid); 3344 return -ENXIO; 3345 } 3346 3347 spin_lock_irqsave(&il->sta_lock, flags); 3348 il->stations[sta_id].sta.station_flags_msk = 0; 3349 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK; 3350 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid; 3351 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3352 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3353 sizeof(struct il_addsta_cmd)); 3354 spin_unlock_irqrestore(&il->sta_lock, flags); 3355 3356 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3357} 3358 3359void 3360il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt) 3361{ 3362 unsigned long flags; 3363 3364 spin_lock_irqsave(&il->sta_lock, flags); 3365 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK; 3366 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK; 3367 il->stations[sta_id].sta.sta.modify_mask = 3368 STA_MODIFY_SLEEP_TX_COUNT_MSK; 3369 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt); 3370 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3371 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); 3372 spin_unlock_irqrestore(&il->sta_lock, flags); 3373 3374} 3375 3376void 3377il4965_update_chain_flags(struct il_priv *il) 3378{ 3379 if (il->cfg->ops->hcmd->set_rxon_chain) { 3380 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx); 3381 if (il->ctx.active.rx_chain != il->ctx.staging.rx_chain) 3382 il_commit_rxon(il, &il->ctx); 3383 } 3384} 3385 3386static void 3387il4965_clear_free_frames(struct il_priv *il) 3388{ 3389 struct list_head *element; 3390 3391 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count); 3392 3393 while (!list_empty(&il->free_frames)) { 3394 element = il->free_frames.next; 3395 list_del(element); 3396 kfree(list_entry(element, struct il_frame, list)); 3397 il->frames_count--; 3398 } 3399 3400 if (il->frames_count) { 3401 IL_WARN("%d frames still in use. Did we lose one?\n", 3402 il->frames_count); 3403 il->frames_count = 0; 3404 } 3405} 3406 3407static struct il_frame * 3408il4965_get_free_frame(struct il_priv *il) 3409{ 3410 struct il_frame *frame; 3411 struct list_head *element; 3412 if (list_empty(&il->free_frames)) { 3413 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 3414 if (!frame) { 3415 IL_ERR("Could not allocate frame!\n"); 3416 return NULL; 3417 } 3418 3419 il->frames_count++; 3420 return frame; 3421 } 3422 3423 element = il->free_frames.next; 3424 list_del(element); 3425 return list_entry(element, struct il_frame, list); 3426} 3427 3428static void 3429il4965_free_frame(struct il_priv *il, struct il_frame *frame) 3430{ 3431 memset(frame, 0, sizeof(*frame)); 3432 list_add(&frame->list, &il->free_frames); 3433} 3434 3435static u32 3436il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr, 3437 int left) 3438{ 3439 lockdep_assert_held(&il->mutex); 3440 3441 if (!il->beacon_skb) 3442 return 0; 3443 3444 if (il->beacon_skb->len > left) 3445 return 0; 3446 3447 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len); 3448 3449 return il->beacon_skb->len; 3450} 3451 3452/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ 3453static void 3454il4965_set_beacon_tim(struct il_priv *il, 3455 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon, 3456 u32 frame_size) 3457{ 3458 u16 tim_idx; 3459 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; 3460 3461 /* 3462 * The idx is relative to frame start but we start looking at the 3463 * variable-length part of the beacon. 3464 */ 3465 tim_idx = mgmt->u.beacon.variable - beacon; 3466 3467 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ 3468 while ((tim_idx < (frame_size - 2)) && 3469 (beacon[tim_idx] != WLAN_EID_TIM)) 3470 tim_idx += beacon[tim_idx + 1] + 2; 3471 3472 /* If TIM field was found, set variables */ 3473 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { 3474 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); 3475 tx_beacon_cmd->tim_size = beacon[tim_idx + 1]; 3476 } else 3477 IL_WARN("Unable to find TIM Element in beacon\n"); 3478} 3479 3480static unsigned int 3481il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame) 3482{ 3483 struct il_tx_beacon_cmd *tx_beacon_cmd; 3484 u32 frame_size; 3485 u32 rate_flags; 3486 u32 rate; 3487 /* 3488 * We have to set up the TX command, the TX Beacon command, and the 3489 * beacon contents. 3490 */ 3491 3492 lockdep_assert_held(&il->mutex); 3493 3494 if (!il->beacon_ctx) { 3495 IL_ERR("trying to build beacon w/o beacon context!\n"); 3496 return 0; 3497 } 3498 3499 /* Initialize memory */ 3500 tx_beacon_cmd = &frame->u.beacon; 3501 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); 3502 3503 /* Set up TX beacon contents */ 3504 frame_size = 3505 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame, 3506 sizeof(frame->u) - sizeof(*tx_beacon_cmd)); 3507 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) 3508 return 0; 3509 if (!frame_size) 3510 return 0; 3511 3512 /* Set up TX command fields */ 3513 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size); 3514 tx_beacon_cmd->tx.sta_id = il->beacon_ctx->bcast_sta_id; 3515 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 3516 tx_beacon_cmd->tx.tx_flags = 3517 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK | 3518 TX_CMD_FLG_STA_RATE_MSK; 3519 3520 /* Set up TX beacon command fields */ 3521 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame, 3522 frame_size); 3523 3524 /* Set up packet rate and flags */ 3525 rate = il_get_lowest_plcp(il, il->beacon_ctx); 3526 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); 3527 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; 3528 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE)) 3529 rate_flags |= RATE_MCS_CCK_MSK; 3530 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags); 3531 3532 return sizeof(*tx_beacon_cmd) + frame_size; 3533} 3534 3535int 3536il4965_send_beacon_cmd(struct il_priv *il) 3537{ 3538 struct il_frame *frame; 3539 unsigned int frame_size; 3540 int rc; 3541 3542 frame = il4965_get_free_frame(il); 3543 if (!frame) { 3544 IL_ERR("Could not obtain free frame buffer for beacon " 3545 "command.\n"); 3546 return -ENOMEM; 3547 } 3548 3549 frame_size = il4965_hw_get_beacon_cmd(il, frame); 3550 if (!frame_size) { 3551 IL_ERR("Error configuring the beacon command\n"); 3552 il4965_free_frame(il, frame); 3553 return -EINVAL; 3554 } 3555 3556 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]); 3557 3558 il4965_free_frame(il, frame); 3559 3560 return rc; 3561} 3562 3563static inline dma_addr_t 3564il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx) 3565{ 3566 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3567 3568 dma_addr_t addr = get_unaligned_le32(&tb->lo); 3569 if (sizeof(dma_addr_t) > sizeof(u32)) 3570 addr |= 3571 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 3572 16; 3573 3574 return addr; 3575} 3576 3577static inline u16 3578il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx) 3579{ 3580 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3581 3582 return le16_to_cpu(tb->hi_n_len) >> 4; 3583} 3584 3585static inline void 3586il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len) 3587{ 3588 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3589 u16 hi_n_len = len << 4; 3590 3591 put_unaligned_le32(addr, &tb->lo); 3592 if (sizeof(dma_addr_t) > sizeof(u32)) 3593 hi_n_len |= ((addr >> 16) >> 16) & 0xF; 3594 3595 tb->hi_n_len = cpu_to_le16(hi_n_len); 3596 3597 tfd->num_tbs = idx + 1; 3598} 3599 3600static inline u8 3601il4965_tfd_get_num_tbs(struct il_tfd *tfd) 3602{ 3603 return tfd->num_tbs & 0x1f; 3604} 3605 3606/** 3607 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 3608 * @il - driver ilate data 3609 * @txq - tx queue 3610 * 3611 * Does NOT advance any TFD circular buffer read/write idxes 3612 * Does NOT free the TFD itself (which is within circular buffer) 3613 */ 3614void 3615il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq) 3616{ 3617 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds; 3618 struct il_tfd *tfd; 3619 struct pci_dev *dev = il->pci_dev; 3620 int idx = txq->q.read_ptr; 3621 int i; 3622 int num_tbs; 3623 3624 tfd = &tfd_tmp[idx]; 3625 3626 /* Sanity check on number of chunks */ 3627 num_tbs = il4965_tfd_get_num_tbs(tfd); 3628 3629 if (num_tbs >= IL_NUM_OF_TBS) { 3630 IL_ERR("Too many chunks: %i\n", num_tbs); 3631 /* @todo issue fatal error, it is quite serious situation */ 3632 return; 3633 } 3634 3635 /* Unmap tx_cmd */ 3636 if (num_tbs) 3637 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping), 3638 dma_unmap_len(&txq->meta[idx], len), 3639 PCI_DMA_BIDIRECTIONAL); 3640 3641 /* Unmap chunks, if any. */ 3642 for (i = 1; i < num_tbs; i++) 3643 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i), 3644 il4965_tfd_tb_get_len(tfd, i), 3645 PCI_DMA_TODEVICE); 3646 3647 /* free SKB */ 3648 if (txq->txb) { 3649 struct sk_buff *skb; 3650 3651 skb = txq->txb[txq->q.read_ptr].skb; 3652 3653 /* can be called from irqs-disabled context */ 3654 if (skb) { 3655 dev_kfree_skb_any(skb); 3656 txq->txb[txq->q.read_ptr].skb = NULL; 3657 } 3658 } 3659} 3660 3661int 3662il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 3663 dma_addr_t addr, u16 len, u8 reset, u8 pad) 3664{ 3665 struct il_queue *q; 3666 struct il_tfd *tfd, *tfd_tmp; 3667 u32 num_tbs; 3668 3669 q = &txq->q; 3670 tfd_tmp = (struct il_tfd *)txq->tfds; 3671 tfd = &tfd_tmp[q->write_ptr]; 3672 3673 if (reset) 3674 memset(tfd, 0, sizeof(*tfd)); 3675 3676 num_tbs = il4965_tfd_get_num_tbs(tfd); 3677 3678 /* Each TFD can point to a maximum 20 Tx buffers */ 3679 if (num_tbs >= IL_NUM_OF_TBS) { 3680 IL_ERR("Error can not send more than %d chunks\n", 3681 IL_NUM_OF_TBS); 3682 return -EINVAL; 3683 } 3684 3685 BUG_ON(addr & ~DMA_BIT_MASK(36)); 3686 if (unlikely(addr & ~IL_TX_DMA_MASK)) 3687 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr); 3688 3689 il4965_tfd_set_tb(tfd, num_tbs, addr, len); 3690 3691 return 0; 3692} 3693 3694/* 3695 * Tell nic where to find circular buffer of Tx Frame Descriptors for 3696 * given Tx queue, and enable the DMA channel used for that queue. 3697 * 3698 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA 3699 * channels supported in hardware. 3700 */ 3701int 3702il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) 3703{ 3704 int txq_id = txq->q.id; 3705 3706 /* Circular buffer (TFD queue in DRAM) physical base address */ 3707 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8); 3708 3709 return 0; 3710} 3711 3712/****************************************************************************** 3713 * 3714 * Generic RX handler implementations 3715 * 3716 ******************************************************************************/ 3717static void 3718il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb) 3719{ 3720 struct il_rx_pkt *pkt = rxb_addr(rxb); 3721 struct il_alive_resp *palive; 3722 struct delayed_work *pwork; 3723 3724 palive = &pkt->u.alive_frame; 3725 3726 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n", 3727 palive->is_valid, palive->ver_type, palive->ver_subtype); 3728 3729 if (palive->ver_subtype == INITIALIZE_SUBTYPE) { 3730 D_INFO("Initialization Alive received.\n"); 3731 memcpy(&il->card_alive_init, &pkt->u.alive_frame, 3732 sizeof(struct il_init_alive_resp)); 3733 pwork = &il->init_alive_start; 3734 } else { 3735 D_INFO("Runtime Alive received.\n"); 3736 memcpy(&il->card_alive, &pkt->u.alive_frame, 3737 sizeof(struct il_alive_resp)); 3738 pwork = &il->alive_start; 3739 } 3740 3741 /* We delay the ALIVE response by 5ms to 3742 * give the HW RF Kill time to activate... */ 3743 if (palive->is_valid == UCODE_VALID_OK) 3744 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5)); 3745 else 3746 IL_WARN("uCode did not respond OK.\n"); 3747} 3748 3749/** 3750 * il4965_bg_stats_periodic - Timer callback to queue stats 3751 * 3752 * This callback is provided in order to send a stats request. 3753 * 3754 * This timer function is continually reset to execute within 3755 * REG_RECALIB_PERIOD seconds since the last N_STATS 3756 * was received. We need to ensure we receive the stats in order 3757 * to update the temperature used for calibrating the TXPOWER. 3758 */ 3759static void 3760il4965_bg_stats_periodic(unsigned long data) 3761{ 3762 struct il_priv *il = (struct il_priv *)data; 3763 3764 if (test_bit(S_EXIT_PENDING, &il->status)) 3765 return; 3766 3767 /* dont send host command if rf-kill is on */ 3768 if (!il_is_ready_rf(il)) 3769 return; 3770 3771 il_send_stats_request(il, CMD_ASYNC, false); 3772} 3773 3774static void 3775il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb) 3776{ 3777 struct il_rx_pkt *pkt = rxb_addr(rxb); 3778 struct il4965_beacon_notif *beacon = 3779 (struct il4965_beacon_notif *)pkt->u.raw; 3780#ifdef CONFIG_IWLEGACY_DEBUG 3781 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); 3782 3783 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n", 3784 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, 3785 beacon->beacon_notify_hdr.failure_frame, 3786 le32_to_cpu(beacon->ibss_mgr_status), 3787 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate); 3788#endif 3789 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); 3790} 3791 3792static void 3793il4965_perform_ct_kill_task(struct il_priv *il) 3794{ 3795 unsigned long flags; 3796 3797 D_POWER("Stop all queues\n"); 3798 3799 if (il->mac80211_registered) 3800 ieee80211_stop_queues(il->hw); 3801 3802 _il_wr(il, CSR_UCODE_DRV_GP1_SET, 3803 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 3804 _il_rd(il, CSR_UCODE_DRV_GP1); 3805 3806 spin_lock_irqsave(&il->reg_lock, flags); 3807 if (!_il_grab_nic_access(il)) 3808 _il_release_nic_access(il); 3809 spin_unlock_irqrestore(&il->reg_lock, flags); 3810} 3811 3812/* Handle notification from uCode that card's power state is changing 3813 * due to software, hardware, or critical temperature RFKILL */ 3814static void 3815il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb) 3816{ 3817 struct il_rx_pkt *pkt = rxb_addr(rxb); 3818 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); 3819 unsigned long status = il->status; 3820 3821 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n", 3822 (flags & HW_CARD_DISABLED) ? "Kill" : "On", 3823 (flags & SW_CARD_DISABLED) ? "Kill" : "On", 3824 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached"); 3825 3826 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) { 3827 3828 _il_wr(il, CSR_UCODE_DRV_GP1_SET, 3829 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 3830 3831 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 3832 3833 if (!(flags & RXON_CARD_DISABLED)) { 3834 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, 3835 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 3836 il_wr(il, HBUS_TARG_MBX_C, 3837 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 3838 } 3839 } 3840 3841 if (flags & CT_CARD_DISABLED) 3842 il4965_perform_ct_kill_task(il); 3843 3844 if (flags & HW_CARD_DISABLED) 3845 set_bit(S_RF_KILL_HW, &il->status); 3846 else 3847 clear_bit(S_RF_KILL_HW, &il->status); 3848 3849 if (!(flags & RXON_CARD_DISABLED)) 3850 il_scan_cancel(il); 3851 3852 if ((test_bit(S_RF_KILL_HW, &status) != 3853 test_bit(S_RF_KILL_HW, &il->status))) 3854 wiphy_rfkill_set_hw_state(il->hw->wiphy, 3855 test_bit(S_RF_KILL_HW, &il->status)); 3856 else 3857 wake_up(&il->wait_command_queue); 3858} 3859 3860/** 3861 * il4965_setup_handlers - Initialize Rx handler callbacks 3862 * 3863 * Setup the RX handlers for each of the reply types sent from the uCode 3864 * to the host. 3865 * 3866 * This function chains into the hardware specific files for them to setup 3867 * any hardware specific handlers as well. 3868 */ 3869static void 3870il4965_setup_handlers(struct il_priv *il) 3871{ 3872 il->handlers[N_ALIVE] = il4965_hdl_alive; 3873 il->handlers[N_ERROR] = il_hdl_error; 3874 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa; 3875 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement; 3876 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep; 3877 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats; 3878 il->handlers[N_BEACON] = il4965_hdl_beacon; 3879 3880 /* 3881 * The same handler is used for both the REPLY to a discrete 3882 * stats request from the host as well as for the periodic 3883 * stats notifications (after received beacons) from the uCode. 3884 */ 3885 il->handlers[C_STATS] = il4965_hdl_c_stats; 3886 il->handlers[N_STATS] = il4965_hdl_stats; 3887 3888 il_setup_rx_scan_handlers(il); 3889 3890 /* status change handler */ 3891 il->handlers[N_CARD_STATE] = il4965_hdl_card_state; 3892 3893 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon; 3894 /* Rx handlers */ 3895 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy; 3896 il->handlers[N_RX_MPDU] = il4965_hdl_rx; 3897 /* block ack */ 3898 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba; 3899 /* Set up hardware specific Rx handlers */ 3900 il->cfg->ops->lib->handler_setup(il); 3901} 3902 3903/** 3904 * il4965_rx_handle - Main entry function for receiving responses from uCode 3905 * 3906 * Uses the il->handlers callback function array to invoke 3907 * the appropriate handlers, including command responses, 3908 * frame-received notifications, and other notifications. 3909 */ 3910void 3911il4965_rx_handle(struct il_priv *il) 3912{ 3913 struct il_rx_buf *rxb; 3914 struct il_rx_pkt *pkt; 3915 struct il_rx_queue *rxq = &il->rxq; 3916 u32 r, i; 3917 int reclaim; 3918 unsigned long flags; 3919 u8 fill_rx = 0; 3920 u32 count = 8; 3921 int total_empty; 3922 3923 /* uCode's read idx (stored in shared DRAM) indicates the last Rx 3924 * buffer that the driver may process (last buffer filled by ucode). */ 3925 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; 3926 i = rxq->read; 3927 3928 /* Rx interrupt, but nothing sent from uCode */ 3929 if (i == r) 3930 D_RX("r = %d, i = %d\n", r, i); 3931 3932 /* calculate total frames need to be restock after handling RX */ 3933 total_empty = r - rxq->write_actual; 3934 if (total_empty < 0) 3935 total_empty += RX_QUEUE_SIZE; 3936 3937 if (total_empty > (RX_QUEUE_SIZE / 2)) 3938 fill_rx = 1; 3939 3940 while (i != r) { 3941 int len; 3942 3943 rxb = rxq->queue[i]; 3944 3945 /* If an RXB doesn't have a Rx queue slot associated with it, 3946 * then a bug has been introduced in the queue refilling 3947 * routines -- catch it here */ 3948 BUG_ON(rxb == NULL); 3949 3950 rxq->queue[i] = NULL; 3951 3952 pci_unmap_page(il->pci_dev, rxb->page_dma, 3953 PAGE_SIZE << il->hw_params.rx_page_order, 3954 PCI_DMA_FROMDEVICE); 3955 pkt = rxb_addr(rxb); 3956 3957 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK; 3958 len += sizeof(u32); /* account for status word */ 3959 3960 /* Reclaim a command buffer only if this packet is a response 3961 * to a (driver-originated) command. 3962 * If the packet (e.g. Rx frame) originated from uCode, 3963 * there is no command buffer to reclaim. 3964 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 3965 * but apparently a few don't get set; catch them here. */ 3966 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && 3967 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) && 3968 (pkt->hdr.cmd != N_RX_MPDU) && 3969 (pkt->hdr.cmd != N_COMPRESSED_BA) && 3970 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX); 3971 3972 /* Based on type of command response or notification, 3973 * handle those that need handling via function in 3974 * handlers table. See il4965_setup_handlers() */ 3975 if (il->handlers[pkt->hdr.cmd]) { 3976 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i, 3977 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); 3978 il->isr_stats.handlers[pkt->hdr.cmd]++; 3979 il->handlers[pkt->hdr.cmd] (il, rxb); 3980 } else { 3981 /* No handling needed */ 3982 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r, 3983 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); 3984 } 3985 3986 /* 3987 * XXX: After here, we should always check rxb->page 3988 * against NULL before touching it or its virtual 3989 * memory (pkt). Because some handler might have 3990 * already taken or freed the pages. 3991 */ 3992 3993 if (reclaim) { 3994 /* Invoke any callbacks, transfer the buffer to caller, 3995 * and fire off the (possibly) blocking il_send_cmd() 3996 * as we reclaim the driver command queue */ 3997 if (rxb->page) 3998 il_tx_cmd_complete(il, rxb); 3999 else 4000 IL_WARN("Claim null rxb?\n"); 4001 } 4002 4003 /* Reuse the page if possible. For notification packets and 4004 * SKBs that fail to Rx correctly, add them back into the 4005 * rx_free list for reuse later. */ 4006 spin_lock_irqsave(&rxq->lock, flags); 4007 if (rxb->page != NULL) { 4008 rxb->page_dma = 4009 pci_map_page(il->pci_dev, rxb->page, 0, 4010 PAGE_SIZE << il->hw_params. 4011 rx_page_order, PCI_DMA_FROMDEVICE); 4012 list_add_tail(&rxb->list, &rxq->rx_free); 4013 rxq->free_count++; 4014 } else 4015 list_add_tail(&rxb->list, &rxq->rx_used); 4016 4017 spin_unlock_irqrestore(&rxq->lock, flags); 4018 4019 i = (i + 1) & RX_QUEUE_MASK; 4020 /* If there are a lot of unused frames, 4021 * restock the Rx queue so ucode wont assert. */ 4022 if (fill_rx) { 4023 count++; 4024 if (count >= 8) { 4025 rxq->read = i; 4026 il4965_rx_replenish_now(il); 4027 count = 0; 4028 } 4029 } 4030 } 4031 4032 /* Backtrack one entry */ 4033 rxq->read = i; 4034 if (fill_rx) 4035 il4965_rx_replenish_now(il); 4036 else 4037 il4965_rx_queue_restock(il); 4038} 4039 4040/* call this function to flush any scheduled tasklet */ 4041static inline void 4042il4965_synchronize_irq(struct il_priv *il) 4043{ 4044 /* wait to make sure we flush pending tasklet */ 4045 synchronize_irq(il->pci_dev->irq); 4046 tasklet_kill(&il->irq_tasklet); 4047} 4048 4049static void 4050il4965_irq_tasklet(struct il_priv *il) 4051{ 4052 u32 inta, handled = 0; 4053 u32 inta_fh; 4054 unsigned long flags; 4055 u32 i; 4056#ifdef CONFIG_IWLEGACY_DEBUG 4057 u32 inta_mask; 4058#endif 4059 4060 spin_lock_irqsave(&il->lock, flags); 4061 4062 /* Ack/clear/reset pending uCode interrupts. 4063 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 4064 * and will clear only when CSR_FH_INT_STATUS gets cleared. */ 4065 inta = _il_rd(il, CSR_INT); 4066 _il_wr(il, CSR_INT, inta); 4067 4068 /* Ack/clear/reset pending flow-handler (DMA) interrupts. 4069 * Any new interrupts that happen after this, either while we're 4070 * in this tasklet, or later, will show up in next ISR/tasklet. */ 4071 inta_fh = _il_rd(il, CSR_FH_INT_STATUS); 4072 _il_wr(il, CSR_FH_INT_STATUS, inta_fh); 4073 4074#ifdef CONFIG_IWLEGACY_DEBUG 4075 if (il_get_debug_level(il) & IL_DL_ISR) { 4076 /* just for debug */ 4077 inta_mask = _il_rd(il, CSR_INT_MASK); 4078 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, 4079 inta_mask, inta_fh); 4080 } 4081#endif 4082 4083 spin_unlock_irqrestore(&il->lock, flags); 4084 4085 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not 4086 * atomic, make sure that inta covers all the interrupts that 4087 * we've discovered, even if FH interrupt came in just after 4088 * reading CSR_INT. */ 4089 if (inta_fh & CSR49_FH_INT_RX_MASK) 4090 inta |= CSR_INT_BIT_FH_RX; 4091 if (inta_fh & CSR49_FH_INT_TX_MASK) 4092 inta |= CSR_INT_BIT_FH_TX; 4093 4094 /* Now service all interrupt bits discovered above. */ 4095 if (inta & CSR_INT_BIT_HW_ERR) { 4096 IL_ERR("Hardware error detected. Restarting.\n"); 4097 4098 /* Tell the device to stop sending interrupts */ 4099 il_disable_interrupts(il); 4100 4101 il->isr_stats.hw++; 4102 il_irq_handle_error(il); 4103 4104 handled |= CSR_INT_BIT_HW_ERR; 4105 4106 return; 4107 } 4108#ifdef CONFIG_IWLEGACY_DEBUG 4109 if (il_get_debug_level(il) & (IL_DL_ISR)) { 4110 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 4111 if (inta & CSR_INT_BIT_SCD) { 4112 D_ISR("Scheduler finished to transmit " 4113 "the frame/frames.\n"); 4114 il->isr_stats.sch++; 4115 } 4116 4117 /* Alive notification via Rx interrupt will do the real work */ 4118 if (inta & CSR_INT_BIT_ALIVE) { 4119 D_ISR("Alive interrupt\n"); 4120 il->isr_stats.alive++; 4121 } 4122 } 4123#endif 4124 /* Safely ignore these bits for debug checks below */ 4125 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 4126 4127 /* HW RF KILL switch toggled */ 4128 if (inta & CSR_INT_BIT_RF_KILL) { 4129 int hw_rf_kill = 0; 4130 if (! 4131 (_il_rd(il, CSR_GP_CNTRL) & 4132 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 4133 hw_rf_kill = 1; 4134 4135 IL_WARN("RF_KILL bit toggled to %s.\n", 4136 hw_rf_kill ? "disable radio" : "enable radio"); 4137 4138 il->isr_stats.rfkill++; 4139 4140 /* driver only loads ucode once setting the interface up. 4141 * the driver allows loading the ucode even if the radio 4142 * is killed. Hence update the killswitch state here. The 4143 * rfkill handler will care about restarting if needed. 4144 */ 4145 if (!test_bit(S_ALIVE, &il->status)) { 4146 if (hw_rf_kill) 4147 set_bit(S_RF_KILL_HW, &il->status); 4148 else 4149 clear_bit(S_RF_KILL_HW, &il->status); 4150 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill); 4151 } 4152 4153 handled |= CSR_INT_BIT_RF_KILL; 4154 } 4155 4156 /* Chip got too hot and stopped itself */ 4157 if (inta & CSR_INT_BIT_CT_KILL) { 4158 IL_ERR("Microcode CT kill error detected.\n"); 4159 il->isr_stats.ctkill++; 4160 handled |= CSR_INT_BIT_CT_KILL; 4161 } 4162 4163 /* Error detected by uCode */ 4164 if (inta & CSR_INT_BIT_SW_ERR) { 4165 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n", 4166 inta); 4167 il->isr_stats.sw++; 4168 il_irq_handle_error(il); 4169 handled |= CSR_INT_BIT_SW_ERR; 4170 } 4171 4172 /* 4173 * uCode wakes up after power-down sleep. 4174 * Tell device about any new tx or host commands enqueued, 4175 * and about any Rx buffers made available while asleep. 4176 */ 4177 if (inta & CSR_INT_BIT_WAKEUP) { 4178 D_ISR("Wakeup interrupt\n"); 4179 il_rx_queue_update_write_ptr(il, &il->rxq); 4180 for (i = 0; i < il->hw_params.max_txq_num; i++) 4181 il_txq_update_write_ptr(il, &il->txq[i]); 4182 il->isr_stats.wakeup++; 4183 handled |= CSR_INT_BIT_WAKEUP; 4184 } 4185 4186 /* All uCode command responses, including Tx command responses, 4187 * Rx "responses" (frame-received notification), and other 4188 * notifications from uCode come through here*/ 4189 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 4190 il4965_rx_handle(il); 4191 il->isr_stats.rx++; 4192 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 4193 } 4194 4195 /* This "Tx" DMA channel is used only for loading uCode */ 4196 if (inta & CSR_INT_BIT_FH_TX) { 4197 D_ISR("uCode load interrupt\n"); 4198 il->isr_stats.tx++; 4199 handled |= CSR_INT_BIT_FH_TX; 4200 /* Wake up uCode load routine, now that load is complete */ 4201 il->ucode_write_complete = 1; 4202 wake_up(&il->wait_command_queue); 4203 } 4204 4205 if (inta & ~handled) { 4206 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled); 4207 il->isr_stats.unhandled++; 4208 } 4209 4210 if (inta & ~(il->inta_mask)) { 4211 IL_WARN("Disabled INTA bits 0x%08x were pending\n", 4212 inta & ~il->inta_mask); 4213 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh); 4214 } 4215 4216 /* Re-enable all interrupts */ 4217 /* only Re-enable if disabled by irq */ 4218 if (test_bit(S_INT_ENABLED, &il->status)) 4219 il_enable_interrupts(il); 4220 /* Re-enable RF_KILL if it occurred */ 4221 else if (handled & CSR_INT_BIT_RF_KILL) 4222 il_enable_rfkill_int(il); 4223 4224#ifdef CONFIG_IWLEGACY_DEBUG 4225 if (il_get_debug_level(il) & (IL_DL_ISR)) { 4226 inta = _il_rd(il, CSR_INT); 4227 inta_mask = _il_rd(il, CSR_INT_MASK); 4228 inta_fh = _il_rd(il, CSR_FH_INT_STATUS); 4229 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " 4230 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); 4231 } 4232#endif 4233} 4234 4235/***************************************************************************** 4236 * 4237 * sysfs attributes 4238 * 4239 *****************************************************************************/ 4240 4241#ifdef CONFIG_IWLEGACY_DEBUG 4242 4243/* 4244 * The following adds a new attribute to the sysfs representation 4245 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) 4246 * used for controlling the debug level. 4247 * 4248 * See the level definitions in iwl for details. 4249 * 4250 * The debug_level being managed using sysfs below is a per device debug 4251 * level that is used instead of the global debug level if it (the per 4252 * device debug level) is set. 4253 */ 4254static ssize_t 4255il4965_show_debug_level(struct device *d, struct device_attribute *attr, 4256 char *buf) 4257{ 4258 struct il_priv *il = dev_get_drvdata(d); 4259 return sprintf(buf, "0x%08X\n", il_get_debug_level(il)); 4260} 4261 4262static ssize_t 4263il4965_store_debug_level(struct device *d, struct device_attribute *attr, 4264 const char *buf, size_t count) 4265{ 4266 struct il_priv *il = dev_get_drvdata(d); 4267 unsigned long val; 4268 int ret; 4269 4270 ret = strict_strtoul(buf, 0, &val); 4271 if (ret) 4272 IL_ERR("%s is not in hex or decimal form.\n", buf); 4273 else { 4274 il->debug_level = val; 4275 if (il_alloc_traffic_mem(il)) 4276 IL_ERR("Not enough memory to generate traffic log\n"); 4277 } 4278 return strnlen(buf, count); 4279} 4280 4281static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level, 4282 il4965_store_debug_level); 4283 4284#endif /* CONFIG_IWLEGACY_DEBUG */ 4285 4286static ssize_t 4287il4965_show_temperature(struct device *d, struct device_attribute *attr, 4288 char *buf) 4289{ 4290 struct il_priv *il = dev_get_drvdata(d); 4291 4292 if (!il_is_alive(il)) 4293 return -EAGAIN; 4294 4295 return sprintf(buf, "%d\n", il->temperature); 4296} 4297 4298static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL); 4299 4300static ssize_t 4301il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf) 4302{ 4303 struct il_priv *il = dev_get_drvdata(d); 4304 4305 if (!il_is_ready_rf(il)) 4306 return sprintf(buf, "off\n"); 4307 else 4308 return sprintf(buf, "%d\n", il->tx_power_user_lmt); 4309} 4310 4311static ssize_t 4312il4965_store_tx_power(struct device *d, struct device_attribute *attr, 4313 const char *buf, size_t count) 4314{ 4315 struct il_priv *il = dev_get_drvdata(d); 4316 unsigned long val; 4317 int ret; 4318 4319 ret = strict_strtoul(buf, 10, &val); 4320 if (ret) 4321 IL_INFO("%s is not in decimal form.\n", buf); 4322 else { 4323 ret = il_set_tx_power(il, val, false); 4324 if (ret) 4325 IL_ERR("failed setting tx power (0x%d).\n", ret); 4326 else 4327 ret = count; 4328 } 4329 return ret; 4330} 4331 4332static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power, 4333 il4965_store_tx_power); 4334 4335static struct attribute *il_sysfs_entries[] = { 4336 &dev_attr_temperature.attr, 4337 &dev_attr_tx_power.attr, 4338#ifdef CONFIG_IWLEGACY_DEBUG 4339 &dev_attr_debug_level.attr, 4340#endif 4341 NULL 4342}; 4343 4344static struct attribute_group il_attribute_group = { 4345 .name = NULL, /* put in device directory */ 4346 .attrs = il_sysfs_entries, 4347}; 4348 4349/****************************************************************************** 4350 * 4351 * uCode download functions 4352 * 4353 ******************************************************************************/ 4354 4355static void 4356il4965_dealloc_ucode_pci(struct il_priv *il) 4357{ 4358 il_free_fw_desc(il->pci_dev, &il->ucode_code); 4359 il_free_fw_desc(il->pci_dev, &il->ucode_data); 4360 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup); 4361 il_free_fw_desc(il->pci_dev, &il->ucode_init); 4362 il_free_fw_desc(il->pci_dev, &il->ucode_init_data); 4363 il_free_fw_desc(il->pci_dev, &il->ucode_boot); 4364} 4365 4366static void 4367il4965_nic_start(struct il_priv *il) 4368{ 4369 /* Remove all resets to allow NIC to operate */ 4370 _il_wr(il, CSR_RESET, 0); 4371} 4372 4373static void il4965_ucode_callback(const struct firmware *ucode_raw, 4374 void *context); 4375static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length); 4376 4377static int __must_check 4378il4965_request_firmware(struct il_priv *il, bool first) 4379{ 4380 const char *name_pre = il->cfg->fw_name_pre; 4381 char tag[8]; 4382 4383 if (first) { 4384 il->fw_idx = il->cfg->ucode_api_max; 4385 sprintf(tag, "%d", il->fw_idx); 4386 } else { 4387 il->fw_idx--; 4388 sprintf(tag, "%d", il->fw_idx); 4389 } 4390 4391 if (il->fw_idx < il->cfg->ucode_api_min) { 4392 IL_ERR("no suitable firmware found!\n"); 4393 return -ENOENT; 4394 } 4395 4396 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); 4397 4398 D_INFO("attempting to load firmware '%s'\n", il->firmware_name); 4399 4400 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name, 4401 &il->pci_dev->dev, GFP_KERNEL, il, 4402 il4965_ucode_callback); 4403} 4404 4405struct il4965_firmware_pieces { 4406 const void *inst, *data, *init, *init_data, *boot; 4407 size_t inst_size, data_size, init_size, init_data_size, boot_size; 4408}; 4409 4410static int 4411il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw, 4412 struct il4965_firmware_pieces *pieces) 4413{ 4414 struct il_ucode_header *ucode = (void *)ucode_raw->data; 4415 u32 api_ver, hdr_size; 4416 const u8 *src; 4417 4418 il->ucode_ver = le32_to_cpu(ucode->ver); 4419 api_ver = IL_UCODE_API(il->ucode_ver); 4420 4421 switch (api_ver) { 4422 default: 4423 case 0: 4424 case 1: 4425 case 2: 4426 hdr_size = 24; 4427 if (ucode_raw->size < hdr_size) { 4428 IL_ERR("File size too small!\n"); 4429 return -EINVAL; 4430 } 4431 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size); 4432 pieces->data_size = le32_to_cpu(ucode->v1.data_size); 4433 pieces->init_size = le32_to_cpu(ucode->v1.init_size); 4434 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size); 4435 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size); 4436 src = ucode->v1.data; 4437 break; 4438 } 4439 4440 /* Verify size of file vs. image size info in file's header */ 4441 if (ucode_raw->size != 4442 hdr_size + pieces->inst_size + pieces->data_size + 4443 pieces->init_size + pieces->init_data_size + pieces->boot_size) { 4444 4445 IL_ERR("uCode file size %d does not match expected size\n", 4446 (int)ucode_raw->size); 4447 return -EINVAL; 4448 } 4449 4450 pieces->inst = src; 4451 src += pieces->inst_size; 4452 pieces->data = src; 4453 src += pieces->data_size; 4454 pieces->init = src; 4455 src += pieces->init_size; 4456 pieces->init_data = src; 4457 src += pieces->init_data_size; 4458 pieces->boot = src; 4459 src += pieces->boot_size; 4460 4461 return 0; 4462} 4463 4464/** 4465 * il4965_ucode_callback - callback when firmware was loaded 4466 * 4467 * If loaded successfully, copies the firmware into buffers 4468 * for the card to fetch (via DMA). 4469 */ 4470static void 4471il4965_ucode_callback(const struct firmware *ucode_raw, void *context) 4472{ 4473 struct il_priv *il = context; 4474 struct il_ucode_header *ucode; 4475 int err; 4476 struct il4965_firmware_pieces pieces; 4477 const unsigned int api_max = il->cfg->ucode_api_max; 4478 const unsigned int api_min = il->cfg->ucode_api_min; 4479 u32 api_ver; 4480 4481 u32 max_probe_length = 200; 4482 u32 standard_phy_calibration_size = 4483 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE; 4484 4485 memset(&pieces, 0, sizeof(pieces)); 4486 4487 if (!ucode_raw) { 4488 if (il->fw_idx <= il->cfg->ucode_api_max) 4489 IL_ERR("request for firmware file '%s' failed.\n", 4490 il->firmware_name); 4491 goto try_again; 4492 } 4493 4494 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name, 4495 ucode_raw->size); 4496 4497 /* Make sure that we got at least the API version number */ 4498 if (ucode_raw->size < 4) { 4499 IL_ERR("File size way too small!\n"); 4500 goto try_again; 4501 } 4502 4503 /* Data from ucode file: header followed by uCode images */ 4504 ucode = (struct il_ucode_header *)ucode_raw->data; 4505 4506 err = il4965_load_firmware(il, ucode_raw, &pieces); 4507 4508 if (err) 4509 goto try_again; 4510 4511 api_ver = IL_UCODE_API(il->ucode_ver); 4512 4513 /* 4514 * api_ver should match the api version forming part of the 4515 * firmware filename ... but we don't check for that and only rely 4516 * on the API version read from firmware header from here on forward 4517 */ 4518 if (api_ver < api_min || api_ver > api_max) { 4519 IL_ERR("Driver unable to support your firmware API. " 4520 "Driver supports v%u, firmware is v%u.\n", api_max, 4521 api_ver); 4522 goto try_again; 4523 } 4524 4525 if (api_ver != api_max) 4526 IL_ERR("Firmware has old API version. Expected v%u, " 4527 "got v%u. New firmware can be obtained " 4528 "from http://www.intellinuxwireless.org.\n", api_max, 4529 api_ver); 4530 4531 IL_INFO("loaded firmware version %u.%u.%u.%u\n", 4532 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver), 4533 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver)); 4534 4535 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version), 4536 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver), 4537 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver), 4538 IL_UCODE_SERIAL(il->ucode_ver)); 4539 4540 /* 4541 * For any of the failures below (before allocating pci memory) 4542 * we will try to load a version with a smaller API -- maybe the 4543 * user just got a corrupted version of the latest API. 4544 */ 4545 4546 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver); 4547 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size); 4548 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size); 4549 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size); 4550 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size); 4551 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size); 4552 4553 /* Verify that uCode images will fit in card's SRAM */ 4554 if (pieces.inst_size > il->hw_params.max_inst_size) { 4555 IL_ERR("uCode instr len %Zd too large to fit in\n", 4556 pieces.inst_size); 4557 goto try_again; 4558 } 4559 4560 if (pieces.data_size > il->hw_params.max_data_size) { 4561 IL_ERR("uCode data len %Zd too large to fit in\n", 4562 pieces.data_size); 4563 goto try_again; 4564 } 4565 4566 if (pieces.init_size > il->hw_params.max_inst_size) { 4567 IL_ERR("uCode init instr len %Zd too large to fit in\n", 4568 pieces.init_size); 4569 goto try_again; 4570 } 4571 4572 if (pieces.init_data_size > il->hw_params.max_data_size) { 4573 IL_ERR("uCode init data len %Zd too large to fit in\n", 4574 pieces.init_data_size); 4575 goto try_again; 4576 } 4577 4578 if (pieces.boot_size > il->hw_params.max_bsm_size) { 4579 IL_ERR("uCode boot instr len %Zd too large to fit in\n", 4580 pieces.boot_size); 4581 goto try_again; 4582 } 4583 4584 /* Allocate ucode buffers for card's bus-master loading ... */ 4585 4586 /* Runtime instructions and 2 copies of data: 4587 * 1) unmodified from disk 4588 * 2) backup cache for save/restore during power-downs */ 4589 il->ucode_code.len = pieces.inst_size; 4590 il_alloc_fw_desc(il->pci_dev, &il->ucode_code); 4591 4592 il->ucode_data.len = pieces.data_size; 4593 il_alloc_fw_desc(il->pci_dev, &il->ucode_data); 4594 4595 il->ucode_data_backup.len = pieces.data_size; 4596 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup); 4597 4598 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr || 4599 !il->ucode_data_backup.v_addr) 4600 goto err_pci_alloc; 4601 4602 /* Initialization instructions and data */ 4603 if (pieces.init_size && pieces.init_data_size) { 4604 il->ucode_init.len = pieces.init_size; 4605 il_alloc_fw_desc(il->pci_dev, &il->ucode_init); 4606 4607 il->ucode_init_data.len = pieces.init_data_size; 4608 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data); 4609 4610 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr) 4611 goto err_pci_alloc; 4612 } 4613 4614 /* Bootstrap (instructions only, no data) */ 4615 if (pieces.boot_size) { 4616 il->ucode_boot.len = pieces.boot_size; 4617 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot); 4618 4619 if (!il->ucode_boot.v_addr) 4620 goto err_pci_alloc; 4621 } 4622 4623 /* Now that we can no longer fail, copy information */ 4624 4625 il->sta_key_max_num = STA_KEY_MAX_NUM; 4626 4627 /* Copy images into buffers for card's bus-master reads ... */ 4628 4629 /* Runtime instructions (first block of data in file) */ 4630 D_INFO("Copying (but not loading) uCode instr len %Zd\n", 4631 pieces.inst_size); 4632 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size); 4633 4634 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", 4635 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr); 4636 4637 /* 4638 * Runtime data 4639 * NOTE: Copy into backup buffer will be done in il_up() 4640 */ 4641 D_INFO("Copying (but not loading) uCode data len %Zd\n", 4642 pieces.data_size); 4643 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size); 4644 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size); 4645 4646 /* Initialization instructions */ 4647 if (pieces.init_size) { 4648 D_INFO("Copying (but not loading) init instr len %Zd\n", 4649 pieces.init_size); 4650 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size); 4651 } 4652 4653 /* Initialization data */ 4654 if (pieces.init_data_size) { 4655 D_INFO("Copying (but not loading) init data len %Zd\n", 4656 pieces.init_data_size); 4657 memcpy(il->ucode_init_data.v_addr, pieces.init_data, 4658 pieces.init_data_size); 4659 } 4660 4661 /* Bootstrap instructions */ 4662 D_INFO("Copying (but not loading) boot instr len %Zd\n", 4663 pieces.boot_size); 4664 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size); 4665 4666 /* 4667 * figure out the offset of chain noise reset and gain commands 4668 * base on the size of standard phy calibration commands table size 4669 */ 4670 il->_4965.phy_calib_chain_noise_reset_cmd = 4671 standard_phy_calibration_size; 4672 il->_4965.phy_calib_chain_noise_gain_cmd = 4673 standard_phy_calibration_size + 1; 4674 4675 /************************************************** 4676 * This is still part of probe() in a sense... 4677 * 4678 * 9. Setup and register with mac80211 and debugfs 4679 **************************************************/ 4680 err = il4965_mac_setup_register(il, max_probe_length); 4681 if (err) 4682 goto out_unbind; 4683 4684 err = il_dbgfs_register(il, DRV_NAME); 4685 if (err) 4686 IL_ERR("failed to create debugfs files. Ignoring error: %d\n", 4687 err); 4688 4689 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group); 4690 if (err) { 4691 IL_ERR("failed to create sysfs device attributes\n"); 4692 goto out_unbind; 4693 } 4694 4695 /* We have our copies now, allow OS release its copies */ 4696 release_firmware(ucode_raw); 4697 complete(&il->_4965.firmware_loading_complete); 4698 return; 4699 4700try_again: 4701 /* try next, if any */ 4702 if (il4965_request_firmware(il, false)) 4703 goto out_unbind; 4704 release_firmware(ucode_raw); 4705 return; 4706 4707err_pci_alloc: 4708 IL_ERR("failed to allocate pci memory\n"); 4709 il4965_dealloc_ucode_pci(il); 4710out_unbind: 4711 complete(&il->_4965.firmware_loading_complete); 4712 device_release_driver(&il->pci_dev->dev); 4713 release_firmware(ucode_raw); 4714} 4715 4716static const char *const desc_lookup_text[] = { 4717 "OK", 4718 "FAIL", 4719 "BAD_PARAM", 4720 "BAD_CHECKSUM", 4721 "NMI_INTERRUPT_WDG", 4722 "SYSASSERT", 4723 "FATAL_ERROR", 4724 "BAD_COMMAND", 4725 "HW_ERROR_TUNE_LOCK", 4726 "HW_ERROR_TEMPERATURE", 4727 "ILLEGAL_CHAN_FREQ", 4728 "VCC_NOT_STBL", 4729 "FH49_ERROR", 4730 "NMI_INTERRUPT_HOST", 4731 "NMI_INTERRUPT_ACTION_PT", 4732 "NMI_INTERRUPT_UNKNOWN", 4733 "UCODE_VERSION_MISMATCH", 4734 "HW_ERROR_ABS_LOCK", 4735 "HW_ERROR_CAL_LOCK_FAIL", 4736 "NMI_INTERRUPT_INST_ACTION_PT", 4737 "NMI_INTERRUPT_DATA_ACTION_PT", 4738 "NMI_TRM_HW_ER", 4739 "NMI_INTERRUPT_TRM", 4740 "NMI_INTERRUPT_BREAK_POINT", 4741 "DEBUG_0", 4742 "DEBUG_1", 4743 "DEBUG_2", 4744 "DEBUG_3", 4745}; 4746 4747static struct { 4748 char *name; 4749 u8 num; 4750} advanced_lookup[] = { 4751 { 4752 "NMI_INTERRUPT_WDG", 0x34}, { 4753 "SYSASSERT", 0x35}, { 4754 "UCODE_VERSION_MISMATCH", 0x37}, { 4755 "BAD_COMMAND", 0x38}, { 4756 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, { 4757 "FATAL_ERROR", 0x3D}, { 4758 "NMI_TRM_HW_ERR", 0x46}, { 4759 "NMI_INTERRUPT_TRM", 0x4C}, { 4760 "NMI_INTERRUPT_BREAK_POINT", 0x54}, { 4761 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, { 4762 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, { 4763 "NMI_INTERRUPT_HOST", 0x66}, { 4764 "NMI_INTERRUPT_ACTION_PT", 0x7C}, { 4765 "NMI_INTERRUPT_UNKNOWN", 0x84}, { 4766 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, { 4767"ADVANCED_SYSASSERT", 0},}; 4768 4769static const char * 4770il4965_desc_lookup(u32 num) 4771{ 4772 int i; 4773 int max = ARRAY_SIZE(desc_lookup_text); 4774 4775 if (num < max) 4776 return desc_lookup_text[num]; 4777 4778 max = ARRAY_SIZE(advanced_lookup) - 1; 4779 for (i = 0; i < max; i++) { 4780 if (advanced_lookup[i].num == num) 4781 break; 4782 } 4783 return advanced_lookup[i].name; 4784} 4785 4786#define ERROR_START_OFFSET (1 * sizeof(u32)) 4787#define ERROR_ELEM_SIZE (7 * sizeof(u32)) 4788 4789void 4790il4965_dump_nic_error_log(struct il_priv *il) 4791{ 4792 u32 data2, line; 4793 u32 desc, time, count, base, data1; 4794 u32 blink1, blink2, ilink1, ilink2; 4795 u32 pc, hcmd; 4796 4797 if (il->ucode_type == UCODE_INIT) 4798 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr); 4799 else 4800 base = le32_to_cpu(il->card_alive.error_event_table_ptr); 4801 4802 if (!il->cfg->ops->lib->is_valid_rtc_data_addr(base)) { 4803 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n", 4804 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT"); 4805 return; 4806 } 4807 4808 count = il_read_targ_mem(il, base); 4809 4810 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { 4811 IL_ERR("Start IWL Error Log Dump:\n"); 4812 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count); 4813 } 4814 4815 desc = il_read_targ_mem(il, base + 1 * sizeof(u32)); 4816 il->isr_stats.err_code = desc; 4817 pc = il_read_targ_mem(il, base + 2 * sizeof(u32)); 4818 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32)); 4819 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32)); 4820 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32)); 4821 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32)); 4822 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32)); 4823 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32)); 4824 line = il_read_targ_mem(il, base + 9 * sizeof(u32)); 4825 time = il_read_targ_mem(il, base + 11 * sizeof(u32)); 4826 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32)); 4827 4828 IL_ERR("Desc Time " 4829 "data1 data2 line\n"); 4830 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", 4831 il4965_desc_lookup(desc), desc, time, data1, data2, line); 4832 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n"); 4833 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1, 4834 blink2, ilink1, ilink2, hcmd); 4835} 4836 4837static void 4838il4965_rf_kill_ct_config(struct il_priv *il) 4839{ 4840 struct il_ct_kill_config cmd; 4841 unsigned long flags; 4842 int ret = 0; 4843 4844 spin_lock_irqsave(&il->lock, flags); 4845 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, 4846 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 4847 spin_unlock_irqrestore(&il->lock, flags); 4848 4849 cmd.critical_temperature_R = 4850 cpu_to_le32(il->hw_params.ct_kill_threshold); 4851 4852 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd); 4853 if (ret) 4854 IL_ERR("C_CT_KILL_CONFIG failed\n"); 4855 else 4856 D_INFO("C_CT_KILL_CONFIG " "succeeded, " 4857 "critical temperature is %d\n", 4858 il->hw_params.ct_kill_threshold); 4859} 4860 4861static const s8 default_queue_to_tx_fifo[] = { 4862 IL_TX_FIFO_VO, 4863 IL_TX_FIFO_VI, 4864 IL_TX_FIFO_BE, 4865 IL_TX_FIFO_BK, 4866 IL49_CMD_FIFO_NUM, 4867 IL_TX_FIFO_UNUSED, 4868 IL_TX_FIFO_UNUSED, 4869}; 4870 4871#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 4872 4873static int 4874il4965_alive_notify(struct il_priv *il) 4875{ 4876 u32 a; 4877 unsigned long flags; 4878 int i, chan; 4879 u32 reg_val; 4880 4881 spin_lock_irqsave(&il->lock, flags); 4882 4883 /* Clear 4965's internal Tx Scheduler data base */ 4884 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR); 4885 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET; 4886 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4) 4887 il_write_targ_mem(il, a, 0); 4888 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4) 4889 il_write_targ_mem(il, a, 0); 4890 for (; 4891 a < 4892 il->scd_base_addr + 4893 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); 4894 a += 4) 4895 il_write_targ_mem(il, a, 0); 4896 4897 /* Tel 4965 where to find Tx byte count tables */ 4898 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10); 4899 4900 /* Enable DMA channel */ 4901 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++) 4902 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan), 4903 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 4904 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 4905 4906 /* Update FH chicken bits */ 4907 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG); 4908 il_wr(il, FH49_TX_CHICKEN_BITS_REG, 4909 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 4910 4911 /* Disable chain mode for all queues */ 4912 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0); 4913 4914 /* Initialize each Tx queue (including the command queue) */ 4915 for (i = 0; i < il->hw_params.max_txq_num; i++) { 4916 4917 /* TFD circular buffer read/write idxes */ 4918 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0); 4919 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8)); 4920 4921 /* Max Tx Window size for Scheduler-ACK mode */ 4922 il_write_targ_mem(il, 4923 il->scd_base_addr + 4924 IL49_SCD_CONTEXT_QUEUE_OFFSET(i), 4925 (SCD_WIN_SIZE << 4926 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 4927 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 4928 4929 /* Frame limit */ 4930 il_write_targ_mem(il, 4931 il->scd_base_addr + 4932 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) + 4933 sizeof(u32), 4934 (SCD_FRAME_LIMIT << 4935 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 4936 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 4937 4938 } 4939 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK, 4940 (1 << il->hw_params.max_txq_num) - 1); 4941 4942 /* Activate all Tx DMA/FIFO channels */ 4943 il4965_txq_set_sched(il, IL_MASK(0, 6)); 4944 4945 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0); 4946 4947 /* make sure all queue are not stopped */ 4948 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped)); 4949 for (i = 0; i < 4; i++) 4950 atomic_set(&il->queue_stop_count[i], 0); 4951 4952 /* reset to 0 to enable all the queue first */ 4953 il->txq_ctx_active_msk = 0; 4954 /* Map each Tx/cmd queue to its corresponding fifo */ 4955 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7); 4956 4957 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { 4958 int ac = default_queue_to_tx_fifo[i]; 4959 4960 il_txq_ctx_activate(il, i); 4961 4962 if (ac == IL_TX_FIFO_UNUSED) 4963 continue; 4964 4965 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0); 4966 } 4967 4968 spin_unlock_irqrestore(&il->lock, flags); 4969 4970 return 0; 4971} 4972 4973/** 4974 * il4965_alive_start - called after N_ALIVE notification received 4975 * from protocol/runtime uCode (initialization uCode's 4976 * Alive gets handled by il_init_alive_start()). 4977 */ 4978static void 4979il4965_alive_start(struct il_priv *il) 4980{ 4981 int ret = 0; 4982 struct il_rxon_context *ctx = &il->ctx; 4983 4984 D_INFO("Runtime Alive received.\n"); 4985 4986 if (il->card_alive.is_valid != UCODE_VALID_OK) { 4987 /* We had an error bringing up the hardware, so take it 4988 * all the way back down so we can try again */ 4989 D_INFO("Alive failed.\n"); 4990 goto restart; 4991 } 4992 4993 /* Initialize uCode has loaded Runtime uCode ... verify inst image. 4994 * This is a paranoid check, because we would not have gotten the 4995 * "runtime" alive if code weren't properly loaded. */ 4996 if (il4965_verify_ucode(il)) { 4997 /* Runtime instruction load was bad; 4998 * take it all the way back down so we can try again */ 4999 D_INFO("Bad runtime uCode load.\n"); 5000 goto restart; 5001 } 5002 5003 ret = il4965_alive_notify(il); 5004 if (ret) { 5005 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret); 5006 goto restart; 5007 } 5008 5009 /* After the ALIVE response, we can send host commands to the uCode */ 5010 set_bit(S_ALIVE, &il->status); 5011 5012 /* Enable watchdog to monitor the driver tx queues */ 5013 il_setup_watchdog(il); 5014 5015 if (il_is_rfkill(il)) 5016 return; 5017 5018 ieee80211_wake_queues(il->hw); 5019 5020 il->active_rate = RATES_MASK; 5021 5022 if (il_is_associated_ctx(ctx)) { 5023 struct il_rxon_cmd *active_rxon = 5024 (struct il_rxon_cmd *)&ctx->active; 5025 /* apply any changes in staging */ 5026 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; 5027 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 5028 } else { 5029 /* Initialize our rx_config data */ 5030 il_connection_init_rx_config(il, &il->ctx); 5031 5032 if (il->cfg->ops->hcmd->set_rxon_chain) 5033 il->cfg->ops->hcmd->set_rxon_chain(il, ctx); 5034 } 5035 5036 /* Configure bluetooth coexistence if enabled */ 5037 il_send_bt_config(il); 5038 5039 il4965_reset_run_time_calib(il); 5040 5041 set_bit(S_READY, &il->status); 5042 5043 /* Configure the adapter for unassociated operation */ 5044 il_commit_rxon(il, ctx); 5045 5046 /* At this point, the NIC is initialized and operational */ 5047 il4965_rf_kill_ct_config(il); 5048 5049 D_INFO("ALIVE processing complete.\n"); 5050 wake_up(&il->wait_command_queue); 5051 5052 il_power_update_mode(il, true); 5053 D_INFO("Updated power mode\n"); 5054 5055 return; 5056 5057restart: 5058 queue_work(il->workqueue, &il->restart); 5059} 5060 5061static void il4965_cancel_deferred_work(struct il_priv *il); 5062 5063static void 5064__il4965_down(struct il_priv *il) 5065{ 5066 unsigned long flags; 5067 int exit_pending; 5068 5069 D_INFO(DRV_NAME " is going down\n"); 5070 5071 il_scan_cancel_timeout(il, 200); 5072 5073 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status); 5074 5075 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set 5076 * to prevent rearm timer */ 5077 del_timer_sync(&il->watchdog); 5078 5079 il_clear_ucode_stations(il, NULL); 5080 il_dealloc_bcast_stations(il); 5081 il_clear_driver_stations(il); 5082 5083 /* Unblock any waiting calls */ 5084 wake_up_all(&il->wait_command_queue); 5085 5086 /* Wipe out the EXIT_PENDING status bit if we are not actually 5087 * exiting the module */ 5088 if (!exit_pending) 5089 clear_bit(S_EXIT_PENDING, &il->status); 5090 5091 /* stop and reset the on-board processor */ 5092 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 5093 5094 /* tell the device to stop sending interrupts */ 5095 spin_lock_irqsave(&il->lock, flags); 5096 il_disable_interrupts(il); 5097 spin_unlock_irqrestore(&il->lock, flags); 5098 il4965_synchronize_irq(il); 5099 5100 if (il->mac80211_registered) 5101 ieee80211_stop_queues(il->hw); 5102 5103 /* If we have not previously called il_init() then 5104 * clear all bits but the RF Kill bit and return */ 5105 if (!il_is_init(il)) { 5106 il->status = 5107 test_bit(S_RF_KILL_HW, 5108 &il-> 5109 status) << S_RF_KILL_HW | 5110 test_bit(S_GEO_CONFIGURED, 5111 &il-> 5112 status) << S_GEO_CONFIGURED | 5113 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; 5114 goto exit; 5115 } 5116 5117 /* ...otherwise clear out all the status bits but the RF Kill 5118 * bit and continue taking the NIC down. */ 5119 il->status &= 5120 test_bit(S_RF_KILL_HW, 5121 &il->status) << S_RF_KILL_HW | test_bit(S_GEO_CONFIGURED, 5122 &il-> 5123 status) << 5124 S_GEO_CONFIGURED | test_bit(S_FW_ERROR, 5125 &il-> 5126 status) << S_FW_ERROR | 5127 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; 5128 5129 il4965_txq_ctx_stop(il); 5130 il4965_rxq_stop(il); 5131 5132 /* Power-down device's busmaster DMA clocks */ 5133 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); 5134 udelay(5); 5135 5136 /* Make sure (redundant) we've released our request to stay awake */ 5137 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 5138 5139 /* Stop the device, and put it in low power state */ 5140 il_apm_stop(il); 5141 5142exit: 5143 memset(&il->card_alive, 0, sizeof(struct il_alive_resp)); 5144 5145 dev_kfree_skb(il->beacon_skb); 5146 il->beacon_skb = NULL; 5147 5148 /* clear out any free frames */ 5149 il4965_clear_free_frames(il); 5150} 5151 5152static void 5153il4965_down(struct il_priv *il) 5154{ 5155 mutex_lock(&il->mutex); 5156 __il4965_down(il); 5157 mutex_unlock(&il->mutex); 5158 5159 il4965_cancel_deferred_work(il); 5160} 5161 5162#define HW_READY_TIMEOUT (50) 5163 5164static int 5165il4965_set_hw_ready(struct il_priv *il) 5166{ 5167 int ret = 0; 5168 5169 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 5170 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 5171 5172 /* See if we got it */ 5173 ret = 5174 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, 5175 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 5176 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, HW_READY_TIMEOUT); 5177 if (ret != -ETIMEDOUT) 5178 il->hw_ready = true; 5179 else 5180 il->hw_ready = false; 5181 5182 D_INFO("hardware %s\n", (il->hw_ready == 1) ? "ready" : "not ready"); 5183 return ret; 5184} 5185 5186static int 5187il4965_prepare_card_hw(struct il_priv *il) 5188{ 5189 int ret = 0; 5190 5191 D_INFO("il4965_prepare_card_hw enter\n"); 5192 5193 ret = il4965_set_hw_ready(il); 5194 if (il->hw_ready) 5195 return ret; 5196 5197 /* If HW is not ready, prepare the conditions to check again */ 5198 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE); 5199 5200 ret = 5201 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, 5202 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 5203 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); 5204 5205 /* HW should be ready by now, check again. */ 5206 if (ret != -ETIMEDOUT) 5207 il4965_set_hw_ready(il); 5208 5209 return ret; 5210} 5211 5212#define MAX_HW_RESTARTS 5 5213 5214static int 5215__il4965_up(struct il_priv *il) 5216{ 5217 int i; 5218 int ret; 5219 5220 if (test_bit(S_EXIT_PENDING, &il->status)) { 5221 IL_WARN("Exit pending; will not bring the NIC up\n"); 5222 return -EIO; 5223 } 5224 5225 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) { 5226 IL_ERR("ucode not available for device bringup\n"); 5227 return -EIO; 5228 } 5229 5230 ret = il4965_alloc_bcast_station(il, &il->ctx); 5231 if (ret) { 5232 il_dealloc_bcast_stations(il); 5233 return ret; 5234 } 5235 5236 il4965_prepare_card_hw(il); 5237 5238 if (!il->hw_ready) { 5239 IL_WARN("Exit HW not ready\n"); 5240 return -EIO; 5241 } 5242 5243 /* If platform's RF_KILL switch is NOT set to KILL */ 5244 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 5245 clear_bit(S_RF_KILL_HW, &il->status); 5246 else 5247 set_bit(S_RF_KILL_HW, &il->status); 5248 5249 if (il_is_rfkill(il)) { 5250 wiphy_rfkill_set_hw_state(il->hw->wiphy, true); 5251 5252 il_enable_interrupts(il); 5253 IL_WARN("Radio disabled by HW RF Kill switch\n"); 5254 return 0; 5255 } 5256 5257 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5258 5259 /* must be initialised before il_hw_nic_init */ 5260 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM; 5261 5262 ret = il4965_hw_nic_init(il); 5263 if (ret) { 5264 IL_ERR("Unable to init nic\n"); 5265 return ret; 5266 } 5267 5268 /* make sure rfkill handshake bits are cleared */ 5269 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5270 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 5271 5272 /* clear (again), then enable host interrupts */ 5273 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5274 il_enable_interrupts(il); 5275 5276 /* really make sure rfkill handshake bits are cleared */ 5277 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5278 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5279 5280 /* Copy original ucode data image from disk into backup cache. 5281 * This will be used to initialize the on-board processor's 5282 * data SRAM for a clean start when the runtime program first loads. */ 5283 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr, 5284 il->ucode_data.len); 5285 5286 for (i = 0; i < MAX_HW_RESTARTS; i++) { 5287 5288 /* load bootstrap state machine, 5289 * load bootstrap program into processor's memory, 5290 * prepare to load the "initialize" uCode */ 5291 ret = il->cfg->ops->lib->load_ucode(il); 5292 5293 if (ret) { 5294 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret); 5295 continue; 5296 } 5297 5298 /* start card; "initialize" will load runtime ucode */ 5299 il4965_nic_start(il); 5300 5301 D_INFO(DRV_NAME " is coming up\n"); 5302 5303 return 0; 5304 } 5305 5306 set_bit(S_EXIT_PENDING, &il->status); 5307 __il4965_down(il); 5308 clear_bit(S_EXIT_PENDING, &il->status); 5309 5310 /* tried to restart and config the device for as long as our 5311 * patience could withstand */ 5312 IL_ERR("Unable to initialize device after %d attempts.\n", i); 5313 return -EIO; 5314} 5315 5316/***************************************************************************** 5317 * 5318 * Workqueue callbacks 5319 * 5320 *****************************************************************************/ 5321 5322static void 5323il4965_bg_init_alive_start(struct work_struct *data) 5324{ 5325 struct il_priv *il = 5326 container_of(data, struct il_priv, init_alive_start.work); 5327 5328 mutex_lock(&il->mutex); 5329 if (test_bit(S_EXIT_PENDING, &il->status)) 5330 goto out; 5331 5332 il->cfg->ops->lib->init_alive_start(il); 5333out: 5334 mutex_unlock(&il->mutex); 5335} 5336 5337static void 5338il4965_bg_alive_start(struct work_struct *data) 5339{ 5340 struct il_priv *il = 5341 container_of(data, struct il_priv, alive_start.work); 5342 5343 mutex_lock(&il->mutex); 5344 if (test_bit(S_EXIT_PENDING, &il->status)) 5345 goto out; 5346 5347 il4965_alive_start(il); 5348out: 5349 mutex_unlock(&il->mutex); 5350} 5351 5352static void 5353il4965_bg_run_time_calib_work(struct work_struct *work) 5354{ 5355 struct il_priv *il = container_of(work, struct il_priv, 5356 run_time_calib_work); 5357 5358 mutex_lock(&il->mutex); 5359 5360 if (test_bit(S_EXIT_PENDING, &il->status) || 5361 test_bit(S_SCANNING, &il->status)) { 5362 mutex_unlock(&il->mutex); 5363 return; 5364 } 5365 5366 if (il->start_calib) { 5367 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats); 5368 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats); 5369 } 5370 5371 mutex_unlock(&il->mutex); 5372} 5373 5374static void 5375il4965_bg_restart(struct work_struct *data) 5376{ 5377 struct il_priv *il = container_of(data, struct il_priv, restart); 5378 5379 if (test_bit(S_EXIT_PENDING, &il->status)) 5380 return; 5381 5382 if (test_and_clear_bit(S_FW_ERROR, &il->status)) { 5383 mutex_lock(&il->mutex); 5384 il->ctx.vif = NULL; 5385 il->is_open = 0; 5386 5387 __il4965_down(il); 5388 5389 mutex_unlock(&il->mutex); 5390 il4965_cancel_deferred_work(il); 5391 ieee80211_restart_hw(il->hw); 5392 } else { 5393 il4965_down(il); 5394 5395 mutex_lock(&il->mutex); 5396 if (test_bit(S_EXIT_PENDING, &il->status)) { 5397 mutex_unlock(&il->mutex); 5398 return; 5399 } 5400 5401 __il4965_up(il); 5402 mutex_unlock(&il->mutex); 5403 } 5404} 5405 5406static void 5407il4965_bg_rx_replenish(struct work_struct *data) 5408{ 5409 struct il_priv *il = container_of(data, struct il_priv, rx_replenish); 5410 5411 if (test_bit(S_EXIT_PENDING, &il->status)) 5412 return; 5413 5414 mutex_lock(&il->mutex); 5415 il4965_rx_replenish(il); 5416 mutex_unlock(&il->mutex); 5417} 5418 5419/***************************************************************************** 5420 * 5421 * mac80211 entry point functions 5422 * 5423 *****************************************************************************/ 5424 5425#define UCODE_READY_TIMEOUT (4 * HZ) 5426 5427/* 5428 * Not a mac80211 entry point function, but it fits in with all the 5429 * other mac80211 functions grouped here. 5430 */ 5431static int 5432il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length) 5433{ 5434 int ret; 5435 struct ieee80211_hw *hw = il->hw; 5436 5437 hw->rate_control_algorithm = "iwl-4965-rs"; 5438 5439 /* Tell mac80211 our characteristics */ 5440 hw->flags = 5441 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION | 5442 IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT | 5443 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 5444 5445 if (il->cfg->sku & IL_SKU_N) 5446 hw->flags |= 5447 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | 5448 IEEE80211_HW_SUPPORTS_STATIC_SMPS; 5449 5450 hw->sta_data_size = sizeof(struct il_station_priv); 5451 hw->vif_data_size = sizeof(struct il_vif_priv); 5452 5453 hw->wiphy->interface_modes |= il->ctx.interface_modes; 5454 hw->wiphy->interface_modes |= il->ctx.exclusive_interface_modes; 5455 5456 hw->wiphy->flags |= 5457 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS; 5458 5459 /* 5460 * For now, disable PS by default because it affects 5461 * RX performance significantly. 5462 */ 5463 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 5464 5465 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; 5466 /* we create the 802.11 header and a zero-length SSID element */ 5467 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2; 5468 5469 /* Default value; 4 EDCA QOS priorities */ 5470 hw->queues = 4; 5471 5472 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL; 5473 5474 if (il->bands[IEEE80211_BAND_2GHZ].n_channels) 5475 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 5476 &il->bands[IEEE80211_BAND_2GHZ]; 5477 if (il->bands[IEEE80211_BAND_5GHZ].n_channels) 5478 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 5479 &il->bands[IEEE80211_BAND_5GHZ]; 5480 5481 il_leds_init(il); 5482 5483 ret = ieee80211_register_hw(il->hw); 5484 if (ret) { 5485 IL_ERR("Failed to register hw (error %d)\n", ret); 5486 return ret; 5487 } 5488 il->mac80211_registered = 1; 5489 5490 return 0; 5491} 5492 5493int 5494il4965_mac_start(struct ieee80211_hw *hw) 5495{ 5496 struct il_priv *il = hw->priv; 5497 int ret; 5498 5499 D_MAC80211("enter\n"); 5500 5501 /* we should be verifying the device is ready to be opened */ 5502 mutex_lock(&il->mutex); 5503 ret = __il4965_up(il); 5504 mutex_unlock(&il->mutex); 5505 5506 if (ret) 5507 return ret; 5508 5509 if (il_is_rfkill(il)) 5510 goto out; 5511 5512 D_INFO("Start UP work done.\n"); 5513 5514 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from 5515 * mac80211 will not be run successfully. */ 5516 ret = wait_event_timeout(il->wait_command_queue, 5517 test_bit(S_READY, &il->status), 5518 UCODE_READY_TIMEOUT); 5519 if (!ret) { 5520 if (!test_bit(S_READY, &il->status)) { 5521 IL_ERR("START_ALIVE timeout after %dms.\n", 5522 jiffies_to_msecs(UCODE_READY_TIMEOUT)); 5523 return -ETIMEDOUT; 5524 } 5525 } 5526 5527 il4965_led_enable(il); 5528 5529out: 5530 il->is_open = 1; 5531 D_MAC80211("leave\n"); 5532 return 0; 5533} 5534 5535void 5536il4965_mac_stop(struct ieee80211_hw *hw) 5537{ 5538 struct il_priv *il = hw->priv; 5539 5540 D_MAC80211("enter\n"); 5541 5542 if (!il->is_open) 5543 return; 5544 5545 il->is_open = 0; 5546 5547 il4965_down(il); 5548 5549 flush_workqueue(il->workqueue); 5550 5551 /* User space software may expect getting rfkill changes 5552 * even if interface is down */ 5553 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5554 il_enable_rfkill_int(il); 5555 5556 D_MAC80211("leave\n"); 5557} 5558 5559void 5560il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 5561{ 5562 struct il_priv *il = hw->priv; 5563 5564 D_MACDUMP("enter\n"); 5565 5566 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, 5567 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); 5568 5569 if (il4965_tx_skb(il, skb)) 5570 dev_kfree_skb_any(skb); 5571 5572 D_MACDUMP("leave\n"); 5573} 5574 5575void 5576il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5577 struct ieee80211_key_conf *keyconf, 5578 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key) 5579{ 5580 struct il_priv *il = hw->priv; 5581 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 5582 5583 D_MAC80211("enter\n"); 5584 5585 il4965_update_tkip_key(il, vif_priv->ctx, keyconf, sta, iv32, 5586 phase1key); 5587 5588 D_MAC80211("leave\n"); 5589} 5590 5591int 5592il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 5593 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 5594 struct ieee80211_key_conf *key) 5595{ 5596 struct il_priv *il = hw->priv; 5597 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 5598 struct il_rxon_context *ctx = vif_priv->ctx; 5599 int ret; 5600 u8 sta_id; 5601 bool is_default_wep_key = false; 5602 5603 D_MAC80211("enter\n"); 5604 5605 if (il->cfg->mod_params->sw_crypto) { 5606 D_MAC80211("leave - hwcrypto disabled\n"); 5607 return -EOPNOTSUPP; 5608 } 5609 5610 sta_id = il_sta_id_or_broadcast(il, vif_priv->ctx, sta); 5611 if (sta_id == IL_INVALID_STATION) 5612 return -EINVAL; 5613 5614 mutex_lock(&il->mutex); 5615 il_scan_cancel_timeout(il, 100); 5616 5617 /* 5618 * If we are getting WEP group key and we didn't receive any key mapping 5619 * so far, we are in legacy wep mode (group key only), otherwise we are 5620 * in 1X mode. 5621 * In legacy wep mode, we use another host command to the uCode. 5622 */ 5623 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || 5624 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) { 5625 if (cmd == SET_KEY) 5626 is_default_wep_key = !ctx->key_mapping_keys; 5627 else 5628 is_default_wep_key = 5629 (key->hw_key_idx == HW_KEY_DEFAULT); 5630 } 5631 5632 switch (cmd) { 5633 case SET_KEY: 5634 if (is_default_wep_key) 5635 ret = 5636 il4965_set_default_wep_key(il, vif_priv->ctx, key); 5637 else 5638 ret = 5639 il4965_set_dynamic_key(il, vif_priv->ctx, key, 5640 sta_id); 5641 5642 D_MAC80211("enable hwcrypto key\n"); 5643 break; 5644 case DISABLE_KEY: 5645 if (is_default_wep_key) 5646 ret = il4965_remove_default_wep_key(il, ctx, key); 5647 else 5648 ret = il4965_remove_dynamic_key(il, ctx, key, sta_id); 5649 5650 D_MAC80211("disable hwcrypto key\n"); 5651 break; 5652 default: 5653 ret = -EINVAL; 5654 } 5655 5656 mutex_unlock(&il->mutex); 5657 D_MAC80211("leave\n"); 5658 5659 return ret; 5660} 5661 5662int 5663il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5664 enum ieee80211_ampdu_mlme_action action, 5665 struct ieee80211_sta *sta, u16 tid, u16 * ssn, 5666 u8 buf_size) 5667{ 5668 struct il_priv *il = hw->priv; 5669 int ret = -EINVAL; 5670 5671 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid); 5672 5673 if (!(il->cfg->sku & IL_SKU_N)) 5674 return -EACCES; 5675 5676 mutex_lock(&il->mutex); 5677 5678 switch (action) { 5679 case IEEE80211_AMPDU_RX_START: 5680 D_HT("start Rx\n"); 5681 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn); 5682 break; 5683 case IEEE80211_AMPDU_RX_STOP: 5684 D_HT("stop Rx\n"); 5685 ret = il4965_sta_rx_agg_stop(il, sta, tid); 5686 if (test_bit(S_EXIT_PENDING, &il->status)) 5687 ret = 0; 5688 break; 5689 case IEEE80211_AMPDU_TX_START: 5690 D_HT("start Tx\n"); 5691 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn); 5692 break; 5693 case IEEE80211_AMPDU_TX_STOP: 5694 D_HT("stop Tx\n"); 5695 ret = il4965_tx_agg_stop(il, vif, sta, tid); 5696 if (test_bit(S_EXIT_PENDING, &il->status)) 5697 ret = 0; 5698 break; 5699 case IEEE80211_AMPDU_TX_OPERATIONAL: 5700 ret = 0; 5701 break; 5702 } 5703 mutex_unlock(&il->mutex); 5704 5705 return ret; 5706} 5707 5708int 5709il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5710 struct ieee80211_sta *sta) 5711{ 5712 struct il_priv *il = hw->priv; 5713 struct il_station_priv *sta_priv = (void *)sta->drv_priv; 5714 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 5715 bool is_ap = vif->type == NL80211_IFTYPE_STATION; 5716 int ret; 5717 u8 sta_id; 5718 5719 D_INFO("received request to add station %pM\n", sta->addr); 5720 mutex_lock(&il->mutex); 5721 D_INFO("proceeding to add station %pM\n", sta->addr); 5722 sta_priv->common.sta_id = IL_INVALID_STATION; 5723 5724 atomic_set(&sta_priv->pending_frames, 0); 5725 5726 ret = 5727 il_add_station_common(il, vif_priv->ctx, sta->addr, is_ap, sta, 5728 &sta_id); 5729 if (ret) { 5730 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret); 5731 /* Should we return success if return code is EEXIST ? */ 5732 mutex_unlock(&il->mutex); 5733 return ret; 5734 } 5735 5736 sta_priv->common.sta_id = sta_id; 5737 5738 /* Initialize rate scaling */ 5739 D_INFO("Initializing rate scaling for station %pM\n", sta->addr); 5740 il4965_rs_rate_init(il, sta, sta_id); 5741 mutex_unlock(&il->mutex); 5742 5743 return 0; 5744} 5745 5746void 5747il4965_mac_channel_switch(struct ieee80211_hw *hw, 5748 struct ieee80211_channel_switch *ch_switch) 5749{ 5750 struct il_priv *il = hw->priv; 5751 const struct il_channel_info *ch_info; 5752 struct ieee80211_conf *conf = &hw->conf; 5753 struct ieee80211_channel *channel = ch_switch->channel; 5754 struct il_ht_config *ht_conf = &il->current_ht_config; 5755 5756 struct il_rxon_context *ctx = &il->ctx; 5757 u16 ch; 5758 5759 D_MAC80211("enter\n"); 5760 5761 mutex_lock(&il->mutex); 5762 5763 if (il_is_rfkill(il)) 5764 goto out; 5765 5766 if (test_bit(S_EXIT_PENDING, &il->status) || 5767 test_bit(S_SCANNING, &il->status) || 5768 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) 5769 goto out; 5770 5771 if (!il_is_associated_ctx(ctx)) 5772 goto out; 5773 5774 if (!il->cfg->ops->lib->set_channel_switch) 5775 goto out; 5776 5777 ch = channel->hw_value; 5778 if (le16_to_cpu(ctx->active.channel) == ch) 5779 goto out; 5780 5781 ch_info = il_get_channel_info(il, channel->band, ch); 5782 if (!il_is_channel_valid(ch_info)) { 5783 D_MAC80211("invalid channel\n"); 5784 goto out; 5785 } 5786 5787 spin_lock_irq(&il->lock); 5788 5789 il->current_ht_config.smps = conf->smps_mode; 5790 5791 /* Configure HT40 channels */ 5792 ctx->ht.enabled = conf_is_ht(conf); 5793 if (ctx->ht.enabled) { 5794 if (conf_is_ht40_minus(conf)) { 5795 ctx->ht.extension_chan_offset = 5796 IEEE80211_HT_PARAM_CHA_SEC_BELOW; 5797 ctx->ht.is_40mhz = true; 5798 } else if (conf_is_ht40_plus(conf)) { 5799 ctx->ht.extension_chan_offset = 5800 IEEE80211_HT_PARAM_CHA_SEC_ABOVE; 5801 ctx->ht.is_40mhz = true; 5802 } else { 5803 ctx->ht.extension_chan_offset = 5804 IEEE80211_HT_PARAM_CHA_SEC_NONE; 5805 ctx->ht.is_40mhz = false; 5806 } 5807 } else 5808 ctx->ht.is_40mhz = false; 5809 5810 if ((le16_to_cpu(ctx->staging.channel) != ch)) 5811 ctx->staging.flags = 0; 5812 5813 il_set_rxon_channel(il, channel, ctx); 5814 il_set_rxon_ht(il, ht_conf); 5815 il_set_flags_for_band(il, ctx, channel->band, ctx->vif); 5816 5817 spin_unlock_irq(&il->lock); 5818 5819 il_set_rate(il); 5820 /* 5821 * at this point, staging_rxon has the 5822 * configuration for channel switch 5823 */ 5824 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status); 5825 il->switch_channel = cpu_to_le16(ch); 5826 if (il->cfg->ops->lib->set_channel_switch(il, ch_switch)) { 5827 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status); 5828 il->switch_channel = 0; 5829 ieee80211_chswitch_done(ctx->vif, false); 5830 } 5831 5832out: 5833 mutex_unlock(&il->mutex); 5834 D_MAC80211("leave\n"); 5835} 5836 5837void 5838il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, 5839 unsigned int *total_flags, u64 multicast) 5840{ 5841 struct il_priv *il = hw->priv; 5842 __le32 filter_or = 0, filter_nand = 0; 5843 5844#define CHK(test, flag) do { \ 5845 if (*total_flags & (test)) \ 5846 filter_or |= (flag); \ 5847 else \ 5848 filter_nand |= (flag); \ 5849 } while (0) 5850 5851 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags, 5852 *total_flags); 5853 5854 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); 5855 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ 5856 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); 5857 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); 5858 5859#undef CHK 5860 5861 mutex_lock(&il->mutex); 5862 5863 il->ctx.staging.filter_flags &= ~filter_nand; 5864 il->ctx.staging.filter_flags |= filter_or; 5865 5866 /* 5867 * Not committing directly because hardware can perform a scan, 5868 * but we'll eventually commit the filter flags change anyway. 5869 */ 5870 5871 mutex_unlock(&il->mutex); 5872 5873 /* 5874 * Receiving all multicast frames is always enabled by the 5875 * default flags setup in il_connection_init_rx_config() 5876 * since we currently do not support programming multicast 5877 * filters into the device. 5878 */ 5879 *total_flags &= 5880 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | 5881 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; 5882} 5883 5884/***************************************************************************** 5885 * 5886 * driver setup and teardown 5887 * 5888 *****************************************************************************/ 5889 5890static void 5891il4965_bg_txpower_work(struct work_struct *work) 5892{ 5893 struct il_priv *il = container_of(work, struct il_priv, 5894 txpower_work); 5895 5896 mutex_lock(&il->mutex); 5897 5898 /* If a scan happened to start before we got here 5899 * then just return; the stats notification will 5900 * kick off another scheduled work to compensate for 5901 * any temperature delta we missed here. */ 5902 if (test_bit(S_EXIT_PENDING, &il->status) || 5903 test_bit(S_SCANNING, &il->status)) 5904 goto out; 5905 5906 /* Regardless of if we are associated, we must reconfigure the 5907 * TX power since frames can be sent on non-radar channels while 5908 * not associated */ 5909 il->cfg->ops->lib->send_tx_power(il); 5910 5911 /* Update last_temperature to keep is_calib_needed from running 5912 * when it isn't needed... */ 5913 il->last_temperature = il->temperature; 5914out: 5915 mutex_unlock(&il->mutex); 5916} 5917 5918static void 5919il4965_setup_deferred_work(struct il_priv *il) 5920{ 5921 il->workqueue = create_singlethread_workqueue(DRV_NAME); 5922 5923 init_waitqueue_head(&il->wait_command_queue); 5924 5925 INIT_WORK(&il->restart, il4965_bg_restart); 5926 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish); 5927 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work); 5928 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start); 5929 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start); 5930 5931 il_setup_scan_deferred_work(il); 5932 5933 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work); 5934 5935 init_timer(&il->stats_periodic); 5936 il->stats_periodic.data = (unsigned long)il; 5937 il->stats_periodic.function = il4965_bg_stats_periodic; 5938 5939 init_timer(&il->watchdog); 5940 il->watchdog.data = (unsigned long)il; 5941 il->watchdog.function = il_bg_watchdog; 5942 5943 tasklet_init(&il->irq_tasklet, 5944 (void (*)(unsigned long))il4965_irq_tasklet, 5945 (unsigned long)il); 5946} 5947 5948static void 5949il4965_cancel_deferred_work(struct il_priv *il) 5950{ 5951 cancel_work_sync(&il->txpower_work); 5952 cancel_delayed_work_sync(&il->init_alive_start); 5953 cancel_delayed_work(&il->alive_start); 5954 cancel_work_sync(&il->run_time_calib_work); 5955 5956 il_cancel_scan_deferred_work(il); 5957 5958 del_timer_sync(&il->stats_periodic); 5959} 5960 5961static void 5962il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates) 5963{ 5964 int i; 5965 5966 for (i = 0; i < RATE_COUNT_LEGACY; i++) { 5967 rates[i].bitrate = il_rates[i].ieee * 5; 5968 rates[i].hw_value = i; /* Rate scaling will work on idxes */ 5969 rates[i].hw_value_short = i; 5970 rates[i].flags = 0; 5971 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) { 5972 /* 5973 * If CCK != 1M then set short preamble rate flag. 5974 */ 5975 rates[i].flags |= 5976 (il_rates[i].plcp == 5977 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE; 5978 } 5979 } 5980} 5981 5982/* 5983 * Acquire il->lock before calling this function ! 5984 */ 5985void 5986il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx) 5987{ 5988 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8)); 5989 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx); 5990} 5991 5992void 5993il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq, 5994 int tx_fifo_id, int scd_retry) 5995{ 5996 int txq_id = txq->q.id; 5997 5998 /* Find out whether to activate Tx queue */ 5999 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0; 6000 6001 /* Set up and activate */ 6002 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), 6003 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 6004 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) | 6005 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) | 6006 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) | 6007 IL49_SCD_QUEUE_STTS_REG_MSK); 6008 6009 txq->sched_retry = scd_retry; 6010 6011 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate", 6012 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 6013} 6014 6015static int 6016il4965_init_drv(struct il_priv *il) 6017{ 6018 int ret; 6019 6020 spin_lock_init(&il->sta_lock); 6021 spin_lock_init(&il->hcmd_lock); 6022 6023 INIT_LIST_HEAD(&il->free_frames); 6024 6025 mutex_init(&il->mutex); 6026 6027 il->ieee_channels = NULL; 6028 il->ieee_rates = NULL; 6029 il->band = IEEE80211_BAND_2GHZ; 6030 6031 il->iw_mode = NL80211_IFTYPE_STATION; 6032 il->current_ht_config.smps = IEEE80211_SMPS_STATIC; 6033 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF; 6034 6035 /* initialize force reset */ 6036 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD; 6037 6038 /* Choose which receivers/antennas to use */ 6039 if (il->cfg->ops->hcmd->set_rxon_chain) 6040 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx); 6041 6042 il_init_scan_params(il); 6043 6044 ret = il_init_channel_map(il); 6045 if (ret) { 6046 IL_ERR("initializing regulatory failed: %d\n", ret); 6047 goto err; 6048 } 6049 6050 ret = il_init_geos(il); 6051 if (ret) { 6052 IL_ERR("initializing geos failed: %d\n", ret); 6053 goto err_free_channel_map; 6054 } 6055 il4965_init_hw_rates(il, il->ieee_rates); 6056 6057 return 0; 6058 6059err_free_channel_map: 6060 il_free_channel_map(il); 6061err: 6062 return ret; 6063} 6064 6065static void 6066il4965_uninit_drv(struct il_priv *il) 6067{ 6068 il4965_calib_free_results(il); 6069 il_free_geos(il); 6070 il_free_channel_map(il); 6071 kfree(il->scan_cmd); 6072} 6073 6074static void 6075il4965_hw_detect(struct il_priv *il) 6076{ 6077 il->hw_rev = _il_rd(il, CSR_HW_REV); 6078 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG); 6079 il->rev_id = il->pci_dev->revision; 6080 D_INFO("HW Revision ID = 0x%X\n", il->rev_id); 6081} 6082 6083static int 6084il4965_set_hw_params(struct il_priv *il) 6085{ 6086 il->hw_params.max_rxq_size = RX_QUEUE_SIZE; 6087 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 6088 if (il->cfg->mod_params->amsdu_size_8K) 6089 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K); 6090 else 6091 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K); 6092 6093 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL; 6094 6095 if (il->cfg->mod_params->disable_11n) 6096 il->cfg->sku &= ~IL_SKU_N; 6097 6098 /* Device-specific setup */ 6099 return il->cfg->ops->lib->set_hw_params(il); 6100} 6101 6102static const u8 il4965_bss_ac_to_fifo[] = { 6103 IL_TX_FIFO_VO, 6104 IL_TX_FIFO_VI, 6105 IL_TX_FIFO_BE, 6106 IL_TX_FIFO_BK, 6107}; 6108 6109static const u8 il4965_bss_ac_to_queue[] = { 6110 0, 1, 2, 3, 6111}; 6112 6113static int 6114il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 6115{ 6116 int err = 0; 6117 struct il_priv *il; 6118 struct ieee80211_hw *hw; 6119 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data); 6120 unsigned long flags; 6121 u16 pci_cmd; 6122 6123 /************************ 6124 * 1. Allocating HW data 6125 ************************/ 6126 6127 hw = il_alloc_all(cfg); 6128 if (!hw) { 6129 err = -ENOMEM; 6130 goto out; 6131 } 6132 il = hw->priv; 6133 /* At this point both hw and il are allocated. */ 6134 6135 il->ctx.ctxid = 0; 6136 6137 il->ctx.always_active = true; 6138 il->ctx.is_active = true; 6139 il->ctx.rxon_cmd = C_RXON; 6140 il->ctx.rxon_timing_cmd = C_RXON_TIMING; 6141 il->ctx.rxon_assoc_cmd = C_RXON_ASSOC; 6142 il->ctx.qos_cmd = C_QOS_PARAM; 6143 il->ctx.ap_sta_id = IL_AP_ID; 6144 il->ctx.wep_key_cmd = C_WEPKEY; 6145 il->ctx.ac_to_fifo = il4965_bss_ac_to_fifo; 6146 il->ctx.ac_to_queue = il4965_bss_ac_to_queue; 6147 il->ctx.exclusive_interface_modes = BIT(NL80211_IFTYPE_ADHOC); 6148 il->ctx.interface_modes = BIT(NL80211_IFTYPE_STATION); 6149 il->ctx.ap_devtype = RXON_DEV_TYPE_AP; 6150 il->ctx.ibss_devtype = RXON_DEV_TYPE_IBSS; 6151 il->ctx.station_devtype = RXON_DEV_TYPE_ESS; 6152 il->ctx.unused_devtype = RXON_DEV_TYPE_ESS; 6153 6154 SET_IEEE80211_DEV(hw, &pdev->dev); 6155 6156 D_INFO("*** LOAD DRIVER ***\n"); 6157 il->cfg = cfg; 6158 il->pci_dev = pdev; 6159 il->inta_mask = CSR_INI_SET_MASK; 6160 6161 if (il_alloc_traffic_mem(il)) 6162 IL_ERR("Not enough memory to generate traffic log\n"); 6163 6164 /************************** 6165 * 2. Initializing PCI bus 6166 **************************/ 6167 pci_disable_link_state(pdev, 6168 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | 6169 PCIE_LINK_STATE_CLKPM); 6170 6171 if (pci_enable_device(pdev)) { 6172 err = -ENODEV; 6173 goto out_ieee80211_free_hw; 6174 } 6175 6176 pci_set_master(pdev); 6177 6178 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); 6179 if (!err) 6180 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); 6181 if (err) { 6182 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 6183 if (!err) 6184 err = 6185 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 6186 /* both attempts failed: */ 6187 if (err) { 6188 IL_WARN("No suitable DMA available.\n"); 6189 goto out_pci_disable_device; 6190 } 6191 } 6192 6193 err = pci_request_regions(pdev, DRV_NAME); 6194 if (err) 6195 goto out_pci_disable_device; 6196 6197 pci_set_drvdata(pdev, il); 6198 6199 /*********************** 6200 * 3. Read REV register 6201 ***********************/ 6202 il->hw_base = pci_iomap(pdev, 0, 0); 6203 if (!il->hw_base) { 6204 err = -ENODEV; 6205 goto out_pci_release_regions; 6206 } 6207 6208 D_INFO("pci_resource_len = 0x%08llx\n", 6209 (unsigned long long)pci_resource_len(pdev, 0)); 6210 D_INFO("pci_resource_base = %p\n", il->hw_base); 6211 6212 /* these spin locks will be used in apm_ops.init and EEPROM access 6213 * we should init now 6214 */ 6215 spin_lock_init(&il->reg_lock); 6216 spin_lock_init(&il->lock); 6217 6218 /* 6219 * stop and reset the on-board processor just in case it is in a 6220 * strange state ... like being left stranded by a primary kernel 6221 * and this is now the kdump kernel trying to start up 6222 */ 6223 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 6224 6225 il4965_hw_detect(il); 6226 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev); 6227 6228 /* We disable the RETRY_TIMEOUT register (0x41) to keep 6229 * PCI Tx retries from interfering with C3 CPU state */ 6230 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 6231 6232 il4965_prepare_card_hw(il); 6233 if (!il->hw_ready) { 6234 IL_WARN("Failed, HW not ready\n"); 6235 goto out_iounmap; 6236 } 6237 6238 /***************** 6239 * 4. Read EEPROM 6240 *****************/ 6241 /* Read the EEPROM */ 6242 err = il_eeprom_init(il); 6243 if (err) { 6244 IL_ERR("Unable to init EEPROM\n"); 6245 goto out_iounmap; 6246 } 6247 err = il4965_eeprom_check_version(il); 6248 if (err) 6249 goto out_free_eeprom; 6250 6251 if (err) 6252 goto out_free_eeprom; 6253 6254 /* extract MAC Address */ 6255 il4965_eeprom_get_mac(il, il->addresses[0].addr); 6256 D_INFO("MAC address: %pM\n", il->addresses[0].addr); 6257 il->hw->wiphy->addresses = il->addresses; 6258 il->hw->wiphy->n_addresses = 1; 6259 6260 /************************ 6261 * 5. Setup HW constants 6262 ************************/ 6263 if (il4965_set_hw_params(il)) { 6264 IL_ERR("failed to set hw parameters\n"); 6265 goto out_free_eeprom; 6266 } 6267 6268 /******************* 6269 * 6. Setup il 6270 *******************/ 6271 6272 err = il4965_init_drv(il); 6273 if (err) 6274 goto out_free_eeprom; 6275 /* At this point both hw and il are initialized. */ 6276 6277 /******************** 6278 * 7. Setup services 6279 ********************/ 6280 spin_lock_irqsave(&il->lock, flags); 6281 il_disable_interrupts(il); 6282 spin_unlock_irqrestore(&il->lock, flags); 6283 6284 pci_enable_msi(il->pci_dev); 6285 6286 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il); 6287 if (err) { 6288 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq); 6289 goto out_disable_msi; 6290 } 6291 6292 il4965_setup_deferred_work(il); 6293 il4965_setup_handlers(il); 6294 6295 /********************************************* 6296 * 8. Enable interrupts and read RFKILL state 6297 *********************************************/ 6298 6299 /* enable rfkill interrupt: hw bug w/a */ 6300 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd); 6301 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 6302 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 6303 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd); 6304 } 6305 6306 il_enable_rfkill_int(il); 6307 6308 /* If platform's RF_KILL switch is NOT set to KILL */ 6309 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 6310 clear_bit(S_RF_KILL_HW, &il->status); 6311 else 6312 set_bit(S_RF_KILL_HW, &il->status); 6313 6314 wiphy_rfkill_set_hw_state(il->hw->wiphy, 6315 test_bit(S_RF_KILL_HW, &il->status)); 6316 6317 il_power_initialize(il); 6318 6319 init_completion(&il->_4965.firmware_loading_complete); 6320 6321 err = il4965_request_firmware(il, true); 6322 if (err) 6323 goto out_destroy_workqueue; 6324 6325 return 0; 6326 6327out_destroy_workqueue: 6328 destroy_workqueue(il->workqueue); 6329 il->workqueue = NULL; 6330 free_irq(il->pci_dev->irq, il); 6331out_disable_msi: 6332 pci_disable_msi(il->pci_dev); 6333 il4965_uninit_drv(il); 6334out_free_eeprom: 6335 il_eeprom_free(il); 6336out_iounmap: 6337 pci_iounmap(pdev, il->hw_base); 6338out_pci_release_regions: 6339 pci_set_drvdata(pdev, NULL); 6340 pci_release_regions(pdev); 6341out_pci_disable_device: 6342 pci_disable_device(pdev); 6343out_ieee80211_free_hw: 6344 il_free_traffic_mem(il); 6345 ieee80211_free_hw(il->hw); 6346out: 6347 return err; 6348} 6349 6350static void __devexit 6351il4965_pci_remove(struct pci_dev *pdev) 6352{ 6353 struct il_priv *il = pci_get_drvdata(pdev); 6354 unsigned long flags; 6355 6356 if (!il) 6357 return; 6358 6359 wait_for_completion(&il->_4965.firmware_loading_complete); 6360 6361 D_INFO("*** UNLOAD DRIVER ***\n"); 6362 6363 il_dbgfs_unregister(il); 6364 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group); 6365 6366 /* ieee80211_unregister_hw call wil cause il_mac_stop to 6367 * to be called and il4965_down since we are removing the device 6368 * we need to set S_EXIT_PENDING bit. 6369 */ 6370 set_bit(S_EXIT_PENDING, &il->status); 6371 6372 il_leds_exit(il); 6373 6374 if (il->mac80211_registered) { 6375 ieee80211_unregister_hw(il->hw); 6376 il->mac80211_registered = 0; 6377 } else { 6378 il4965_down(il); 6379 } 6380 6381 /* 6382 * Make sure device is reset to low power before unloading driver. 6383 * This may be redundant with il4965_down(), but there are paths to 6384 * run il4965_down() without calling apm_ops.stop(), and there are 6385 * paths to avoid running il4965_down() at all before leaving driver. 6386 * This (inexpensive) call *makes sure* device is reset. 6387 */ 6388 il_apm_stop(il); 6389 6390 /* make sure we flush any pending irq or 6391 * tasklet for the driver 6392 */ 6393 spin_lock_irqsave(&il->lock, flags); 6394 il_disable_interrupts(il); 6395 spin_unlock_irqrestore(&il->lock, flags); 6396 6397 il4965_synchronize_irq(il); 6398 6399 il4965_dealloc_ucode_pci(il); 6400 6401 if (il->rxq.bd) 6402 il4965_rx_queue_free(il, &il->rxq); 6403 il4965_hw_txq_ctx_free(il); 6404 6405 il_eeprom_free(il); 6406 6407 /*netif_stop_queue(dev); */ 6408 flush_workqueue(il->workqueue); 6409 6410 /* ieee80211_unregister_hw calls il_mac_stop, which flushes 6411 * il->workqueue... so we can't take down the workqueue 6412 * until now... */ 6413 destroy_workqueue(il->workqueue); 6414 il->workqueue = NULL; 6415 il_free_traffic_mem(il); 6416 6417 free_irq(il->pci_dev->irq, il); 6418 pci_disable_msi(il->pci_dev); 6419 pci_iounmap(pdev, il->hw_base); 6420 pci_release_regions(pdev); 6421 pci_disable_device(pdev); 6422 pci_set_drvdata(pdev, NULL); 6423 6424 il4965_uninit_drv(il); 6425 6426 dev_kfree_skb(il->beacon_skb); 6427 6428 ieee80211_free_hw(il->hw); 6429} 6430 6431/* 6432 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 6433 * must be called under il->lock and mac access 6434 */ 6435void 6436il4965_txq_set_sched(struct il_priv *il, u32 mask) 6437{ 6438 il_wr_prph(il, IL49_SCD_TXFACT, mask); 6439} 6440 6441/***************************************************************************** 6442 * 6443 * driver and module entry point 6444 * 6445 *****************************************************************************/ 6446 6447/* Hardware specific file defines the PCI IDs table for that hardware module */ 6448static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = { 6449 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)}, 6450 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)}, 6451 {0} 6452}; 6453MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids); 6454 6455static struct pci_driver il4965_driver = { 6456 .name = DRV_NAME, 6457 .id_table = il4965_hw_card_ids, 6458 .probe = il4965_pci_probe, 6459 .remove = __devexit_p(il4965_pci_remove), 6460 .driver.pm = IL_LEGACY_PM_OPS, 6461}; 6462 6463static int __init 6464il4965_init(void) 6465{ 6466 6467 int ret; 6468 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); 6469 pr_info(DRV_COPYRIGHT "\n"); 6470 6471 ret = il4965_rate_control_register(); 6472 if (ret) { 6473 pr_err("Unable to register rate control algorithm: %d\n", ret); 6474 return ret; 6475 } 6476 6477 ret = pci_register_driver(&il4965_driver); 6478 if (ret) { 6479 pr_err("Unable to initialize PCI module\n"); 6480 goto error_register; 6481 } 6482 6483 return ret; 6484 6485error_register: 6486 il4965_rate_control_unregister(); 6487 return ret; 6488} 6489 6490static void __exit 6491il4965_exit(void) 6492{ 6493 pci_unregister_driver(&il4965_driver); 6494 il4965_rate_control_unregister(); 6495} 6496 6497module_exit(il4965_exit); 6498module_init(il4965_init); 6499 6500#ifdef CONFIG_IWLEGACY_DEBUG 6501module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR); 6502MODULE_PARM_DESC(debug, "debug output mask"); 6503#endif 6504 6505module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO); 6506MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); 6507module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO); 6508MODULE_PARM_DESC(queues_num, "number of hw queues."); 6509module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO); 6510MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); 6511module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int, 6512 S_IRUGO); 6513MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); 6514module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO); 6515MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); 6516