1/* 2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * Copyright (C) 2009 NVIDIA Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 */ 18 19#include <linux/clk.h> 20#include <linux/platform_device.h> 21#include <linux/platform_data/tegra_usb.h> 22#include <linux/irq.h> 23#include <linux/usb/otg.h> 24#include <linux/gpio.h> 25#include <linux/of.h> 26#include <linux/of_gpio.h> 27 28#include <mach/usb_phy.h> 29#include <mach/iomap.h> 30 31#define TEGRA_USB_DMA_ALIGN 32 32 33struct tegra_ehci_hcd { 34 struct ehci_hcd *ehci; 35 struct tegra_usb_phy *phy; 36 struct clk *clk; 37 struct clk *emc_clk; 38 struct otg_transceiver *transceiver; 39 int host_resumed; 40 int bus_suspended; 41 int port_resuming; 42 int power_down_on_bus_suspend; 43 enum tegra_usb_phy_port_speed port_speed; 44}; 45 46static void tegra_ehci_power_up(struct usb_hcd *hcd) 47{ 48 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 49 50 clk_enable(tegra->emc_clk); 51 clk_enable(tegra->clk); 52 tegra_usb_phy_power_on(tegra->phy); 53 tegra->host_resumed = 1; 54} 55 56static void tegra_ehci_power_down(struct usb_hcd *hcd) 57{ 58 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 59 60 tegra->host_resumed = 0; 61 tegra_usb_phy_power_off(tegra->phy); 62 clk_disable(tegra->clk); 63 clk_disable(tegra->emc_clk); 64} 65 66static int tegra_ehci_internal_port_reset( 67 struct ehci_hcd *ehci, 68 u32 __iomem *portsc_reg 69) 70{ 71 u32 temp; 72 unsigned long flags; 73 int retval = 0; 74 int i, tries; 75 u32 saved_usbintr; 76 77 spin_lock_irqsave(&ehci->lock, flags); 78 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); 79 /* disable USB interrupt */ 80 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 81 spin_unlock_irqrestore(&ehci->lock, flags); 82 83 /* 84 * Here we have to do Port Reset at most twice for 85 * Port Enable bit to be set. 86 */ 87 for (i = 0; i < 2; i++) { 88 temp = ehci_readl(ehci, portsc_reg); 89 temp |= PORT_RESET; 90 ehci_writel(ehci, temp, portsc_reg); 91 mdelay(10); 92 temp &= ~PORT_RESET; 93 ehci_writel(ehci, temp, portsc_reg); 94 mdelay(1); 95 tries = 100; 96 do { 97 mdelay(1); 98 /* 99 * Up to this point, Port Enable bit is 100 * expected to be set after 2 ms waiting. 101 * USB1 usually takes extra 45 ms, for safety, 102 * we take 100 ms as timeout. 103 */ 104 temp = ehci_readl(ehci, portsc_reg); 105 } while (!(temp & PORT_PE) && tries--); 106 if (temp & PORT_PE) 107 break; 108 } 109 if (i == 2) 110 retval = -ETIMEDOUT; 111 112 /* 113 * Clear Connect Status Change bit if it's set. 114 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. 115 */ 116 if (temp & PORT_CSC) 117 ehci_writel(ehci, PORT_CSC, portsc_reg); 118 119 /* 120 * Write to clear any interrupt status bits that might be set 121 * during port reset. 122 */ 123 temp = ehci_readl(ehci, &ehci->regs->status); 124 ehci_writel(ehci, temp, &ehci->regs->status); 125 126 /* restore original interrupt enable bits */ 127 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); 128 return retval; 129} 130 131static int tegra_ehci_hub_control( 132 struct usb_hcd *hcd, 133 u16 typeReq, 134 u16 wValue, 135 u16 wIndex, 136 char *buf, 137 u16 wLength 138) 139{ 140 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 141 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 142 u32 __iomem *status_reg; 143 u32 temp; 144 unsigned long flags; 145 int retval = 0; 146 147 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; 148 149 spin_lock_irqsave(&ehci->lock, flags); 150 151 /* 152 * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits 153 * that are write on clear, by writing back the register read value, so 154 * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits 155 */ 156 if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) { 157 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS; 158 ehci_writel(ehci, temp & ~PORT_PE, status_reg); 159 goto done; 160 } 161 162 else if (typeReq == GetPortStatus) { 163 temp = ehci_readl(ehci, status_reg); 164 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { 165 /* Resume completed, re-enable disconnect detection */ 166 tegra->port_resuming = 0; 167 tegra_usb_phy_postresume(tegra->phy); 168 } 169 } 170 171 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { 172 temp = ehci_readl(ehci, status_reg); 173 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { 174 retval = -EPIPE; 175 goto done; 176 } 177 178 temp &= ~PORT_WKCONN_E; 179 temp |= PORT_WKDISC_E | PORT_WKOC_E; 180 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); 181 182 /* 183 * If a transaction is in progress, there may be a delay in 184 * suspending the port. Poll until the port is suspended. 185 */ 186 if (handshake(ehci, status_reg, PORT_SUSPEND, 187 PORT_SUSPEND, 5000)) 188 pr_err("%s: timeout waiting for SUSPEND\n", __func__); 189 190 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); 191 goto done; 192 } 193 194 /* For USB1 port we need to issue Port Reset twice internally */ 195 if (tegra->phy->instance == 0 && 196 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { 197 spin_unlock_irqrestore(&ehci->lock, flags); 198 return tegra_ehci_internal_port_reset(ehci, status_reg); 199 } 200 201 /* 202 * Tegra host controller will time the resume operation to clear the bit 203 * when the port control state switches to HS or FS Idle. This behavior 204 * is different from EHCI where the host controller driver is required 205 * to set this bit to a zero after the resume duration is timed in the 206 * driver. 207 */ 208 else if (typeReq == ClearPortFeature && 209 wValue == USB_PORT_FEAT_SUSPEND) { 210 temp = ehci_readl(ehci, status_reg); 211 if ((temp & PORT_RESET) || !(temp & PORT_PE)) { 212 retval = -EPIPE; 213 goto done; 214 } 215 216 if (!(temp & PORT_SUSPEND)) 217 goto done; 218 219 /* Disable disconnect detection during port resume */ 220 tegra_usb_phy_preresume(tegra->phy); 221 222 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); 223 224 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 225 /* start resume signalling */ 226 ehci_writel(ehci, temp | PORT_RESUME, status_reg); 227 228 spin_unlock_irqrestore(&ehci->lock, flags); 229 msleep(20); 230 spin_lock_irqsave(&ehci->lock, flags); 231 232 /* Poll until the controller clears RESUME and SUSPEND */ 233 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) 234 pr_err("%s: timeout waiting for RESUME\n", __func__); 235 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) 236 pr_err("%s: timeout waiting for SUSPEND\n", __func__); 237 238 ehci->reset_done[wIndex-1] = 0; 239 240 tegra->port_resuming = 1; 241 goto done; 242 } 243 244 spin_unlock_irqrestore(&ehci->lock, flags); 245 246 /* Handle the hub control events here */ 247 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); 248done: 249 spin_unlock_irqrestore(&ehci->lock, flags); 250 return retval; 251} 252 253static void tegra_ehci_restart(struct usb_hcd *hcd) 254{ 255 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 256 257 ehci_reset(ehci); 258 259 /* setup the frame list and Async q heads */ 260 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 261 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 262 /* setup the command register and set the controller in RUN mode */ 263 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 264 ehci->command |= CMD_RUN; 265 ehci_writel(ehci, ehci->command, &ehci->regs->command); 266 267 down_write(&ehci_cf_port_reset_rwsem); 268 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 269 /* flush posted writes */ 270 ehci_readl(ehci, &ehci->regs->command); 271 up_write(&ehci_cf_port_reset_rwsem); 272} 273 274static int tegra_usb_suspend(struct usb_hcd *hcd) 275{ 276 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 277 struct ehci_regs __iomem *hw = tegra->ehci->regs; 278 unsigned long flags; 279 280 spin_lock_irqsave(&tegra->ehci->lock, flags); 281 282 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3; 283 ehci_halt(tegra->ehci); 284 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 285 286 spin_unlock_irqrestore(&tegra->ehci->lock, flags); 287 288 tegra_ehci_power_down(hcd); 289 return 0; 290} 291 292static int tegra_usb_resume(struct usb_hcd *hcd) 293{ 294 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 295 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 296 struct ehci_regs __iomem *hw = ehci->regs; 297 unsigned long val; 298 299 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 300 tegra_ehci_power_up(hcd); 301 302 if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) { 303 /* Wait for the phy to detect new devices 304 * before we restart the controller */ 305 msleep(10); 306 goto restart; 307 } 308 309 /* Force the phy to keep data lines in suspend state */ 310 tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed); 311 312 /* Enable host mode */ 313 tdi_reset(ehci); 314 315 /* Enable Port Power */ 316 val = readl(&hw->port_status[0]); 317 val |= PORT_POWER; 318 writel(val, &hw->port_status[0]); 319 udelay(10); 320 321 /* Check if the phy resume from LP0. When the phy resume from LP0 322 * USB register will be reset. */ 323 if (!readl(&hw->async_next)) { 324 /* Program the field PTC based on the saved speed mode */ 325 val = readl(&hw->port_status[0]); 326 val &= ~PORT_TEST(~0); 327 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH) 328 val |= PORT_TEST_FORCE; 329 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL) 330 val |= PORT_TEST(6); 331 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) 332 val |= PORT_TEST(7); 333 writel(val, &hw->port_status[0]); 334 udelay(10); 335 336 /* Disable test mode by setting PTC field to NORMAL_OP */ 337 val = readl(&hw->port_status[0]); 338 val &= ~PORT_TEST(~0); 339 writel(val, &hw->port_status[0]); 340 udelay(10); 341 } 342 343 /* Poll until CCS is enabled */ 344 if (handshake(ehci, &hw->port_status[0], PORT_CONNECT, 345 PORT_CONNECT, 2000)) { 346 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__); 347 goto restart; 348 } 349 350 /* Poll until PE is enabled */ 351 if (handshake(ehci, &hw->port_status[0], PORT_PE, 352 PORT_PE, 2000)) { 353 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__); 354 goto restart; 355 } 356 357 /* Clear the PCI status, to avoid an interrupt taken upon resume */ 358 val = readl(&hw->status); 359 val |= STS_PCD; 360 writel(val, &hw->status); 361 362 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */ 363 val = readl(&hw->port_status[0]); 364 if ((val & PORT_POWER) && (val & PORT_PE)) { 365 val |= PORT_SUSPEND; 366 writel(val, &hw->port_status[0]); 367 368 /* Wait until port suspend completes */ 369 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND, 370 PORT_SUSPEND, 1000)) { 371 pr_err("%s: timeout waiting for PORT_SUSPEND\n", 372 __func__); 373 goto restart; 374 } 375 } 376 377 tegra_ehci_phy_restore_end(tegra->phy); 378 return 0; 379 380restart: 381 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) 382 tegra_ehci_phy_restore_end(tegra->phy); 383 384 tegra_ehci_restart(hcd); 385 return 0; 386} 387 388static void tegra_ehci_shutdown(struct usb_hcd *hcd) 389{ 390 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 391 392 /* ehci_shutdown touches the USB controller registers, make sure 393 * controller has clocks to it */ 394 if (!tegra->host_resumed) 395 tegra_ehci_power_up(hcd); 396 397 ehci_shutdown(hcd); 398} 399 400static int tegra_ehci_setup(struct usb_hcd *hcd) 401{ 402 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 403 int retval; 404 405 /* EHCI registers start at offset 0x100 */ 406 ehci->caps = hcd->regs + 0x100; 407 ehci->regs = hcd->regs + 0x100 + 408 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); 409 410 dbg_hcs_params(ehci, "reset"); 411 dbg_hcc_params(ehci, "reset"); 412 413 /* cache this readonly data; minimize chip reads */ 414 ehci->hcs_params = readl(&ehci->caps->hcs_params); 415 416 /* switch to host mode */ 417 hcd->has_tt = 1; 418 ehci_reset(ehci); 419 420 retval = ehci_halt(ehci); 421 if (retval) 422 return retval; 423 424 /* data structure init */ 425 retval = ehci_init(hcd); 426 if (retval) 427 return retval; 428 429 ehci->sbrn = 0x20; 430 431 ehci_port_power(ehci, 1); 432 return retval; 433} 434 435#ifdef CONFIG_PM 436static int tegra_ehci_bus_suspend(struct usb_hcd *hcd) 437{ 438 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 439 int error_status = 0; 440 441 error_status = ehci_bus_suspend(hcd); 442 if (!error_status && tegra->power_down_on_bus_suspend) { 443 tegra_usb_suspend(hcd); 444 tegra->bus_suspended = 1; 445 } 446 447 return error_status; 448} 449 450static int tegra_ehci_bus_resume(struct usb_hcd *hcd) 451{ 452 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 453 454 if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) { 455 tegra_usb_resume(hcd); 456 tegra->bus_suspended = 0; 457 } 458 459 tegra_usb_phy_preresume(tegra->phy); 460 tegra->port_resuming = 1; 461 return ehci_bus_resume(hcd); 462} 463#endif 464 465struct temp_buffer { 466 void *kmalloc_ptr; 467 void *old_xfer_buffer; 468 u8 data[0]; 469}; 470 471static void free_temp_buffer(struct urb *urb) 472{ 473 enum dma_data_direction dir; 474 struct temp_buffer *temp; 475 476 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 477 return; 478 479 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 480 481 temp = container_of(urb->transfer_buffer, struct temp_buffer, 482 data); 483 484 if (dir == DMA_FROM_DEVICE) 485 memcpy(temp->old_xfer_buffer, temp->data, 486 urb->transfer_buffer_length); 487 urb->transfer_buffer = temp->old_xfer_buffer; 488 kfree(temp->kmalloc_ptr); 489 490 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 491} 492 493static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) 494{ 495 enum dma_data_direction dir; 496 struct temp_buffer *temp, *kmalloc_ptr; 497 size_t kmalloc_size; 498 499 if (urb->num_sgs || urb->sg || 500 urb->transfer_buffer_length == 0 || 501 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) 502 return 0; 503 504 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 505 506 /* Allocate a buffer with enough padding for alignment */ 507 kmalloc_size = urb->transfer_buffer_length + 508 sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1; 509 510 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 511 if (!kmalloc_ptr) 512 return -ENOMEM; 513 514 /* Position our struct temp_buffer such that data is aligned */ 515 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; 516 517 temp->kmalloc_ptr = kmalloc_ptr; 518 temp->old_xfer_buffer = urb->transfer_buffer; 519 if (dir == DMA_TO_DEVICE) 520 memcpy(temp->data, urb->transfer_buffer, 521 urb->transfer_buffer_length); 522 urb->transfer_buffer = temp->data; 523 524 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 525 526 return 0; 527} 528 529static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 530 gfp_t mem_flags) 531{ 532 int ret; 533 534 ret = alloc_temp_buffer(urb, mem_flags); 535 if (ret) 536 return ret; 537 538 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 539 if (ret) 540 free_temp_buffer(urb); 541 542 return ret; 543} 544 545static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 546{ 547 usb_hcd_unmap_urb_for_dma(hcd, urb); 548 free_temp_buffer(urb); 549} 550 551static const struct hc_driver tegra_ehci_hc_driver = { 552 .description = hcd_name, 553 .product_desc = "Tegra EHCI Host Controller", 554 .hcd_priv_size = sizeof(struct ehci_hcd), 555 556 .flags = HCD_USB2 | HCD_MEMORY, 557 558 .reset = tegra_ehci_setup, 559 .irq = ehci_irq, 560 561 .start = ehci_run, 562 .stop = ehci_stop, 563 .shutdown = tegra_ehci_shutdown, 564 .urb_enqueue = ehci_urb_enqueue, 565 .urb_dequeue = ehci_urb_dequeue, 566 .map_urb_for_dma = tegra_ehci_map_urb_for_dma, 567 .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, 568 .endpoint_disable = ehci_endpoint_disable, 569 .endpoint_reset = ehci_endpoint_reset, 570 .get_frame_number = ehci_get_frame, 571 .hub_status_data = ehci_hub_status_data, 572 .hub_control = tegra_ehci_hub_control, 573 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 574#ifdef CONFIG_PM 575 .bus_suspend = tegra_ehci_bus_suspend, 576 .bus_resume = tegra_ehci_bus_resume, 577#endif 578 .relinquish_port = ehci_relinquish_port, 579 .port_handed_over = ehci_port_handed_over, 580}; 581 582static int setup_vbus_gpio(struct platform_device *pdev) 583{ 584 int err = 0; 585 int gpio; 586 587 if (!pdev->dev.of_node) 588 return 0; 589 590 gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); 591 if (!gpio_is_valid(gpio)) 592 return 0; 593 594 err = gpio_request(gpio, "vbus_gpio"); 595 if (err) { 596 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); 597 return err; 598 } 599 err = gpio_direction_output(gpio, 1); 600 if (err) { 601 dev_err(&pdev->dev, "can't enable vbus\n"); 602 return err; 603 } 604 gpio_set_value(gpio, 1); 605 606 return err; 607} 608 609static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32); 610 611static int tegra_ehci_probe(struct platform_device *pdev) 612{ 613 struct resource *res; 614 struct usb_hcd *hcd; 615 struct tegra_ehci_hcd *tegra; 616 struct tegra_ehci_platform_data *pdata; 617 int err = 0; 618 int irq; 619 int instance = pdev->id; 620 621 pdata = pdev->dev.platform_data; 622 if (!pdata) { 623 dev_err(&pdev->dev, "Platform data missing\n"); 624 return -EINVAL; 625 } 626 627 /* Right now device-tree probed devices don't get dma_mask set. 628 * Since shared usb code relies on it, set it here for now. 629 * Once we have dma capability bindings this can go away. 630 */ 631 if (!pdev->dev.dma_mask) 632 pdev->dev.dma_mask = &tegra_ehci_dma_mask; 633 634 setup_vbus_gpio(pdev); 635 636 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); 637 if (!tegra) 638 return -ENOMEM; 639 640 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, 641 dev_name(&pdev->dev)); 642 if (!hcd) { 643 dev_err(&pdev->dev, "Unable to create HCD\n"); 644 err = -ENOMEM; 645 goto fail_hcd; 646 } 647 648 platform_set_drvdata(pdev, tegra); 649 650 tegra->clk = clk_get(&pdev->dev, NULL); 651 if (IS_ERR(tegra->clk)) { 652 dev_err(&pdev->dev, "Can't get ehci clock\n"); 653 err = PTR_ERR(tegra->clk); 654 goto fail_clk; 655 } 656 657 err = clk_enable(tegra->clk); 658 if (err) 659 goto fail_clken; 660 661 tegra->emc_clk = clk_get(&pdev->dev, "emc"); 662 if (IS_ERR(tegra->emc_clk)) { 663 dev_err(&pdev->dev, "Can't get emc clock\n"); 664 err = PTR_ERR(tegra->emc_clk); 665 goto fail_emc_clk; 666 } 667 668 clk_enable(tegra->emc_clk); 669 clk_set_rate(tegra->emc_clk, 400000000); 670 671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 672 if (!res) { 673 dev_err(&pdev->dev, "Failed to get I/O memory\n"); 674 err = -ENXIO; 675 goto fail_io; 676 } 677 hcd->rsrc_start = res->start; 678 hcd->rsrc_len = resource_size(res); 679 hcd->regs = ioremap(res->start, resource_size(res)); 680 if (!hcd->regs) { 681 dev_err(&pdev->dev, "Failed to remap I/O memory\n"); 682 err = -ENOMEM; 683 goto fail_io; 684 } 685 686 /* This is pretty ugly and needs to be fixed when we do only 687 * device-tree probing. Old code relies on the platform_device 688 * numbering that we lack for device-tree-instantiated devices. 689 */ 690 if (instance < 0) { 691 switch (res->start) { 692 case TEGRA_USB_BASE: 693 instance = 0; 694 break; 695 case TEGRA_USB2_BASE: 696 instance = 1; 697 break; 698 case TEGRA_USB3_BASE: 699 instance = 2; 700 break; 701 default: 702 err = -ENODEV; 703 dev_err(&pdev->dev, "unknown usb instance\n"); 704 goto fail_phy; 705 } 706 } 707 708 tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config, 709 TEGRA_USB_PHY_MODE_HOST); 710 if (IS_ERR(tegra->phy)) { 711 dev_err(&pdev->dev, "Failed to open USB phy\n"); 712 err = -ENXIO; 713 goto fail_phy; 714 } 715 716 err = tegra_usb_phy_power_on(tegra->phy); 717 if (err) { 718 dev_err(&pdev->dev, "Failed to power on the phy\n"); 719 goto fail; 720 } 721 722 tegra->host_resumed = 1; 723 tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend; 724 tegra->ehci = hcd_to_ehci(hcd); 725 726 irq = platform_get_irq(pdev, 0); 727 if (!irq) { 728 dev_err(&pdev->dev, "Failed to get IRQ\n"); 729 err = -ENODEV; 730 goto fail; 731 } 732 set_irq_flags(irq, IRQF_VALID); 733 734#ifdef CONFIG_USB_OTG_UTILS 735 if (pdata->operating_mode == TEGRA_USB_OTG) { 736 tegra->transceiver = otg_get_transceiver(); 737 if (tegra->transceiver) 738 otg_set_host(tegra->transceiver, &hcd->self); 739 } 740#endif 741 742 err = usb_add_hcd(hcd, irq, IRQF_SHARED); 743 if (err) { 744 dev_err(&pdev->dev, "Failed to add USB HCD\n"); 745 goto fail; 746 } 747 748 return err; 749 750fail: 751#ifdef CONFIG_USB_OTG_UTILS 752 if (tegra->transceiver) { 753 otg_set_host(tegra->transceiver, NULL); 754 otg_put_transceiver(tegra->transceiver); 755 } 756#endif 757 tegra_usb_phy_close(tegra->phy); 758fail_phy: 759 iounmap(hcd->regs); 760fail_io: 761 clk_disable(tegra->emc_clk); 762 clk_put(tegra->emc_clk); 763fail_emc_clk: 764 clk_disable(tegra->clk); 765fail_clken: 766 clk_put(tegra->clk); 767fail_clk: 768 usb_put_hcd(hcd); 769fail_hcd: 770 kfree(tegra); 771 return err; 772} 773 774#ifdef CONFIG_PM 775static int tegra_ehci_resume(struct platform_device *pdev) 776{ 777 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); 778 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); 779 780 if (tegra->bus_suspended) 781 return 0; 782 783 return tegra_usb_resume(hcd); 784} 785 786static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state) 787{ 788 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); 789 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); 790 791 if (tegra->bus_suspended) 792 return 0; 793 794 if (time_before(jiffies, tegra->ehci->next_statechange)) 795 msleep(10); 796 797 return tegra_usb_suspend(hcd); 798} 799#endif 800 801static int tegra_ehci_remove(struct platform_device *pdev) 802{ 803 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); 804 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); 805 806 if (tegra == NULL || hcd == NULL) 807 return -EINVAL; 808 809#ifdef CONFIG_USB_OTG_UTILS 810 if (tegra->transceiver) { 811 otg_set_host(tegra->transceiver, NULL); 812 otg_put_transceiver(tegra->transceiver); 813 } 814#endif 815 816 usb_remove_hcd(hcd); 817 usb_put_hcd(hcd); 818 819 tegra_usb_phy_close(tegra->phy); 820 iounmap(hcd->regs); 821 822 clk_disable(tegra->clk); 823 clk_put(tegra->clk); 824 825 clk_disable(tegra->emc_clk); 826 clk_put(tegra->emc_clk); 827 828 kfree(tegra); 829 return 0; 830} 831 832static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) 833{ 834 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); 835 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); 836 837 if (hcd->driver->shutdown) 838 hcd->driver->shutdown(hcd); 839} 840 841static struct of_device_id tegra_ehci_of_match[] __devinitdata = { 842 { .compatible = "nvidia,tegra20-ehci", }, 843 { }, 844}; 845 846static struct platform_driver tegra_ehci_driver = { 847 .probe = tegra_ehci_probe, 848 .remove = tegra_ehci_remove, 849#ifdef CONFIG_PM 850 .suspend = tegra_ehci_suspend, 851 .resume = tegra_ehci_resume, 852#endif 853 .shutdown = tegra_ehci_hcd_shutdown, 854 .driver = { 855 .name = "tegra-ehci", 856 .of_match_table = tegra_ehci_of_match, 857 } 858}; 859