1/* 2 * Open Host Controller Interface (OHCI) driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> 8 * 9 * [ Initialisation is based on Linus' ] 10 * [ uhci code and gregs ohci fragments ] 11 * [ (C) Copyright 1999 Linus Torvalds ] 12 * [ (C) Copyright 1999 Gregory P. Smith] 13 * 14 * 15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller 16 * interfaces (though some non-x86 Intel chips use it). It supports 17 * smarter hardware than UHCI. A download link for the spec available 18 * through the http://www.usb.org website. 19 * 20 * This file is licenced under the GPL. 21 */ 22 23#include <linux/module.h> 24#include <linux/moduleparam.h> 25#include <linux/pci.h> 26#include <linux/kernel.h> 27#include <linux/delay.h> 28#include <linux/ioport.h> 29#include <linux/sched.h> 30#include <linux/slab.h> 31#include <linux/errno.h> 32#include <linux/init.h> 33#include <linux/timer.h> 34#include <linux/list.h> 35#include <linux/usb.h> 36#include <linux/usb/otg.h> 37#include <linux/usb/hcd.h> 38#include <linux/dma-mapping.h> 39#include <linux/dmapool.h> 40#include <linux/workqueue.h> 41#include <linux/debugfs.h> 42 43#include <asm/io.h> 44#include <asm/irq.h> 45#include <asm/system.h> 46#include <asm/unaligned.h> 47#include <asm/byteorder.h> 48 49 50#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" 51#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" 52 53/*-------------------------------------------------------------------------*/ 54 55#undef OHCI_VERBOSE_DEBUG /* not always helpful */ 56 57/* For initializing controller (mask in an HCFS mode too) */ 58#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR 59#define OHCI_INTR_INIT \ 60 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ 61 | OHCI_INTR_RD | OHCI_INTR_WDH) 62 63#ifdef __hppa__ 64/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 65#define IR_DISABLE 66#endif 67 68#ifdef CONFIG_ARCH_OMAP 69/* OMAP doesn't support IR (no SMM; not needed) */ 70#define IR_DISABLE 71#endif 72 73/*-------------------------------------------------------------------------*/ 74 75static const char hcd_name [] = "ohci_hcd"; 76 77#define STATECHANGE_DELAY msecs_to_jiffies(300) 78 79#include "ohci.h" 80#include "pci-quirks.h" 81 82static void ohci_dump (struct ohci_hcd *ohci, int verbose); 83static int ohci_init (struct ohci_hcd *ohci); 84static void ohci_stop (struct usb_hcd *hcd); 85 86#if defined(CONFIG_PM) || defined(CONFIG_PCI) 87static int ohci_restart (struct ohci_hcd *ohci); 88#endif 89 90#ifdef CONFIG_PCI 91static void sb800_prefetch(struct ohci_hcd *ohci, int on); 92#else 93static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) 94{ 95 return; 96} 97#endif 98 99 100#include "ohci-hub.c" 101#include "ohci-dbg.c" 102#include "ohci-mem.c" 103#include "ohci-q.c" 104 105 106/* 107 * On architectures with edge-triggered interrupts we must never return 108 * IRQ_NONE. 109 */ 110#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ 111#define IRQ_NOTMINE IRQ_HANDLED 112#else 113#define IRQ_NOTMINE IRQ_NONE 114#endif 115 116 117/* Some boards misreport power switching/overcurrent */ 118static bool distrust_firmware = 1; 119module_param (distrust_firmware, bool, 0); 120MODULE_PARM_DESC (distrust_firmware, 121 "true to distrust firmware power/overcurrent setup"); 122 123/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ 124static bool no_handshake = 0; 125module_param (no_handshake, bool, 0); 126MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); 127 128/*-------------------------------------------------------------------------*/ 129 130/* 131 * queue up an urb for anything except the root hub 132 */ 133static int ohci_urb_enqueue ( 134 struct usb_hcd *hcd, 135 struct urb *urb, 136 gfp_t mem_flags 137) { 138 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 139 struct ed *ed; 140 urb_priv_t *urb_priv; 141 unsigned int pipe = urb->pipe; 142 int i, size = 0; 143 unsigned long flags; 144 int retval = 0; 145 146#ifdef OHCI_VERBOSE_DEBUG 147 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); 148#endif 149 150 /* every endpoint has a ed, locate and maybe (re)initialize it */ 151 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) 152 return -ENOMEM; 153 154 /* for the private part of the URB we need the number of TDs (size) */ 155 switch (ed->type) { 156 case PIPE_CONTROL: 157 /* td_submit_urb() doesn't yet handle these */ 158 if (urb->transfer_buffer_length > 4096) 159 return -EMSGSIZE; 160 161 /* 1 TD for setup, 1 for ACK, plus ... */ 162 size = 2; 163 /* FALLTHROUGH */ 164 // case PIPE_INTERRUPT: 165 // case PIPE_BULK: 166 default: 167 /* one TD for every 4096 Bytes (can be up to 8K) */ 168 size += urb->transfer_buffer_length / 4096; 169 /* ... and for any remaining bytes ... */ 170 if ((urb->transfer_buffer_length % 4096) != 0) 171 size++; 172 /* ... and maybe a zero length packet to wrap it up */ 173 if (size == 0) 174 size++; 175 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 176 && (urb->transfer_buffer_length 177 % usb_maxpacket (urb->dev, pipe, 178 usb_pipeout (pipe))) == 0) 179 size++; 180 break; 181 case PIPE_ISOCHRONOUS: /* number of packets from URB */ 182 size = urb->number_of_packets; 183 break; 184 } 185 186 /* allocate the private part of the URB */ 187 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), 188 mem_flags); 189 if (!urb_priv) 190 return -ENOMEM; 191 INIT_LIST_HEAD (&urb_priv->pending); 192 urb_priv->length = size; 193 urb_priv->ed = ed; 194 195 /* allocate the TDs (deferring hash chain updates) */ 196 for (i = 0; i < size; i++) { 197 urb_priv->td [i] = td_alloc (ohci, mem_flags); 198 if (!urb_priv->td [i]) { 199 urb_priv->length = i; 200 urb_free_priv (ohci, urb_priv); 201 return -ENOMEM; 202 } 203 } 204 205 spin_lock_irqsave (&ohci->lock, flags); 206 207 /* don't submit to a dead HC */ 208 if (!HCD_HW_ACCESSIBLE(hcd)) { 209 retval = -ENODEV; 210 goto fail; 211 } 212 if (ohci->rh_state != OHCI_RH_RUNNING) { 213 retval = -ENODEV; 214 goto fail; 215 } 216 retval = usb_hcd_link_urb_to_ep(hcd, urb); 217 if (retval) 218 goto fail; 219 220 /* schedule the ed if needed */ 221 if (ed->state == ED_IDLE) { 222 retval = ed_schedule (ohci, ed); 223 if (retval < 0) { 224 usb_hcd_unlink_urb_from_ep(hcd, urb); 225 goto fail; 226 } 227 if (ed->type == PIPE_ISOCHRONOUS) { 228 u16 frame = ohci_frame_no(ohci); 229 230 /* delay a few frames before the first TD */ 231 frame += max_t (u16, 8, ed->interval); 232 frame &= ~(ed->interval - 1); 233 frame |= ed->branch; 234 urb->start_frame = frame; 235 236 /* yes, only URB_ISO_ASAP is supported, and 237 * urb->start_frame is never used as input. 238 */ 239 } 240 } else if (ed->type == PIPE_ISOCHRONOUS) 241 urb->start_frame = ed->last_iso + ed->interval; 242 243 /* fill the TDs and link them to the ed; and 244 * enable that part of the schedule, if needed 245 * and update count of queued periodic urbs 246 */ 247 urb->hcpriv = urb_priv; 248 td_submit_urb (ohci, urb); 249 250fail: 251 if (retval) 252 urb_free_priv (ohci, urb_priv); 253 spin_unlock_irqrestore (&ohci->lock, flags); 254 return retval; 255} 256 257/* 258 * decouple the URB from the HC queues (TDs, urb_priv). 259 * reporting is always done 260 * asynchronously, and we might be dealing with an urb that's 261 * partially transferred, or an ED with other urbs being unlinked. 262 */ 263static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 264{ 265 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 266 unsigned long flags; 267 int rc; 268 269#ifdef OHCI_VERBOSE_DEBUG 270 urb_print(urb, "UNLINK", 1, status); 271#endif 272 273 spin_lock_irqsave (&ohci->lock, flags); 274 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 275 if (rc) { 276 ; /* Do nothing */ 277 } else if (ohci->rh_state == OHCI_RH_RUNNING) { 278 urb_priv_t *urb_priv; 279 280 /* Unless an IRQ completed the unlink while it was being 281 * handed to us, flag it for unlink and giveback, and force 282 * some upcoming INTR_SF to call finish_unlinks() 283 */ 284 urb_priv = urb->hcpriv; 285 if (urb_priv) { 286 if (urb_priv->ed->state == ED_OPER) 287 start_ed_unlink (ohci, urb_priv->ed); 288 } 289 } else { 290 /* 291 * with HC dead, we won't respect hc queue pointers 292 * any more ... just clean up every urb's memory. 293 */ 294 if (urb->hcpriv) 295 finish_urb(ohci, urb, status); 296 } 297 spin_unlock_irqrestore (&ohci->lock, flags); 298 return rc; 299} 300 301/*-------------------------------------------------------------------------*/ 302 303/* frees config/altsetting state for endpoints, 304 * including ED memory, dummy TD, and bulk/intr data toggle 305 */ 306 307static void 308ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 309{ 310 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 311 unsigned long flags; 312 struct ed *ed = ep->hcpriv; 313 unsigned limit = 1000; 314 315 /* ASSERT: any requests/urbs are being unlinked */ 316 /* ASSERT: nobody can be submitting urbs for this any more */ 317 318 if (!ed) 319 return; 320 321rescan: 322 spin_lock_irqsave (&ohci->lock, flags); 323 324 if (ohci->rh_state != OHCI_RH_RUNNING) { 325sanitize: 326 ed->state = ED_IDLE; 327 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) 328 ohci->eds_scheduled--; 329 finish_unlinks (ohci, 0); 330 } 331 332 switch (ed->state) { 333 case ED_UNLINK: /* wait for hw to finish? */ 334 /* major IRQ delivery trouble loses INTR_SF too... */ 335 if (limit-- == 0) { 336 ohci_warn(ohci, "ED unlink timeout\n"); 337 if (quirk_zfmicro(ohci)) { 338 ohci_warn(ohci, "Attempting ZF TD recovery\n"); 339 ohci->ed_to_check = ed; 340 ohci->zf_delay = 2; 341 } 342 goto sanitize; 343 } 344 spin_unlock_irqrestore (&ohci->lock, flags); 345 schedule_timeout_uninterruptible(1); 346 goto rescan; 347 case ED_IDLE: /* fully unlinked */ 348 if (list_empty (&ed->td_list)) { 349 td_free (ohci, ed->dummy); 350 ed_free (ohci, ed); 351 break; 352 } 353 /* else FALL THROUGH */ 354 default: 355 /* caller was supposed to have unlinked any requests; 356 * that's not our job. can't recover; must leak ed. 357 */ 358 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", 359 ed, ep->desc.bEndpointAddress, ed->state, 360 list_empty (&ed->td_list) ? "" : " (has tds)"); 361 td_free (ohci, ed->dummy); 362 break; 363 } 364 ep->hcpriv = NULL; 365 spin_unlock_irqrestore (&ohci->lock, flags); 366} 367 368static int ohci_get_frame (struct usb_hcd *hcd) 369{ 370 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 371 372 return ohci_frame_no(ohci); 373} 374 375static void ohci_usb_reset (struct ohci_hcd *ohci) 376{ 377 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); 378 ohci->hc_control &= OHCI_CTRL_RWC; 379 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 380 ohci->rh_state = OHCI_RH_HALTED; 381} 382 383/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and 384 * other cases where the next software may expect clean state from the 385 * "firmware". this is bus-neutral, unlike shutdown() methods. 386 */ 387static void 388ohci_shutdown (struct usb_hcd *hcd) 389{ 390 struct ohci_hcd *ohci; 391 392 ohci = hcd_to_ohci (hcd); 393 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable); 394 395 /* Software reset, after which the controller goes into SUSPEND */ 396 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus); 397 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */ 398 udelay(10); 399 400 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval); 401} 402 403static int check_ed(struct ohci_hcd *ohci, struct ed *ed) 404{ 405 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 406 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) 407 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) 408 && !list_empty(&ed->td_list); 409} 410 411/* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes 412 * an interrupt TD but neglects to add it to the donelist. On systems with 413 * this chipset, we need to periodically check the state of the queues to look 414 * for such "lost" TDs. 415 */ 416static void unlink_watchdog_func(unsigned long _ohci) 417{ 418 unsigned long flags; 419 unsigned max; 420 unsigned seen_count = 0; 421 unsigned i; 422 struct ed **seen = NULL; 423 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; 424 425 spin_lock_irqsave(&ohci->lock, flags); 426 max = ohci->eds_scheduled; 427 if (!max) 428 goto done; 429 430 if (ohci->ed_to_check) 431 goto out; 432 433 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); 434 if (!seen) 435 goto out; 436 437 for (i = 0; i < NUM_INTS; i++) { 438 struct ed *ed = ohci->periodic[i]; 439 440 while (ed) { 441 unsigned temp; 442 443 /* scan this branch of the periodic schedule tree */ 444 for (temp = 0; temp < seen_count; temp++) { 445 if (seen[temp] == ed) { 446 /* we've checked it and what's after */ 447 ed = NULL; 448 break; 449 } 450 } 451 if (!ed) 452 break; 453 seen[seen_count++] = ed; 454 if (!check_ed(ohci, ed)) { 455 ed = ed->ed_next; 456 continue; 457 } 458 459 /* HC's TD list is empty, but HCD sees at least one 460 * TD that's not been sent through the donelist. 461 */ 462 ohci->ed_to_check = ed; 463 ohci->zf_delay = 2; 464 465 /* The HC may wait until the next frame to report the 466 * TD as done through the donelist and INTR_WDH. (We 467 * just *assume* it's not a multi-TD interrupt URB; 468 * those could defer the IRQ more than one frame, using 469 * DI...) Check again after the next INTR_SF. 470 */ 471 ohci_writel(ohci, OHCI_INTR_SF, 472 &ohci->regs->intrstatus); 473 ohci_writel(ohci, OHCI_INTR_SF, 474 &ohci->regs->intrenable); 475 476 /* flush those writes */ 477 (void) ohci_readl(ohci, &ohci->regs->control); 478 479 goto out; 480 } 481 } 482out: 483 kfree(seen); 484 if (ohci->eds_scheduled) 485 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); 486done: 487 spin_unlock_irqrestore(&ohci->lock, flags); 488} 489 490/*-------------------------------------------------------------------------* 491 * HC functions 492 *-------------------------------------------------------------------------*/ 493 494/* init memory, and kick BIOS/SMM off */ 495 496static int ohci_init (struct ohci_hcd *ohci) 497{ 498 int ret; 499 struct usb_hcd *hcd = ohci_to_hcd(ohci); 500 501 if (distrust_firmware) 502 ohci->flags |= OHCI_QUIRK_HUB_POWER; 503 504 ohci->rh_state = OHCI_RH_HALTED; 505 ohci->regs = hcd->regs; 506 507 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and 508 * was never needed for most non-PCI systems ... remove the code? 509 */ 510 511#ifndef IR_DISABLE 512 /* SMM owns the HC? not for long! */ 513 if (!no_handshake && ohci_readl (ohci, 514 &ohci->regs->control) & OHCI_CTRL_IR) { 515 u32 temp; 516 517 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); 518 519 /* this timeout is arbitrary. we make it long, so systems 520 * depending on usb keyboards may be usable even if the 521 * BIOS/SMM code seems pretty broken. 522 */ 523 temp = 500; /* arbitrary: five seconds */ 524 525 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); 526 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); 527 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { 528 msleep (10); 529 if (--temp == 0) { 530 ohci_err (ohci, "USB HC takeover failed!" 531 " (BIOS/SMM bug)\n"); 532 return -EBUSY; 533 } 534 } 535 ohci_usb_reset (ohci); 536 } 537#endif 538 539 /* Disable HC interrupts */ 540 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 541 542 /* flush the writes, and save key bits like RWC */ 543 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) 544 ohci->hc_control |= OHCI_CTRL_RWC; 545 546 /* Read the number of ports unless overridden */ 547 if (ohci->num_ports == 0) 548 ohci->num_ports = roothub_a(ohci) & RH_A_NDP; 549 550 if (ohci->hcca) 551 return 0; 552 553 ohci->hcca = dma_alloc_coherent (hcd->self.controller, 554 sizeof *ohci->hcca, &ohci->hcca_dma, 0); 555 if (!ohci->hcca) 556 return -ENOMEM; 557 558 if ((ret = ohci_mem_init (ohci)) < 0) 559 ohci_stop (hcd); 560 else { 561 create_debug_files (ohci); 562 } 563 564 return ret; 565} 566 567/*-------------------------------------------------------------------------*/ 568 569/* Start an OHCI controller, set the BUS operational 570 * resets USB and controller 571 * enable interrupts 572 */ 573static int ohci_run (struct ohci_hcd *ohci) 574{ 575 u32 mask, val; 576 int first = ohci->fminterval == 0; 577 struct usb_hcd *hcd = ohci_to_hcd(ohci); 578 579 ohci->rh_state = OHCI_RH_HALTED; 580 581 /* boot firmware should have set this up (5.1.1.3.1) */ 582 if (first) { 583 584 val = ohci_readl (ohci, &ohci->regs->fminterval); 585 ohci->fminterval = val & 0x3fff; 586 if (ohci->fminterval != FI) 587 ohci_dbg (ohci, "fminterval delta %d\n", 588 ohci->fminterval - FI); 589 ohci->fminterval |= FSMP (ohci->fminterval) << 16; 590 /* also: power/overcurrent flags in roothub.a */ 591 } 592 593 /* Reset USB nearly "by the book". RemoteWakeupConnected has 594 * to be checked in case boot firmware (BIOS/SMM/...) has set up 595 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). 596 * If the bus glue detected wakeup capability then it should 597 * already be enabled; if so we'll just enable it again. 598 */ 599 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) 600 device_set_wakeup_capable(hcd->self.controller, 1); 601 602 switch (ohci->hc_control & OHCI_CTRL_HCFS) { 603 case OHCI_USB_OPER: 604 val = 0; 605 break; 606 case OHCI_USB_SUSPEND: 607 case OHCI_USB_RESUME: 608 ohci->hc_control &= OHCI_CTRL_RWC; 609 ohci->hc_control |= OHCI_USB_RESUME; 610 val = 10 /* msec wait */; 611 break; 612 // case OHCI_USB_RESET: 613 default: 614 ohci->hc_control &= OHCI_CTRL_RWC; 615 ohci->hc_control |= OHCI_USB_RESET; 616 val = 50 /* msec wait */; 617 break; 618 } 619 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 620 // flush the writes 621 (void) ohci_readl (ohci, &ohci->regs->control); 622 msleep(val); 623 624 memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); 625 626 /* 2msec timelimit here means no irqs/preempt */ 627 spin_lock_irq (&ohci->lock); 628 629retry: 630 /* HC Reset requires max 10 us delay */ 631 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); 632 val = 30; /* ... allow extra time */ 633 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 634 if (--val == 0) { 635 spin_unlock_irq (&ohci->lock); 636 ohci_err (ohci, "USB HC reset timed out!\n"); 637 return -1; 638 } 639 udelay (1); 640 } 641 642 /* now we're in the SUSPEND state ... must go OPERATIONAL 643 * within 2msec else HC enters RESUME 644 * 645 * ... but some hardware won't init fmInterval "by the book" 646 * (SiS, OPTi ...), so reset again instead. SiS doesn't need 647 * this if we write fmInterval after we're OPERATIONAL. 648 * Unclear about ALi, ServerWorks, and others ... this could 649 * easily be a longstanding bug in chip init on Linux. 650 */ 651 if (ohci->flags & OHCI_QUIRK_INITRESET) { 652 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 653 // flush those writes 654 (void) ohci_readl (ohci, &ohci->regs->control); 655 } 656 657 /* Tell the controller where the control and bulk lists are 658 * The lists are empty now. */ 659 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); 660 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); 661 662 /* a reset clears this */ 663 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); 664 665 periodic_reinit (ohci); 666 667 /* some OHCI implementations are finicky about how they init. 668 * bogus values here mean not even enumeration could work. 669 */ 670 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 671 || !ohci_readl (ohci, &ohci->regs->periodicstart)) { 672 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { 673 ohci->flags |= OHCI_QUIRK_INITRESET; 674 ohci_dbg (ohci, "enabling initreset quirk\n"); 675 goto retry; 676 } 677 spin_unlock_irq (&ohci->lock); 678 ohci_err (ohci, "init err (%08x %04x)\n", 679 ohci_readl (ohci, &ohci->regs->fminterval), 680 ohci_readl (ohci, &ohci->regs->periodicstart)); 681 return -EOVERFLOW; 682 } 683 684 /* use rhsc irqs after khubd is fully initialized */ 685 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 686 hcd->uses_new_polling = 1; 687 688 /* start controller operations */ 689 ohci->hc_control &= OHCI_CTRL_RWC; 690 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; 691 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 692 ohci->rh_state = OHCI_RH_RUNNING; 693 694 /* wake on ConnectStatusChange, matching external hubs */ 695 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); 696 697 /* Choose the interrupts we care about now, others later on demand */ 698 mask = OHCI_INTR_INIT; 699 ohci_writel (ohci, ~0, &ohci->regs->intrstatus); 700 ohci_writel (ohci, mask, &ohci->regs->intrenable); 701 702 /* handle root hub init quirks ... */ 703 val = roothub_a (ohci); 704 val &= ~(RH_A_PSM | RH_A_OCPM); 705 if (ohci->flags & OHCI_QUIRK_SUPERIO) { 706 /* NSC 87560 and maybe others */ 707 val |= RH_A_NOCP; 708 val &= ~(RH_A_POTPGT | RH_A_NPS); 709 ohci_writel (ohci, val, &ohci->regs->roothub.a); 710 } else if ((ohci->flags & OHCI_QUIRK_AMD756) || 711 (ohci->flags & OHCI_QUIRK_HUB_POWER)) { 712 /* hub power always on; required for AMD-756 and some 713 * Mac platforms. ganged overcurrent reporting, if any. 714 */ 715 val |= RH_A_NPS; 716 ohci_writel (ohci, val, &ohci->regs->roothub.a); 717 } 718 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); 719 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, 720 &ohci->regs->roothub.b); 721 // flush those writes 722 (void) ohci_readl (ohci, &ohci->regs->control); 723 724 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 725 spin_unlock_irq (&ohci->lock); 726 727 // POTPGT delay is bits 24-31, in 2 ms units. 728 mdelay ((val >> 23) & 0x1fe); 729 730 if (quirk_zfmicro(ohci)) { 731 /* Create timer to watch for bad queue state on ZF Micro */ 732 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, 733 (unsigned long) ohci); 734 735 ohci->eds_scheduled = 0; 736 ohci->ed_to_check = NULL; 737 } 738 739 ohci_dump (ohci, 1); 740 741 return 0; 742} 743 744/*-------------------------------------------------------------------------*/ 745 746/* an interrupt happens */ 747 748static irqreturn_t ohci_irq (struct usb_hcd *hcd) 749{ 750 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 751 struct ohci_regs __iomem *regs = ohci->regs; 752 int ints; 753 754 /* Read interrupt status (and flush pending writes). We ignore the 755 * optimization of checking the LSB of hcca->done_head; it doesn't 756 * work on all systems (edge triggering for OHCI can be a factor). 757 */ 758 ints = ohci_readl(ohci, ®s->intrstatus); 759 760 /* Check for an all 1's result which is a typical consequence 761 * of dead, unclocked, or unplugged (CardBus...) devices 762 */ 763 if (ints == ~(u32)0) { 764 ohci->rh_state = OHCI_RH_HALTED; 765 ohci_dbg (ohci, "device removed!\n"); 766 usb_hc_died(hcd); 767 return IRQ_HANDLED; 768 } 769 770 /* We only care about interrupts that are enabled */ 771 ints &= ohci_readl(ohci, ®s->intrenable); 772 773 /* interrupt for some other device? */ 774 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED)) 775 return IRQ_NOTMINE; 776 777 if (ints & OHCI_INTR_UE) { 778 // e.g. due to PCI Master/Target Abort 779 if (quirk_nec(ohci)) { 780 /* Workaround for a silicon bug in some NEC chips used 781 * in Apple's PowerBooks. Adapted from Darwin code. 782 */ 783 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); 784 785 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); 786 787 schedule_work (&ohci->nec_work); 788 } else { 789 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); 790 ohci->rh_state = OHCI_RH_HALTED; 791 usb_hc_died(hcd); 792 } 793 794 ohci_dump (ohci, 1); 795 ohci_usb_reset (ohci); 796 } 797 798 if (ints & OHCI_INTR_RHSC) { 799 ohci_vdbg(ohci, "rhsc\n"); 800 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 801 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, 802 ®s->intrstatus); 803 804 /* NOTE: Vendors didn't always make the same implementation 805 * choices for RHSC. Many followed the spec; RHSC triggers 806 * on an edge, like setting and maybe clearing a port status 807 * change bit. With others it's level-triggered, active 808 * until khubd clears all the port status change bits. We'll 809 * always disable it here and rely on polling until khubd 810 * re-enables it. 811 */ 812 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); 813 usb_hcd_poll_rh_status(hcd); 814 } 815 816 /* For connect and disconnect events, we expect the controller 817 * to turn on RHSC along with RD. But for remote wakeup events 818 * this might not happen. 819 */ 820 else if (ints & OHCI_INTR_RD) { 821 ohci_vdbg(ohci, "resume detect\n"); 822 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); 823 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 824 if (ohci->autostop) { 825 spin_lock (&ohci->lock); 826 ohci_rh_resume (ohci); 827 spin_unlock (&ohci->lock); 828 } else 829 usb_hcd_resume_root_hub(hcd); 830 } 831 832 if (ints & OHCI_INTR_WDH) { 833 spin_lock (&ohci->lock); 834 dl_done_list (ohci); 835 spin_unlock (&ohci->lock); 836 } 837 838 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { 839 spin_lock(&ohci->lock); 840 if (ohci->ed_to_check) { 841 struct ed *ed = ohci->ed_to_check; 842 843 if (check_ed(ohci, ed)) { 844 /* HC thinks the TD list is empty; HCD knows 845 * at least one TD is outstanding 846 */ 847 if (--ohci->zf_delay == 0) { 848 struct td *td = list_entry( 849 ed->td_list.next, 850 struct td, td_list); 851 ohci_warn(ohci, 852 "Reclaiming orphan TD %p\n", 853 td); 854 takeback_td(ohci, td); 855 ohci->ed_to_check = NULL; 856 } 857 } else 858 ohci->ed_to_check = NULL; 859 } 860 spin_unlock(&ohci->lock); 861 } 862 863 /* could track INTR_SO to reduce available PCI/... bandwidth */ 864 865 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled 866 * when there's still unlinking to be done (next frame). 867 */ 868 spin_lock (&ohci->lock); 869 if (ohci->ed_rm_list) 870 finish_unlinks (ohci, ohci_frame_no(ohci)); 871 if ((ints & OHCI_INTR_SF) != 0 872 && !ohci->ed_rm_list 873 && !ohci->ed_to_check 874 && ohci->rh_state == OHCI_RH_RUNNING) 875 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); 876 spin_unlock (&ohci->lock); 877 878 if (ohci->rh_state == OHCI_RH_RUNNING) { 879 ohci_writel (ohci, ints, ®s->intrstatus); 880 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); 881 // flush those writes 882 (void) ohci_readl (ohci, &ohci->regs->control); 883 } 884 885 return IRQ_HANDLED; 886} 887 888/*-------------------------------------------------------------------------*/ 889 890static void ohci_stop (struct usb_hcd *hcd) 891{ 892 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 893 894 ohci_dump (ohci, 1); 895 896 if (quirk_nec(ohci)) 897 flush_work_sync(&ohci->nec_work); 898 899 ohci_usb_reset (ohci); 900 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 901 free_irq(hcd->irq, hcd); 902 hcd->irq = -1; 903 904 if (quirk_zfmicro(ohci)) 905 del_timer(&ohci->unlink_watchdog); 906 if (quirk_amdiso(ohci)) 907 usb_amd_dev_put(); 908 909 remove_debug_files (ohci); 910 ohci_mem_cleanup (ohci); 911 if (ohci->hcca) { 912 dma_free_coherent (hcd->self.controller, 913 sizeof *ohci->hcca, 914 ohci->hcca, ohci->hcca_dma); 915 ohci->hcca = NULL; 916 ohci->hcca_dma = 0; 917 } 918} 919 920/*-------------------------------------------------------------------------*/ 921 922#if defined(CONFIG_PM) || defined(CONFIG_PCI) 923 924/* must not be called from interrupt context */ 925static int ohci_restart (struct ohci_hcd *ohci) 926{ 927 int temp; 928 int i; 929 struct urb_priv *priv; 930 931 spin_lock_irq(&ohci->lock); 932 ohci->rh_state = OHCI_RH_HALTED; 933 934 /* Recycle any "live" eds/tds (and urbs). */ 935 if (!list_empty (&ohci->pending)) 936 ohci_dbg(ohci, "abort schedule...\n"); 937 list_for_each_entry (priv, &ohci->pending, pending) { 938 struct urb *urb = priv->td[0]->urb; 939 struct ed *ed = priv->ed; 940 941 switch (ed->state) { 942 case ED_OPER: 943 ed->state = ED_UNLINK; 944 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); 945 ed_deschedule (ohci, ed); 946 947 ed->ed_next = ohci->ed_rm_list; 948 ed->ed_prev = NULL; 949 ohci->ed_rm_list = ed; 950 /* FALLTHROUGH */ 951 case ED_UNLINK: 952 break; 953 default: 954 ohci_dbg(ohci, "bogus ed %p state %d\n", 955 ed, ed->state); 956 } 957 958 if (!urb->unlinked) 959 urb->unlinked = -ESHUTDOWN; 960 } 961 finish_unlinks (ohci, 0); 962 spin_unlock_irq(&ohci->lock); 963 964 /* paranoia, in case that didn't work: */ 965 966 /* empty the interrupt branches */ 967 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; 968 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; 969 970 /* no EDs to remove */ 971 ohci->ed_rm_list = NULL; 972 973 /* empty control and bulk lists */ 974 ohci->ed_controltail = NULL; 975 ohci->ed_bulktail = NULL; 976 977 if ((temp = ohci_run (ohci)) < 0) { 978 ohci_err (ohci, "can't restart, %d\n", temp); 979 return temp; 980 } 981 ohci_dbg(ohci, "restart complete\n"); 982 return 0; 983} 984 985#endif 986 987/*-------------------------------------------------------------------------*/ 988 989MODULE_AUTHOR (DRIVER_AUTHOR); 990MODULE_DESCRIPTION(DRIVER_DESC); 991MODULE_LICENSE ("GPL"); 992 993#ifdef CONFIG_PCI 994#include "ohci-pci.c" 995#define PCI_DRIVER ohci_pci_driver 996#endif 997 998#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) 999#include "ohci-sa1111.c" 1000#define SA1111_DRIVER ohci_hcd_sa1111_driver 1001#endif 1002 1003#if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) 1004#include "ohci-s3c2410.c" 1005#define PLATFORM_DRIVER ohci_hcd_s3c2410_driver 1006#endif 1007 1008#ifdef CONFIG_USB_OHCI_EXYNOS 1009#include "ohci-exynos.c" 1010#define PLATFORM_DRIVER exynos_ohci_driver 1011#endif 1012 1013#ifdef CONFIG_USB_OHCI_HCD_OMAP1 1014#include "ohci-omap.c" 1015#define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver 1016#endif 1017 1018#ifdef CONFIG_USB_OHCI_HCD_OMAP3 1019#include "ohci-omap3.c" 1020#define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver 1021#endif 1022 1023#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 1024#include "ohci-pxa27x.c" 1025#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver 1026#endif 1027 1028#ifdef CONFIG_ARCH_EP93XX 1029#include "ohci-ep93xx.c" 1030#define PLATFORM_DRIVER ohci_hcd_ep93xx_driver 1031#endif 1032 1033#ifdef CONFIG_MIPS_ALCHEMY 1034#include "ohci-au1xxx.c" 1035#define PLATFORM_DRIVER ohci_hcd_au1xxx_driver 1036#endif 1037 1038#ifdef CONFIG_PNX8550 1039#include "ohci-pnx8550.c" 1040#define PLATFORM_DRIVER ohci_hcd_pnx8550_driver 1041#endif 1042 1043#ifdef CONFIG_USB_OHCI_HCD_PPC_SOC 1044#include "ohci-ppc-soc.c" 1045#define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver 1046#endif 1047 1048#ifdef CONFIG_ARCH_AT91 1049#include "ohci-at91.c" 1050#define PLATFORM_DRIVER ohci_hcd_at91_driver 1051#endif 1052 1053#ifdef CONFIG_ARCH_PNX4008 1054#include "ohci-pnx4008.c" 1055#define PLATFORM_DRIVER usb_hcd_pnx4008_driver 1056#endif 1057 1058#ifdef CONFIG_ARCH_DAVINCI_DA8XX 1059#include "ohci-da8xx.c" 1060#define PLATFORM_DRIVER ohci_hcd_da8xx_driver 1061#endif 1062 1063#ifdef CONFIG_USB_OHCI_SH 1064#include "ohci-sh.c" 1065#define PLATFORM_DRIVER ohci_hcd_sh_driver 1066#endif 1067 1068 1069#ifdef CONFIG_USB_OHCI_HCD_PPC_OF 1070#include "ohci-ppc-of.c" 1071#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver 1072#endif 1073 1074#ifdef CONFIG_PLAT_SPEAR 1075#include "ohci-spear.c" 1076#define PLATFORM_DRIVER spear_ohci_hcd_driver 1077#endif 1078 1079#ifdef CONFIG_PPC_PS3 1080#include "ohci-ps3.c" 1081#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver 1082#endif 1083 1084#ifdef CONFIG_USB_OHCI_HCD_SSB 1085#include "ohci-ssb.c" 1086#define SSB_OHCI_DRIVER ssb_ohci_driver 1087#endif 1088 1089#ifdef CONFIG_MFD_SM501 1090#include "ohci-sm501.c" 1091#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver 1092#endif 1093 1094#ifdef CONFIG_MFD_TC6393XB 1095#include "ohci-tmio.c" 1096#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver 1097#endif 1098 1099#ifdef CONFIG_MACH_JZ4740 1100#include "ohci-jz4740.c" 1101#define PLATFORM_DRIVER ohci_hcd_jz4740_driver 1102#endif 1103 1104#ifdef CONFIG_USB_OCTEON_OHCI 1105#include "ohci-octeon.c" 1106#define PLATFORM_DRIVER ohci_octeon_driver 1107#endif 1108 1109#ifdef CONFIG_USB_CNS3XXX_OHCI 1110#include "ohci-cns3xxx.c" 1111#define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver 1112#endif 1113 1114#ifdef CONFIG_USB_OHCI_ATH79 1115#include "ohci-ath79.c" 1116#define PLATFORM_DRIVER ohci_hcd_ath79_driver 1117#endif 1118 1119#ifdef CONFIG_CPU_XLR 1120#include "ohci-xls.c" 1121#define PLATFORM_DRIVER ohci_xls_driver 1122#endif 1123 1124#if !defined(PCI_DRIVER) && \ 1125 !defined(PLATFORM_DRIVER) && \ 1126 !defined(OMAP1_PLATFORM_DRIVER) && \ 1127 !defined(OMAP3_PLATFORM_DRIVER) && \ 1128 !defined(OF_PLATFORM_DRIVER) && \ 1129 !defined(SA1111_DRIVER) && \ 1130 !defined(PS3_SYSTEM_BUS_DRIVER) && \ 1131 !defined(SM501_OHCI_DRIVER) && \ 1132 !defined(TMIO_OHCI_DRIVER) && \ 1133 !defined(SSB_OHCI_DRIVER) 1134#error "missing bus glue for ohci-hcd" 1135#endif 1136 1137static int __init ohci_hcd_mod_init(void) 1138{ 1139 int retval = 0; 1140 1141 if (usb_disabled()) 1142 return -ENODEV; 1143 1144 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1145 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, 1146 sizeof (struct ed), sizeof (struct td)); 1147 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1148 1149#ifdef DEBUG 1150 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); 1151 if (!ohci_debug_root) { 1152 retval = -ENOENT; 1153 goto error_debug; 1154 } 1155#endif 1156 1157#ifdef PS3_SYSTEM_BUS_DRIVER 1158 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1159 if (retval < 0) 1160 goto error_ps3; 1161#endif 1162 1163#ifdef PLATFORM_DRIVER 1164 retval = platform_driver_register(&PLATFORM_DRIVER); 1165 if (retval < 0) 1166 goto error_platform; 1167#endif 1168 1169#ifdef OMAP1_PLATFORM_DRIVER 1170 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER); 1171 if (retval < 0) 1172 goto error_omap1_platform; 1173#endif 1174 1175#ifdef OMAP3_PLATFORM_DRIVER 1176 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER); 1177 if (retval < 0) 1178 goto error_omap3_platform; 1179#endif 1180 1181#ifdef OF_PLATFORM_DRIVER 1182 retval = platform_driver_register(&OF_PLATFORM_DRIVER); 1183 if (retval < 0) 1184 goto error_of_platform; 1185#endif 1186 1187#ifdef SA1111_DRIVER 1188 retval = sa1111_driver_register(&SA1111_DRIVER); 1189 if (retval < 0) 1190 goto error_sa1111; 1191#endif 1192 1193#ifdef PCI_DRIVER 1194 retval = pci_register_driver(&PCI_DRIVER); 1195 if (retval < 0) 1196 goto error_pci; 1197#endif 1198 1199#ifdef SSB_OHCI_DRIVER 1200 retval = ssb_driver_register(&SSB_OHCI_DRIVER); 1201 if (retval) 1202 goto error_ssb; 1203#endif 1204 1205#ifdef SM501_OHCI_DRIVER 1206 retval = platform_driver_register(&SM501_OHCI_DRIVER); 1207 if (retval < 0) 1208 goto error_sm501; 1209#endif 1210 1211#ifdef TMIO_OHCI_DRIVER 1212 retval = platform_driver_register(&TMIO_OHCI_DRIVER); 1213 if (retval < 0) 1214 goto error_tmio; 1215#endif 1216 1217 return retval; 1218 1219 /* Error path */ 1220#ifdef TMIO_OHCI_DRIVER 1221 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1222 error_tmio: 1223#endif 1224#ifdef SM501_OHCI_DRIVER 1225 platform_driver_unregister(&SM501_OHCI_DRIVER); 1226 error_sm501: 1227#endif 1228#ifdef SSB_OHCI_DRIVER 1229 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1230 error_ssb: 1231#endif 1232#ifdef PCI_DRIVER 1233 pci_unregister_driver(&PCI_DRIVER); 1234 error_pci: 1235#endif 1236#ifdef SA1111_DRIVER 1237 sa1111_driver_unregister(&SA1111_DRIVER); 1238 error_sa1111: 1239#endif 1240#ifdef OF_PLATFORM_DRIVER 1241 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1242 error_of_platform: 1243#endif 1244#ifdef PLATFORM_DRIVER 1245 platform_driver_unregister(&PLATFORM_DRIVER); 1246 error_platform: 1247#endif 1248#ifdef OMAP1_PLATFORM_DRIVER 1249 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER); 1250 error_omap1_platform: 1251#endif 1252#ifdef OMAP3_PLATFORM_DRIVER 1253 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); 1254 error_omap3_platform: 1255#endif 1256#ifdef PS3_SYSTEM_BUS_DRIVER 1257 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1258 error_ps3: 1259#endif 1260#ifdef DEBUG 1261 debugfs_remove(ohci_debug_root); 1262 ohci_debug_root = NULL; 1263 error_debug: 1264#endif 1265 1266 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1267 return retval; 1268} 1269module_init(ohci_hcd_mod_init); 1270 1271static void __exit ohci_hcd_mod_exit(void) 1272{ 1273#ifdef TMIO_OHCI_DRIVER 1274 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1275#endif 1276#ifdef SM501_OHCI_DRIVER 1277 platform_driver_unregister(&SM501_OHCI_DRIVER); 1278#endif 1279#ifdef SSB_OHCI_DRIVER 1280 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1281#endif 1282#ifdef PCI_DRIVER 1283 pci_unregister_driver(&PCI_DRIVER); 1284#endif 1285#ifdef SA1111_DRIVER 1286 sa1111_driver_unregister(&SA1111_DRIVER); 1287#endif 1288#ifdef OF_PLATFORM_DRIVER 1289 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1290#endif 1291#ifdef PLATFORM_DRIVER 1292 platform_driver_unregister(&PLATFORM_DRIVER); 1293#endif 1294#ifdef OMAP3_PLATFORM_DRIVER 1295 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); 1296#endif 1297#ifdef PS3_SYSTEM_BUS_DRIVER 1298 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1299#endif 1300#ifdef DEBUG 1301 debugfs_remove(ohci_debug_root); 1302#endif 1303 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1304} 1305module_exit(ohci_hcd_mod_exit); 1306 1307