1/* 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 4 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public 7 * License as published by the Free Software Foundation; 8 * either version 2, or (at your option) any later version. 9 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even 12 * the implied warranty of MERCHANTABILITY or FITNESS FOR 13 * A PARTICULAR PURPOSE.See the GNU General Public License 14 * for more details. 15 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21#include <linux/via-core.h> 22#include <linux/via_i2c.h> 23#include "global.h" 24 25static void tmds_register_write(int index, u8 data); 26static int tmds_register_read(int index); 27static int tmds_register_read_bytes(int index, u8 *buff, int buff_len); 28static void __devinit dvi_get_panel_size_from_DDCv1( 29 struct tmds_chip_information *tmds_chip, 30 struct tmds_setting_information *tmds_setting); 31static int viafb_dvi_query_EDID(void); 32 33static inline bool check_tmds_chip(int device_id_subaddr, int device_id) 34{ 35 return tmds_register_read(device_id_subaddr) == device_id; 36} 37 38void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, 39 struct tmds_setting_information *tmds_setting) 40{ 41 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n"); 42 43 viafb_dvi_sense(); 44 if (viafb_dvi_query_EDID() == 1) 45 dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting); 46 47 return; 48} 49 50bool __devinit viafb_tmds_trasmitter_identify(void) 51{ 52 unsigned char sr2a = 0, sr1e = 0, sr3e = 0; 53 54 /* Turn on ouputting pad */ 55 switch (viaparinfo->chip_info->gfx_chip_name) { 56 case UNICHROME_K8M890: 57 /*=* DFP Low Pad on *=*/ 58 sr2a = viafb_read_reg(VIASR, SR2A); 59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); 60 break; 61 62 case UNICHROME_P4M900: 63 case UNICHROME_P4M890: 64 /* DFP Low Pad on */ 65 sr2a = viafb_read_reg(VIASR, SR2A); 66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); 67 /* DVP0 Pad on */ 68 sr1e = viafb_read_reg(VIASR, SR1E); 69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); 70 break; 71 72 default: 73 /* DVP0/DVP1 Pad on */ 74 sr1e = viafb_read_reg(VIASR, SR1E); 75 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + 76 BIT5 + BIT6 + BIT7); 77 /* SR3E[1]Multi-function selection: 78 0 = Emulate I2C and DDC bus by GPIO2/3/4. */ 79 sr3e = viafb_read_reg(VIASR, SR3E); 80 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); 81 break; 82 } 83 84 /* Check for VT1632: */ 85 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS; 86 viaparinfo->chip_info-> 87 tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR; 88 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31; 89 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) { 90 /* 91 * Currently only support 12bits,dual edge,add 24bits mode later 92 */ 93 tmds_register_write(0x08, 0x3b); 94 95 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n"); 96 DEBUG_MSG(KERN_INFO "\n %2d", 97 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); 98 DEBUG_MSG(KERN_INFO "\n %2d", 99 viaparinfo->chip_info->tmds_chip_info.i2c_port); 100 return true; 101 } else { 102 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_2C; 103 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) { 104 tmds_register_write(0x08, 0x3b); 105 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n"); 106 DEBUG_MSG(KERN_INFO "\n %2d", 107 viaparinfo->chip_info-> 108 tmds_chip_info.tmds_chip_name); 109 DEBUG_MSG(KERN_INFO "\n %2d", 110 viaparinfo->chip_info-> 111 tmds_chip_info.i2c_port); 112 return true; 113 } 114 } 115 116 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS; 117 118 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) && 119 ((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) || 120 (viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) { 121 DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n"); 122 return true; 123 } 124 125 switch (viaparinfo->chip_info->gfx_chip_name) { 126 case UNICHROME_K8M890: 127 viafb_write_reg(SR2A, VIASR, sr2a); 128 break; 129 130 case UNICHROME_P4M900: 131 case UNICHROME_P4M890: 132 viafb_write_reg(SR2A, VIASR, sr2a); 133 viafb_write_reg(SR1E, VIASR, sr1e); 134 break; 135 136 default: 137 viafb_write_reg(SR1E, VIASR, sr1e); 138 viafb_write_reg(SR3E, VIASR, sr3e); 139 break; 140 } 141 142 viaparinfo->chip_info-> 143 tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER; 144 viaparinfo->chip_info->tmds_chip_info. 145 tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR; 146 return false; 147} 148 149static void tmds_register_write(int index, u8 data) 150{ 151 viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.i2c_port, 152 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr, 153 index, data); 154} 155 156static int tmds_register_read(int index) 157{ 158 u8 data; 159 160 viafb_i2c_readbyte(viaparinfo->chip_info->tmds_chip_info.i2c_port, 161 (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr, 162 (u8) index, &data); 163 return data; 164} 165 166static int tmds_register_read_bytes(int index, u8 *buff, int buff_len) 167{ 168 viafb_i2c_readbytes(viaparinfo->chip_info->tmds_chip_info.i2c_port, 169 (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr, 170 (u8) index, buff, buff_len); 171 return 0; 172} 173 174/* DVI Set Mode */ 175void viafb_dvi_set_mode(const struct fb_var_screeninfo *var, int iga) 176{ 177 struct fb_var_screeninfo dvi_var = *var; 178 struct crt_mode_table *rb_mode; 179 int maxPixelClock; 180 181 maxPixelClock = viaparinfo->shared->tmds_setting_info.max_pixel_clock; 182 if (maxPixelClock && PICOS2KHZ(var->pixclock) / 1000 > maxPixelClock) { 183 rb_mode = viafb_get_best_rb_mode(var->xres, var->yres, 60); 184 if (rb_mode) 185 viafb_fill_var_timing_info(&dvi_var, rb_mode); 186 } 187 188 viafb_fill_crtc_timing(&dvi_var, iga); 189} 190 191/* Sense DVI Connector */ 192int viafb_dvi_sense(void) 193{ 194 u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0, 195 RegCR93 = 0, RegCR9B = 0, data; 196 int ret = false; 197 198 DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n"); 199 200 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { 201 /* DI1 Pad on */ 202 RegSR1E = viafb_read_reg(VIASR, SR1E); 203 viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30); 204 205 /* CR6B[0]VCK Input Selection: 1 = External clock. */ 206 RegCR6B = viafb_read_reg(VIACR, CR6B); 207 viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08); 208 209 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off 210 [0] Software Control Power Sequence */ 211 RegCR91 = viafb_read_reg(VIACR, CR91); 212 viafb_write_reg(CR91, VIACR, 0x1D); 213 214 /* CR93[7] DI1 Data Source Selection: 1 = DSP2. 215 CR93[5] DI1 Clock Source: 1 = internal. 216 CR93[4] DI1 Clock Polarity. 217 CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */ 218 RegCR93 = viafb_read_reg(VIACR, CR93); 219 viafb_write_reg(CR93, VIACR, 0x01); 220 } else { 221 /* DVP0/DVP1 Pad on */ 222 RegSR1E = viafb_read_reg(VIASR, SR1E); 223 viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0); 224 225 /* SR3E[1]Multi-function selection: 226 0 = Emulate I2C and DDC bus by GPIO2/3/4. */ 227 RegSR3E = viafb_read_reg(VIASR, SR3E); 228 viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20)); 229 230 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off 231 [0] Software Control Power Sequence */ 232 RegCR91 = viafb_read_reg(VIACR, CR91); 233 viafb_write_reg(CR91, VIACR, 0x1D); 234 235 /*CR9B[4] DVP1 Data Source Selection: 1 = From secondary 236 display.CR9B[2:0] DVP1 Clock Adjust */ 237 RegCR9B = viafb_read_reg(VIACR, CR9B); 238 viafb_write_reg(CR9B, VIACR, 0x01); 239 } 240 241 data = (u8) tmds_register_read(0x09); 242 if (data & 0x04) 243 ret = true; 244 245 if (ret == false) { 246 if (viafb_dvi_query_EDID()) 247 ret = true; 248 } 249 250 /* Restore status */ 251 viafb_write_reg(SR1E, VIASR, RegSR1E); 252 viafb_write_reg(CR91, VIACR, RegCR91); 253 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { 254 viafb_write_reg(CR6B, VIACR, RegCR6B); 255 viafb_write_reg(CR93, VIACR, RegCR93); 256 } else { 257 viafb_write_reg(SR3E, VIASR, RegSR3E); 258 viafb_write_reg(CR9B, VIACR, RegCR9B); 259 } 260 261 return ret; 262} 263 264/* Query Flat Panel's EDID Table Version Through DVI Connector */ 265static int viafb_dvi_query_EDID(void) 266{ 267 u8 data0, data1; 268 int restore; 269 270 DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n"); 271 272 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr; 273 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0; 274 275 data0 = (u8) tmds_register_read(0x00); 276 data1 = (u8) tmds_register_read(0x01); 277 if ((data0 == 0) && (data1 == 0xFF)) { 278 viaparinfo->chip_info-> 279 tmds_chip_info.tmds_chip_slave_addr = restore; 280 return EDID_VERSION_1; /* Found EDID1 Table */ 281 } 282 283 return false; 284} 285 286/* Get Panel Size Using EDID1 Table */ 287static void __devinit dvi_get_panel_size_from_DDCv1( 288 struct tmds_chip_information *tmds_chip, 289 struct tmds_setting_information *tmds_setting) 290{ 291 int i, restore; 292 unsigned char EDID_DATA[18]; 293 294 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n"); 295 296 restore = tmds_chip->tmds_chip_slave_addr; 297 tmds_chip->tmds_chip_slave_addr = 0xA0; 298 for (i = 0x25; i < 0x6D; i++) { 299 switch (i) { 300 case 0x36: 301 case 0x48: 302 case 0x5A: 303 case 0x6C: 304 tmds_register_read_bytes(i, EDID_DATA, 10); 305 if (!(EDID_DATA[0] || EDID_DATA[1])) { 306 /* The first two byte must be zero. */ 307 if (EDID_DATA[3] == 0xFD) { 308 /* To get max pixel clock. */ 309 tmds_setting->max_pixel_clock = 310 EDID_DATA[9] * 10; 311 } 312 } 313 break; 314 315 default: 316 break; 317 } 318 } 319 320 DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n", 321 tmds_setting->max_pixel_clock); 322 tmds_chip->tmds_chip_slave_addr = restore; 323} 324 325/* If Disable DVI, turn off pad */ 326void viafb_dvi_disable(void) 327{ 328 if (viaparinfo->chip_info-> 329 tmds_chip_info.output_interface == INTERFACE_TMDS) 330 /* Turn off TMDS power. */ 331 viafb_write_reg(CRD2, VIACR, 332 viafb_read_reg(VIACR, CRD2) | 0x08); 333} 334 335static void dvi_patch_skew_dvp0(void) 336{ 337 /* Reset data driving first: */ 338 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); 339 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); 340 341 switch (viaparinfo->chip_info->gfx_chip_name) { 342 case UNICHROME_P4M890: 343 { 344 if ((viaparinfo->tmds_setting_info->h_active == 1600) && 345 (viaparinfo->tmds_setting_info->v_active == 346 1200)) 347 viafb_write_reg_mask(CR96, VIACR, 0x03, 348 BIT0 + BIT1 + BIT2); 349 else 350 viafb_write_reg_mask(CR96, VIACR, 0x07, 351 BIT0 + BIT1 + BIT2); 352 break; 353 } 354 355 case UNICHROME_P4M900: 356 { 357 viafb_write_reg_mask(CR96, VIACR, 0x07, 358 BIT0 + BIT1 + BIT2 + BIT3); 359 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); 360 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); 361 break; 362 } 363 364 default: 365 { 366 break; 367 } 368 } 369} 370 371static void dvi_patch_skew_dvp_low(void) 372{ 373 switch (viaparinfo->chip_info->gfx_chip_name) { 374 case UNICHROME_K8M890: 375 { 376 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); 377 break; 378 } 379 380 case UNICHROME_P4M900: 381 { 382 viafb_write_reg_mask(CR99, VIACR, 0x08, 383 BIT0 + BIT1 + BIT2 + BIT3); 384 break; 385 } 386 387 case UNICHROME_P4M890: 388 { 389 viafb_write_reg_mask(CR99, VIACR, 0x0F, 390 BIT0 + BIT1 + BIT2 + BIT3); 391 break; 392 } 393 394 default: 395 { 396 break; 397 } 398 } 399} 400 401/* If Enable DVI, turn off pad */ 402void viafb_dvi_enable(void) 403{ 404 u8 data; 405 406 switch (viaparinfo->chip_info->tmds_chip_info.output_interface) { 407 case INTERFACE_DVP0: 408 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); 409 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); 410 dvi_patch_skew_dvp0(); 411 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 412 tmds_register_write(0x88, 0x3b); 413 else 414 /*clear CR91[5] to direct on display period 415 in the secondary diplay path */ 416 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); 417 break; 418 419 case INTERFACE_DVP1: 420 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 421 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); 422 423 /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */ 424 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 425 tmds_register_write(0x88, 0x3b); 426 else 427 /*clear CR91[5] to direct on display period 428 in the secondary diplay path */ 429 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); 430 431 /*fix DVI cannot enable on EPIA-M board */ 432 if (viafb_platform_epia_dvi == 1) { 433 viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f); 434 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); 435 if (viafb_bus_width == 24) { 436 if (viafb_device_lcd_dualedge == 1) 437 data = 0x3F; 438 else 439 data = 0x37; 440 viafb_i2c_writebyte(viaparinfo->chip_info-> 441 tmds_chip_info.i2c_port, 442 viaparinfo->chip_info-> 443 tmds_chip_info.tmds_chip_slave_addr, 444 0x08, data); 445 } 446 } 447 break; 448 449 case INTERFACE_DFP_HIGH: 450 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) 451 via_write_reg_mask(VIACR, CR97, 0x03, 0x03); 452 453 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); 454 break; 455 456 case INTERFACE_DFP_LOW: 457 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 458 break; 459 460 dvi_patch_skew_dvp_low(); 461 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20); 462 break; 463 464 case INTERFACE_TMDS: 465 /* Turn on Display period in the panel path. */ 466 viafb_write_reg_mask(CR91, VIACR, 0, BIT7); 467 468 /* Turn on TMDS power. */ 469 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3); 470 break; 471 } 472 473 if (viaparinfo->tmds_setting_info->iga_path == IGA2) { 474 /* Disable LCD Scaling */ 475 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); 476 } 477} 478